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authorBen Hutchings <ben.hutchings@codethink.co.uk>2015-03-02 19:52:00 -0500
committerDavid S. Miller <davem@davemloft.net>2015-03-02 21:30:56 -0500
commit7d7355f58ba4f9d68d2fb79864bab4ccb618e4e1 (patch)
tree79a7efdc9a433f1c5f05651adc70c2579760c313 /drivers/net/ethernet
parenteee617a1c35dbf598690879f13dc3df548fd6ea6 (diff)
sh_eth: Ensure proper ordering of descriptor active bit write/read
When submitting a DMA descriptor, the active bit must be written last. When reading a completed DMA descriptor, the active bit must be read first. Add memory barriers to ensure that this ordering is maintained. Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet')
-rw-r--r--drivers/net/ethernet/renesas/sh_eth.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index 654b48d1e61a..5c212a833bcf 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -1410,6 +1410,8 @@ static int sh_eth_txfree(struct net_device *ndev)
1410 txdesc = &mdp->tx_ring[entry]; 1410 txdesc = &mdp->tx_ring[entry];
1411 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) 1411 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1412 break; 1412 break;
1413 /* TACT bit must be checked before all the following reads */
1414 rmb();
1413 /* Free the original skb. */ 1415 /* Free the original skb. */
1414 if (mdp->tx_skbuff[entry]) { 1416 if (mdp->tx_skbuff[entry]) {
1415 dma_unmap_single(&ndev->dev, txdesc->addr, 1417 dma_unmap_single(&ndev->dev, txdesc->addr,
@@ -1447,6 +1449,8 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1447 limit = boguscnt; 1449 limit = boguscnt;
1448 rxdesc = &mdp->rx_ring[entry]; 1450 rxdesc = &mdp->rx_ring[entry];
1449 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { 1451 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1452 /* RACT bit must be checked before all the following reads */
1453 rmb();
1450 desc_status = edmac_to_cpu(mdp, rxdesc->status); 1454 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1451 pkt_len = rxdesc->frame_length; 1455 pkt_len = rxdesc->frame_length;
1452 1456
@@ -1526,6 +1530,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1526 skb_checksum_none_assert(skb); 1530 skb_checksum_none_assert(skb);
1527 rxdesc->addr = dma_addr; 1531 rxdesc->addr = dma_addr;
1528 } 1532 }
1533 wmb(); /* RACT bit must be set after all the above writes */
1529 if (entry >= mdp->num_rx_ring - 1) 1534 if (entry >= mdp->num_rx_ring - 1)
1530 rxdesc->status |= 1535 rxdesc->status |=
1531 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); 1536 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
@@ -2195,6 +2200,7 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2195 } 2200 }
2196 txdesc->buffer_length = skb->len; 2201 txdesc->buffer_length = skb->len;
2197 2202
2203 wmb(); /* TACT bit must be set after all the above writes */
2198 if (entry >= mdp->num_tx_ring - 1) 2204 if (entry >= mdp->num_tx_ring - 1)
2199 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); 2205 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2200 else 2206 else