stmmac: code tidy-up

This patch tidies up the code. I have run Linden (and verified with checkpatch)
many part of the driver trying to reorganize some sections respecting the
codying-style rules in the points where it was not done.

Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 34 insertions, 35 deletions

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
index 57f4e8f607e9..c12aabb8cf93 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
@@ -99,18 +99,18 @@ enum power_event {
 #define GMAC_S_R_GMII   0x000000d8      /* SGMII RGMII status */
 
 /* AN Configuration defines */
-#define GMAC_AN_CTRL_RAN        0x00000200 /* Restart Auto-Negotiation */
-#define GMAC_AN_CTRL_ANE        0x00001000 /* Auto-Negotiation Enable */
-#define GMAC_AN_CTRL_ELE        0x00004000 /* External Loopback Enable */
-#define GMAC_AN_CTRL_ECD        0x00010000 /* Enable Comma Detect */
-#define GMAC_AN_CTRL_LR 0x00020000 /* Lock to Reference */
-#define GMAC_AN_CTRL_SGMRAL     0x00040000 /* SGMII RAL Control */
+#define GMAC_AN_CTRL_RAN        0x00000200      /* Restart Auto-Negotiation */
+#define GMAC_AN_CTRL_ANE        0x00001000      /* Auto-Negotiation Enable */
+#define GMAC_AN_CTRL_ELE        0x00004000      /* External Loopback Enable */
+#define GMAC_AN_CTRL_ECD        0x00010000      /* Enable Comma Detect */
+#define GMAC_AN_CTRL_LR         0x00020000      /* Lock to Reference */
+#define GMAC_AN_CTRL_SGMRAL     0x00040000      /* SGMII RAL Control */
 
 /* AN Status defines */
-#define GMAC_AN_STATUS_LS       0x00000004 /* Link Status 0:down 1:up */
-#define GMAC_AN_STATUS_ANA      0x00000008 /* Auto-Negotiation Ability */
-#define GMAC_AN_STATUS_ANC      0x00000020 /* Auto-Negotiation Complete */
-#define GMAC_AN_STATUS_ES       0x00000100 /* Extended Status */
+#define GMAC_AN_STATUS_LS       0x00000004      /* Link Status 0:down 1:up */
+#define GMAC_AN_STATUS_ANA      0x00000008      /* Auto-Negotiation Ability */
+#define GMAC_AN_STATUS_ANC      0x00000020      /* Auto-Negotiation Complete */
+#define GMAC_AN_STATUS_ES       0x00000100      /* Extended Status */
 
 /* Register 54 (SGMII/RGMII status register) */
 #define GMAC_S_R_GMII_LINK              0x8
@@ -127,8 +127,8 @@ enum power_event {
 #define GMAC_ANE_PSE_SHIFT      7
 
  /* GMAC Configuration defines */
-#define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */
-#define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */
+#define GMAC_CONTROL_TC 0x01000000      /* Transmit Conf. in RGMII/SGMII */
+#define GMAC_CONTROL_WD 0x00800000      /* Disable Watchdog on receive */
 
 /* GMAC Configuration defines */
 #define GMAC_CONTROL_TC 0x01000000      /* Transmit Conf. in RGMII/SGMII */
@@ -141,19 +141,19 @@ enum inter_frame_gap {
         GMAC_CONTROL_IFG_80 = 0x00020000,
         GMAC_CONTROL_IFG_40 = 0x000e0000,
 };
-#define GMAC_CONTROL_DCRS       0x00010000 /* Disable carrier sense during tx */
-#define GMAC_CONTROL_PS         0x00008000 /* Port Select 0:GMI 1:MII */
-#define GMAC_CONTROL_FES        0x00004000 /* Speed 0:10 1:100 */
-#define GMAC_CONTROL_DO         0x00002000 /* Disable Rx Own */
-#define GMAC_CONTROL_LM         0x00001000 /* Loop-back mode */
-#define GMAC_CONTROL_DM         0x00000800 /* Duplex Mode */
-#define GMAC_CONTROL_IPC        0x00000400 /* Checksum Offload */
-#define GMAC_CONTROL_DR         0x00000200 /* Disable Retry */
-#define GMAC_CONTROL_LUD        0x00000100 /* Link up/down */
-#define GMAC_CONTROL_ACS        0x00000080 /* Automatic Pad/FCS Stripping */
-#define GMAC_CONTROL_DC         0x00000010 /* Deferral Check */
-#define GMAC_CONTROL_TE         0x00000008 /* Transmitter Enable */
-#define GMAC_CONTROL_RE         0x00000004 /* Receiver Enable */
+#define GMAC_CONTROL_DCRS       0x00010000      /* Disable carrier sense */
+#define GMAC_CONTROL_PS         0x00008000      /* Port Select 0:GMI 1:MII */
+#define GMAC_CONTROL_FES        0x00004000      /* Speed 0:10 1:100 */
+#define GMAC_CONTROL_DO         0x00002000      /* Disable Rx Own */
+#define GMAC_CONTROL_LM         0x00001000      /* Loop-back mode */
+#define GMAC_CONTROL_DM         0x00000800      /* Duplex Mode */
+#define GMAC_CONTROL_IPC        0x00000400      /* Checksum Offload */
+#define GMAC_CONTROL_DR         0x00000200      /* Disable Retry */
+#define GMAC_CONTROL_LUD        0x00000100      /* Link up/down */
+#define GMAC_CONTROL_ACS        0x00000080      /* Auto Pad/FCS Stripping */
+#define GMAC_CONTROL_DC         0x00000010      /* Deferral Check */
+#define GMAC_CONTROL_TE         0x00000008      /* Transmitter Enable */
+#define GMAC_CONTROL_RE         0x00000004      /* Receiver Enable */
 
 #define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \
                         GMAC_CONTROL_JE | GMAC_CONTROL_BE)
@@ -184,16 +184,16 @@ enum inter_frame_gap {
 #define DMA_BUS_MODE_SFT_RESET  0x00000001      /* Software Reset */
 #define DMA_BUS_MODE_DA         0x00000002      /* Arbitration scheme */
 #define DMA_BUS_MODE_DSL_MASK   0x0000007c      /* Descriptor Skip Length */
-#define DMA_BUS_MODE_DSL_SHIFT  2       /*   (in DWORDS)      */
+#define DMA_BUS_MODE_DSL_SHIFT  2               /*   (in DWORDS)      */
 /* Programmable burst length (passed thorugh platform)*/
 #define DMA_BUS_MODE_PBL_MASK   0x00003f00      /* Programmable Burst Len */
 #define DMA_BUS_MODE_PBL_SHIFT  8
 #define DMA_BUS_MODE_ATDS       0x00000080      /* Alternate Descriptor Size */
 
 enum rx_tx_priority_ratio {
-        double_ratio = 0x00004000,      /*2:1 */
-        triple_ratio = 0x00008000,      /*3:1 */
-        quadruple_ratio = 0x0000c000,   /*4:1 */
+        double_ratio = 0x00004000,      /* 2:1 */
+        triple_ratio = 0x00008000,      /* 3:1 */
+        quadruple_ratio = 0x0000c000,   /* 4:1 */
 };
 
 #define DMA_BUS_MODE_FB         0x00010000      /* Fixed burst */
@@ -213,9 +213,10 @@ enum rx_tx_priority_ratio {
 #define DMA_BUS_FB                0x00010000    /* Fixed Burst */
 
 /* DMA operation mode defines (start/stop tx/rx are placed in common header)*/
-#define DMA_CONTROL_DT          0x04000000 /* Disable Drop TCP/IP csum error */
-#define DMA_CONTROL_RSF         0x02000000 /* Receive Store and Forward */
-#define DMA_CONTROL_DFF         0x01000000 /* Disaable flushing */
+/* Disable Drop TCP/IP csum error */
+#define DMA_CONTROL_DT          0x04000000
+#define DMA_CONTROL_RSF         0x02000000      /* Receive Store and Forward */
+#define DMA_CONTROL_DFF         0x01000000      /* Disaable flushing */
 /* Threshold for Activating the FC */
 enum rfa {
         act_full_minus_1 = 0x00800000,
@@ -230,7 +231,7 @@ enum rfd {
         deac_full_minus_3 = 0x00401000,
         deac_full_minus_4 = 0x00401800,
 };
-#define DMA_CONTROL_TSF         0x00200000 /* Transmit  Store and Forward */
+#define DMA_CONTROL_TSF 0x00200000      /* Transmit  Store and Forward */
 
 enum ttc_control {
         DMA_CONTROL_TTC_64 = 0x00000000,
@@ -264,7 +265,5 @@ enum rtc_control {
 #define GMAC_MMC_TX_INTR   0x108
 #define GMAC_MMC_RX_CSUM_OFFLOAD   0x208
 
-
-
 extern const struct stmmac_dma_ops dwmac1000_dma_ops;
 #endif /* __DWMAC1000_H__ */