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authorKamlakant Patel <kamlakant.patel@broadcom.com>2012-11-13 20:41:38 -0500
committerDavid S. Miller <davem@davemloft.net>2012-11-14 21:50:10 -0500
commit769ce4c95e8f77c1d5df82194e54df49d28830c5 (patch)
treee1918111ed5a87924dc7126baba6454220ebd4fb /drivers/net/ethernet/smsc
parent71c6c837a0fe9d291e0764503f09dac0fec59ce1 (diff)
net/smsc911x: Fix ready check in cases where WORD_SWAP is needed
The chip ready check added by the commit 3ac3546e [Always wait for the chip to be ready] does not work when the register read/write is word swapped. This check has been added before the WORD_SWAP register is programmed, so we need to check for swapped register value as well. Bit 16 is marked as RESERVED in SMSC datasheet, Steve Glendinning <steve@shawell.net> checked with SMSC and wrote: The chip architects have concluded we should be reading PMT_CTRL until we see any of bits 0, 8, 16 or 24 set. Then we should read BYTE_TEST to check the byte order is correct (as we already do). The rationale behind this is that some of the chip variants have word order swapping features too, so the READY bit could actually be in any of the 4 possible locations. The architects have confirmed that if any of these 4 positions is set the chip is ready. The other 3 locations will either never be set or can only go high after READY does (so also indicate the device is ready). This change will check for the READY bit at the 16th position. We do not check the other two cases (bit 8 and 24) since the driver does not support byte-swapped register read/write. Signed-off-by: Kamlakant Patel <kamlakant.patel@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/smsc')
-rw-r--r--drivers/net/ethernet/smsc/smsc911x.c17
1 files changed, 15 insertions, 2 deletions
diff --git a/drivers/net/ethernet/smsc/smsc911x.c b/drivers/net/ethernet/smsc/smsc911x.c
index 62d1baf111ea..c53c0f4e2ce3 100644
--- a/drivers/net/ethernet/smsc/smsc911x.c
+++ b/drivers/net/ethernet/smsc/smsc911x.c
@@ -2110,7 +2110,7 @@ static void __devinit smsc911x_read_mac_address(struct net_device *dev)
2110static int __devinit smsc911x_init(struct net_device *dev) 2110static int __devinit smsc911x_init(struct net_device *dev)
2111{ 2111{
2112 struct smsc911x_data *pdata = netdev_priv(dev); 2112 struct smsc911x_data *pdata = netdev_priv(dev);
2113 unsigned int byte_test; 2113 unsigned int byte_test, mask;
2114 unsigned int to = 100; 2114 unsigned int to = 100;
2115 2115
2116 SMSC_TRACE(pdata, probe, "Driver Parameters:"); 2116 SMSC_TRACE(pdata, probe, "Driver Parameters:");
@@ -2130,9 +2130,22 @@ static int __devinit smsc911x_init(struct net_device *dev)
2130 /* 2130 /*
2131 * poll the READY bit in PMT_CTRL. Any other access to the device is 2131 * poll the READY bit in PMT_CTRL. Any other access to the device is
2132 * forbidden while this bit isn't set. Try for 100ms 2132 * forbidden while this bit isn't set. Try for 100ms
2133 *
2134 * Note that this test is done before the WORD_SWAP register is
2135 * programmed. So in some configurations the READY bit is at 16 before
2136 * WORD_SWAP is written to. This issue is worked around by waiting
2137 * until either bit 0 or bit 16 gets set in PMT_CTRL.
2138 *
2139 * SMSC has confirmed that checking bit 16 (marked as reserved in
2140 * the datasheet) is fine since these bits "will either never be set
2141 * or can only go high after READY does (so also indicate the device
2142 * is ready)".
2133 */ 2143 */
2134 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to) 2144
2145 mask = PMT_CTRL_READY_ | swahw32(PMT_CTRL_READY_);
2146 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & mask) && --to)
2135 udelay(1000); 2147 udelay(1000);
2148
2136 if (to == 0) { 2149 if (to == 0) {
2137 pr_err("Device not READY in 100ms aborting\n"); 2150 pr_err("Device not READY in 100ms aborting\n");
2138 return -ENODEV; 2151 return -ENODEV;