diff options
author | Ben Hutchings <bhutchings@solarflare.com> | 2012-09-19 12:47:08 -0400 |
---|---|---|
committer | Ben Hutchings <bhutchings@solarflare.com> | 2013-08-29 13:12:16 -0400 |
commit | 9c51716512c1e73523b685f389fbb748c15436e4 (patch) | |
tree | 154b84e2e6a024e43f6673553d3528e0b5314c31 /drivers/net/ethernet/sfc/io.h | |
parent | ba8977bdb20d7ae72ec6fddc1c081ca2d56852cb (diff) |
sfc: Add EF10 register and structure definitions
Also update comments and assertions in io.h:
- EF10 does not have a general BIU collector and does not have the
bug affecting TIMER_COMMAND_REG[0] on Falcon/Siena
- The WPTR field moved within RX_DESC_UPD_REG and TX_DESC_UPD_REG.
Adjust efx_writed_page() accordingly
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Diffstat (limited to 'drivers/net/ethernet/sfc/io.h')
-rw-r--r-- | drivers/net/ethernet/sfc/io.h | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/drivers/net/ethernet/sfc/io.h b/drivers/net/ethernet/sfc/io.h index 19e8b95b7af6..416ee4a469c4 100644 --- a/drivers/net/ethernet/sfc/io.h +++ b/drivers/net/ethernet/sfc/io.h | |||
@@ -20,7 +20,7 @@ | |||
20 | * | 20 | * |
21 | ************************************************************************** | 21 | ************************************************************************** |
22 | * | 22 | * |
23 | * Notes on locking strategy: | 23 | * Notes on locking strategy for the Falcon architecture: |
24 | * | 24 | * |
25 | * Many CSRs are very wide and cannot be read or written atomically. | 25 | * Many CSRs are very wide and cannot be read or written atomically. |
26 | * Writes from the host are buffered by the Bus Interface Unit (BIU) | 26 | * Writes from the host are buffered by the Bus Interface Unit (BIU) |
@@ -54,6 +54,12 @@ | |||
54 | * register while the collector already holds values for some other | 54 | * register while the collector already holds values for some other |
55 | * register, the write is discarded and the collector maintains its | 55 | * register, the write is discarded and the collector maintains its |
56 | * current state. | 56 | * current state. |
57 | * | ||
58 | * The EF10 architecture exposes very few registers to the host and | ||
59 | * most of them are only 32 bits wide. The only exceptions are the MC | ||
60 | * doorbell register pair, which has its own latching, and | ||
61 | * TX_DESC_UPD, which works in a similar way to the Falcon | ||
62 | * architecture. | ||
57 | */ | 63 | */ |
58 | 64 | ||
59 | #if BITS_PER_LONG == 64 | 65 | #if BITS_PER_LONG == 64 |
@@ -237,8 +243,8 @@ static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value, | |||
237 | BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \ | 243 | BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \ |
238 | page) | 244 | page) |
239 | 245 | ||
240 | /* Write a page-mapped 32-bit CSR (EVQ_RPTR or the high bits of | 246 | /* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the |
241 | * RX_DESC_UPD or TX_DESC_UPD) | 247 | * high bits of RX_DESC_UPD or TX_DESC_UPD) |
242 | */ | 248 | */ |
243 | static inline void | 249 | static inline void |
244 | _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value, | 250 | _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value, |
@@ -249,8 +255,12 @@ _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value, | |||
249 | #define efx_writed_page(efx, value, reg, page) \ | 255 | #define efx_writed_page(efx, value, reg, page) \ |
250 | _efx_writed_page(efx, value, \ | 256 | _efx_writed_page(efx, value, \ |
251 | reg + \ | 257 | reg + \ |
252 | BUILD_BUG_ON_ZERO((reg) != 0x400 && (reg) != 0x83c \ | 258 | BUILD_BUG_ON_ZERO((reg) != 0x400 && \ |
253 | && (reg) != 0xa1c), \ | 259 | (reg) != 0x420 && \ |
260 | (reg) != 0x830 && \ | ||
261 | (reg) != 0x83c && \ | ||
262 | (reg) != 0xa18 && \ | ||
263 | (reg) != 0xa1c), \ | ||
254 | page) | 264 | page) |
255 | 265 | ||
256 | /* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug | 266 | /* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug |