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authorBen Hutchings <bhutchings@solarflare.com>2012-01-05 20:08:24 -0500
committerBen Hutchings <bhutchings@solarflare.com>2012-01-26 19:10:51 -0500
commitf70d1847348e9548a9a56e4434946315bca297c8 (patch)
treed8bed0762a2393374348cf501cc1cdb0195c6896 /drivers/net/ethernet/sfc/falcon.c
parent0fb53faa2e6fe67a76b8cfc6eb70a88d9d623648 (diff)
Partly revert "sfc: Handle serious errors in exactly one interrupt handler"
This reverts commit 6369545945b90daa1a73fca174da9194c398417c in drivers/net/ethernet/sfc/falcon.c. Unlike the INT_ISR0 register on later controller revisions, the NET_IVEC_INT_Q bits written to memory are only ever set for interrupting event queues, not for any other interrupt sources. By definition there can only be one legacy interrupt handler per function, so there is no need to worry about detecting a fatal interrupt more than once. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Diffstat (limited to 'drivers/net/ethernet/sfc/falcon.c')
-rw-r--r--drivers/net/ethernet/sfc/falcon.c13
1 files changed, 5 insertions, 8 deletions
diff --git a/drivers/net/ethernet/sfc/falcon.c b/drivers/net/ethernet/sfc/falcon.c
index 0b7880b0b8fc..b4e91edec0fa 100644
--- a/drivers/net/ethernet/sfc/falcon.c
+++ b/drivers/net/ethernet/sfc/falcon.c
@@ -174,19 +174,16 @@ irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
174 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", 174 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
175 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); 175 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
176 176
177 /* Check to see if we have a serious error condition */
178 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
179 if (unlikely(syserr))
180 return efx_nic_fatal_interrupt(efx);
181
177 /* Determine interrupting queues, clear interrupt status 182 /* Determine interrupting queues, clear interrupt status
178 * register and acknowledge the device interrupt. 183 * register and acknowledge the device interrupt.
179 */ 184 */
180 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS); 185 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
181 queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q); 186 queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
182
183 /* Check to see if we have a serious error condition */
184 if (queues & (1U << efx->fatal_irq_level)) {
185 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
186 if (unlikely(syserr))
187 return efx_nic_fatal_interrupt(efx);
188 }
189
190 EFX_ZERO_OWORD(*int_ker); 187 EFX_ZERO_OWORD(*int_ker);
191 wmb(); /* Ensure the vector is cleared before interrupt ack */ 188 wmb(); /* Ensure the vector is cleared before interrupt ack */
192 falcon_irq_ack_a1(efx); 189 falcon_irq_ack_a1(efx);