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authorChun-Hao Lin <hau@realtek.com>2014-10-07 03:10:41 -0400
committerDavid S. Miller <davem@davemloft.net>2014-10-08 15:58:45 -0400
commit935e2218d5a0fade1645982fb034eee37f100f11 (patch)
treea47e162c63c4e69ecd15621d54a6bd6532a6d29e /drivers/net/ethernet/realtek
parent28b7deae75642c51f097391765fd39ff0dd6ce95 (diff)
r8169:add support for RTL8168EP
RTL8168EP is Realtek PCIe Gigabit Ethernet controller with DASH support. It is a successor chip of RTL8168DP. For RTL8168EP, the read/write ocp register is via eri channel type 2, so I move ocp_xxx() related functions under rtl_eri_xxx. And use r8168dp_ocp_xxx() for RTL8168DP ocp read/write, r8168ep_ocp_xxx() for RTL8168EP ocp read/write. The way of checking dash enable is different with RTL8168DP. I use r8168dp_check_dash()for RTL8168DP and r8168ep_check_dash() for RTL8168EP, to check if dash is enabled. The driver_start() and driver_stop() of RTL8168EP is also different with RTL8168DP. I use rtl8168dp_driver_xxx() for RTL8168DP and rtl8168ep_driver_xxx for RTL8168EP. Right now, RTL8168EP phy mcu did not need firmware code patch, so I did not add firmware code for it. so I did not add firmware code for it. Signed-off-by: Chun-Hao Lin <hau@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/realtek')
-rw-r--r--drivers/net/ethernet/realtek/r8169.c561
1 files changed, 517 insertions, 44 deletions
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 54476ba42477..cf154f74cba1 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -155,6 +155,9 @@ enum mac_version {
155 RTL_GIGA_MAC_VER_46, 155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47, 156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48, 157 RTL_GIGA_MAC_VER_48,
158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
158 RTL_GIGA_MAC_NONE = 0xff, 161 RTL_GIGA_MAC_NONE = 0xff,
159}; 162};
160 163
@@ -302,6 +305,15 @@ static const struct {
302 [RTL_GIGA_MAC_VER_48] = 305 [RTL_GIGA_MAC_VER_48] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2, 306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
304 JUMBO_1K, false), 307 JUMBO_1K, false),
308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
305}; 317};
306#undef _R 318#undef _R
307 319
@@ -400,6 +412,10 @@ enum rtl_registers {
400 FuncEvent = 0xf0, 412 FuncEvent = 0xf0,
401 FuncEventMask = 0xf4, 413 FuncEventMask = 0xf4,
402 FuncPresetState = 0xf8, 414 FuncPresetState = 0xf8,
415 IBCR0 = 0xf8,
416 IBCR2 = 0xf9,
417 IBIMR0 = 0xfa,
418 IBISR0 = 0xfb,
403 FuncForceEvent = 0xfc, 419 FuncForceEvent = 0xfc,
404}; 420};
405 421
@@ -467,6 +483,7 @@ enum rtl8168_registers {
467#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 483#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
468#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 484#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
469#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 485#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
486#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
470#define ERIAR_MASK_SHIFT 12 487#define ERIAR_MASK_SHIFT 12
471#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 488#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
472#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 489#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
@@ -935,40 +952,6 @@ static const struct rtl_cond name = { \
935 \ 952 \
936static bool name ## _check(struct rtl8169_private *tp) 953static bool name ## _check(struct rtl8169_private *tp)
937 954
938DECLARE_RTL_COND(rtl_ocpar_cond)
939{
940 void __iomem *ioaddr = tp->mmio_addr;
941
942 return RTL_R32(OCPAR) & OCPAR_FLAG;
943}
944
945static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
946{
947 void __iomem *ioaddr = tp->mmio_addr;
948
949 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
950
951 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
952 RTL_R32(OCPDR) : ~0;
953}
954
955static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
956{
957 void __iomem *ioaddr = tp->mmio_addr;
958
959 RTL_W32(OCPDR, data);
960 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
961
962 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
963}
964
965DECLARE_RTL_COND(rtl_eriar_cond)
966{
967 void __iomem *ioaddr = tp->mmio_addr;
968
969 return RTL_R32(ERIAR) & ERIAR_FLAG;
970}
971
972static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 955static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
973{ 956{
974 if (reg & 0xffff0001) { 957 if (reg & 0xffff0001) {
@@ -1110,6 +1093,13 @@ static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1110 return value; 1093 return value;
1111} 1094}
1112 1095
1096DECLARE_RTL_COND(rtl_ocpar_cond)
1097{
1098 void __iomem *ioaddr = tp->mmio_addr;
1099
1100 return RTL_R32(OCPAR) & OCPAR_FLAG;
1101}
1102
1113static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 1103static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1114{ 1104{
1115 void __iomem *ioaddr = tp->mmio_addr; 1105 void __iomem *ioaddr = tp->mmio_addr;
@@ -1245,6 +1235,13 @@ static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1245 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0; 1235 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1246} 1236}
1247 1237
1238DECLARE_RTL_COND(rtl_eriar_cond)
1239{
1240 void __iomem *ioaddr = tp->mmio_addr;
1241
1242 return RTL_R32(ERIAR) & ERIAR_FLAG;
1243}
1244
1248static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1245static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1249 u32 val, int type) 1246 u32 val, int type)
1250{ 1247{
@@ -1276,6 +1273,73 @@ static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1276 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type); 1273 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1277} 1274}
1278 1275
1276static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1277{
1278 void __iomem *ioaddr = tp->mmio_addr;
1279
1280 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1281 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1282 RTL_R32(OCPDR) : ~0;
1283}
1284
1285static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1286{
1287 return rtl_eri_read(tp, reg, ERIAR_OOB);
1288}
1289
1290static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1291{
1292 switch (tp->mac_version) {
1293 case RTL_GIGA_MAC_VER_27:
1294 case RTL_GIGA_MAC_VER_28:
1295 case RTL_GIGA_MAC_VER_31:
1296 return r8168dp_ocp_read(tp, mask, reg);
1297 case RTL_GIGA_MAC_VER_49:
1298 case RTL_GIGA_MAC_VER_50:
1299 case RTL_GIGA_MAC_VER_51:
1300 return r8168ep_ocp_read(tp, mask, reg);
1301 default:
1302 BUG();
1303 return ~0;
1304 }
1305}
1306
1307static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1308 u32 data)
1309{
1310 void __iomem *ioaddr = tp->mmio_addr;
1311
1312 RTL_W32(OCPDR, data);
1313 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1314 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1315}
1316
1317static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1318 u32 data)
1319{
1320 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1321 data, ERIAR_OOB);
1322}
1323
1324static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1325{
1326 switch (tp->mac_version) {
1327 case RTL_GIGA_MAC_VER_27:
1328 case RTL_GIGA_MAC_VER_28:
1329 case RTL_GIGA_MAC_VER_31:
1330 r8168dp_ocp_write(tp, mask, reg, data);
1331 break;
1332 case RTL_GIGA_MAC_VER_49:
1333 case RTL_GIGA_MAC_VER_50:
1334 case RTL_GIGA_MAC_VER_51:
1335 r8168ep_ocp_write(tp, mask, reg, data);
1336 break;
1337 default:
1338 BUG();
1339 break;
1340 }
1341}
1342
1279static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) 1343static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1280{ 1344{
1281 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC); 1345 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
@@ -1301,27 +1365,116 @@ DECLARE_RTL_COND(rtl_ocp_read_cond)
1301 return ocp_read(tp, 0x0f, reg) & 0x00000800; 1365 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1302} 1366}
1303 1367
1304static void rtl8168_driver_start(struct rtl8169_private *tp) 1368DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1305{ 1369{
1306 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); 1370 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1371}
1372
1373DECLARE_RTL_COND(rtl_ocp_tx_cond)
1374{
1375 void __iomem *ioaddr = tp->mmio_addr;
1376
1377 return RTL_R8(IBISR0) & 0x02;
1378}
1307 1379
1380static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1381{
1382 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1308 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10); 1383 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1309} 1384}
1310 1385
1311static void rtl8168_driver_stop(struct rtl8169_private *tp) 1386static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1312{ 1387{
1313 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1388 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1389 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1390 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1391}
1392
1393static void rtl8168_driver_start(struct rtl8169_private *tp)
1394{
1395 switch (tp->mac_version) {
1396 case RTL_GIGA_MAC_VER_27:
1397 case RTL_GIGA_MAC_VER_28:
1398 case RTL_GIGA_MAC_VER_31:
1399 rtl8168dp_driver_start(tp);
1400 break;
1401 case RTL_GIGA_MAC_VER_49:
1402 case RTL_GIGA_MAC_VER_50:
1403 case RTL_GIGA_MAC_VER_51:
1404 rtl8168ep_driver_start(tp);
1405 break;
1406 default:
1407 BUG();
1408 break;
1409 }
1410}
1314 1411
1412static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1413{
1414 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1315 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10); 1415 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1316} 1416}
1317 1417
1318static int r8168_check_dash(struct rtl8169_private *tp) 1418static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1419{
1420 void __iomem *ioaddr = tp->mmio_addr;
1421
1422 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1423 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1424 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1425 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1426 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1427 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1428 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1429}
1430
1431static void rtl8168_driver_stop(struct rtl8169_private *tp)
1432{
1433 switch (tp->mac_version) {
1434 case RTL_GIGA_MAC_VER_27:
1435 case RTL_GIGA_MAC_VER_28:
1436 case RTL_GIGA_MAC_VER_31:
1437 rtl8168dp_driver_stop(tp);
1438 break;
1439 case RTL_GIGA_MAC_VER_49:
1440 case RTL_GIGA_MAC_VER_50:
1441 case RTL_GIGA_MAC_VER_51:
1442 rtl8168ep_driver_stop(tp);
1443 break;
1444 default:
1445 BUG();
1446 break;
1447 }
1448}
1449
1450static int r8168dp_check_dash(struct rtl8169_private *tp)
1319{ 1451{
1320 u16 reg = rtl8168_get_ocp_reg(tp); 1452 u16 reg = rtl8168_get_ocp_reg(tp);
1321 1453
1322 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0; 1454 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1323} 1455}
1324 1456
1457static int r8168ep_check_dash(struct rtl8169_private *tp)
1458{
1459 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1460}
1461
1462static int r8168_check_dash(struct rtl8169_private *tp)
1463{
1464 switch (tp->mac_version) {
1465 case RTL_GIGA_MAC_VER_27:
1466 case RTL_GIGA_MAC_VER_28:
1467 case RTL_GIGA_MAC_VER_31:
1468 return r8168dp_check_dash(tp);
1469 case RTL_GIGA_MAC_VER_49:
1470 case RTL_GIGA_MAC_VER_50:
1471 case RTL_GIGA_MAC_VER_51:
1472 return r8168ep_check_dash(tp);
1473 default:
1474 return 0;
1475 }
1476}
1477
1325struct exgmac_reg { 1478struct exgmac_reg {
1326 u16 addr; 1479 u16 addr;
1327 u16 mask; 1480 u16 mask;
@@ -1553,6 +1706,9 @@ static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1553 case RTL_GIGA_MAC_VER_46: 1706 case RTL_GIGA_MAC_VER_46:
1554 case RTL_GIGA_MAC_VER_47: 1707 case RTL_GIGA_MAC_VER_47:
1555 case RTL_GIGA_MAC_VER_48: 1708 case RTL_GIGA_MAC_VER_48:
1709 case RTL_GIGA_MAC_VER_49:
1710 case RTL_GIGA_MAC_VER_50:
1711 case RTL_GIGA_MAC_VER_51:
1556 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2) 1712 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1557 wolopts |= WAKE_MAGIC; 1713 wolopts |= WAKE_MAGIC;
1558 break; 1714 break;
@@ -1620,6 +1776,9 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1620 case RTL_GIGA_MAC_VER_46: 1776 case RTL_GIGA_MAC_VER_46:
1621 case RTL_GIGA_MAC_VER_47: 1777 case RTL_GIGA_MAC_VER_47:
1622 case RTL_GIGA_MAC_VER_48: 1778 case RTL_GIGA_MAC_VER_48:
1779 case RTL_GIGA_MAC_VER_49:
1780 case RTL_GIGA_MAC_VER_50:
1781 case RTL_GIGA_MAC_VER_51:
1623 tmp = ARRAY_SIZE(cfg) - 1; 1782 tmp = ARRAY_SIZE(cfg) - 1;
1624 if (wolopts & WAKE_MAGIC) 1783 if (wolopts & WAKE_MAGIC)
1625 rtl_w0w1_eri(tp, 1784 rtl_w0w1_eri(tp,
@@ -2126,6 +2285,11 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2126 u32 val; 2285 u32 val;
2127 int mac_version; 2286 int mac_version;
2128 } mac_info[] = { 2287 } mac_info[] = {
2288 /* 8168EP family. */
2289 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2290 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2291 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2292
2129 /* 8168H family. */ 2293 /* 8168H family. */
2130 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 }, 2294 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2131 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 }, 2295 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
@@ -3741,6 +3905,139 @@ static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3741 rtl_writephy(tp, 0x1f, 0x0000); 3905 rtl_writephy(tp, 0x1f, 0x0000);
3742} 3906}
3743 3907
3908static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3909{
3910 /* Enable PHY auto speed down */
3911 rtl_writephy(tp, 0x1f, 0x0a44);
3912 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3913 rtl_writephy(tp, 0x1f, 0x0000);
3914
3915 /* patch 10M & ALDPS */
3916 rtl_writephy(tp, 0x1f, 0x0bcc);
3917 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3918 rtl_writephy(tp, 0x1f, 0x0a44);
3919 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3920 rtl_writephy(tp, 0x1f, 0x0a43);
3921 rtl_writephy(tp, 0x13, 0x8084);
3922 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3923 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3924 rtl_writephy(tp, 0x1f, 0x0000);
3925
3926 /* Enable EEE auto-fallback function */
3927 rtl_writephy(tp, 0x1f, 0x0a4b);
3928 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3929 rtl_writephy(tp, 0x1f, 0x0000);
3930
3931 /* Enable UC LPF tune function */
3932 rtl_writephy(tp, 0x1f, 0x0a43);
3933 rtl_writephy(tp, 0x13, 0x8012);
3934 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3935 rtl_writephy(tp, 0x1f, 0x0000);
3936
3937 /* set rg_sel_sdm_rate */
3938 rtl_writephy(tp, 0x1f, 0x0c42);
3939 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3940 rtl_writephy(tp, 0x1f, 0x0000);
3941
3942 /* Check ALDPS bit, disable it if enabled */
3943 rtl_writephy(tp, 0x1f, 0x0a43);
3944 if (rtl_readphy(tp, 0x10) & 0x0004)
3945 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3946
3947 rtl_writephy(tp, 0x1f, 0x0000);
3948}
3949
3950static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3951{
3952 /* patch 10M & ALDPS */
3953 rtl_writephy(tp, 0x1f, 0x0bcc);
3954 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3955 rtl_writephy(tp, 0x1f, 0x0a44);
3956 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3957 rtl_writephy(tp, 0x1f, 0x0a43);
3958 rtl_writephy(tp, 0x13, 0x8084);
3959 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3960 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3961 rtl_writephy(tp, 0x1f, 0x0000);
3962
3963 /* Enable UC LPF tune function */
3964 rtl_writephy(tp, 0x1f, 0x0a43);
3965 rtl_writephy(tp, 0x13, 0x8012);
3966 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3967 rtl_writephy(tp, 0x1f, 0x0000);
3968
3969 /* Set rg_sel_sdm_rate */
3970 rtl_writephy(tp, 0x1f, 0x0c42);
3971 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3972 rtl_writephy(tp, 0x1f, 0x0000);
3973
3974 /* Channel estimation parameters */
3975 rtl_writephy(tp, 0x1f, 0x0a43);
3976 rtl_writephy(tp, 0x13, 0x80f3);
3977 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3978 rtl_writephy(tp, 0x13, 0x80f0);
3979 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3980 rtl_writephy(tp, 0x13, 0x80ef);
3981 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3982 rtl_writephy(tp, 0x13, 0x80f6);
3983 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3984 rtl_writephy(tp, 0x13, 0x80ec);
3985 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3986 rtl_writephy(tp, 0x13, 0x80ed);
3987 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3988 rtl_writephy(tp, 0x13, 0x80f2);
3989 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3990 rtl_writephy(tp, 0x13, 0x80f4);
3991 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3992 rtl_writephy(tp, 0x1f, 0x0a43);
3993 rtl_writephy(tp, 0x13, 0x8110);
3994 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3995 rtl_writephy(tp, 0x13, 0x810f);
3996 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3997 rtl_writephy(tp, 0x13, 0x8111);
3998 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3999 rtl_writephy(tp, 0x13, 0x8113);
4000 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4001 rtl_writephy(tp, 0x13, 0x8115);
4002 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4003 rtl_writephy(tp, 0x13, 0x810e);
4004 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4005 rtl_writephy(tp, 0x13, 0x810c);
4006 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4007 rtl_writephy(tp, 0x13, 0x810b);
4008 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4009 rtl_writephy(tp, 0x1f, 0x0a43);
4010 rtl_writephy(tp, 0x13, 0x80d1);
4011 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4012 rtl_writephy(tp, 0x13, 0x80cd);
4013 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4014 rtl_writephy(tp, 0x13, 0x80d3);
4015 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4016 rtl_writephy(tp, 0x13, 0x80d5);
4017 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4018 rtl_writephy(tp, 0x13, 0x80d7);
4019 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4020
4021 /* Force PWM-mode */
4022 rtl_writephy(tp, 0x1f, 0x0bcd);
4023 rtl_writephy(tp, 0x14, 0x5065);
4024 rtl_writephy(tp, 0x14, 0xd065);
4025 rtl_writephy(tp, 0x1f, 0x0bc8);
4026 rtl_writephy(tp, 0x12, 0x00ed);
4027 rtl_writephy(tp, 0x1f, 0x0bcd);
4028 rtl_writephy(tp, 0x14, 0x1065);
4029 rtl_writephy(tp, 0x14, 0x9065);
4030 rtl_writephy(tp, 0x14, 0x1065);
4031 rtl_writephy(tp, 0x1f, 0x0000);
4032
4033 /* Check ALDPS bit, disable it if enabled */
4034 rtl_writephy(tp, 0x1f, 0x0a43);
4035 if (rtl_readphy(tp, 0x10) & 0x0004)
4036 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4037
4038 rtl_writephy(tp, 0x1f, 0x0000);
4039}
4040
3744static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) 4041static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3745{ 4042{
3746 static const struct phy_reg phy_reg_init[] = { 4043 static const struct phy_reg phy_reg_init[] = {
@@ -3940,6 +4237,14 @@ static void rtl_hw_phy_config(struct net_device *dev)
3940 rtl8168h_2_hw_phy_config(tp); 4237 rtl8168h_2_hw_phy_config(tp);
3941 break; 4238 break;
3942 4239
4240 case RTL_GIGA_MAC_VER_49:
4241 rtl8168ep_1_hw_phy_config(tp);
4242 break;
4243 case RTL_GIGA_MAC_VER_50:
4244 case RTL_GIGA_MAC_VER_51:
4245 rtl8168ep_2_hw_phy_config(tp);
4246 break;
4247
3943 case RTL_GIGA_MAC_VER_41: 4248 case RTL_GIGA_MAC_VER_41:
3944 default: 4249 default:
3945 break; 4250 break;
@@ -4154,6 +4459,9 @@ static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4154 case RTL_GIGA_MAC_VER_46: 4459 case RTL_GIGA_MAC_VER_46:
4155 case RTL_GIGA_MAC_VER_47: 4460 case RTL_GIGA_MAC_VER_47:
4156 case RTL_GIGA_MAC_VER_48: 4461 case RTL_GIGA_MAC_VER_48:
4462 case RTL_GIGA_MAC_VER_49:
4463 case RTL_GIGA_MAC_VER_50:
4464 case RTL_GIGA_MAC_VER_51:
4157 ops->write = r8168g_mdio_write; 4465 ops->write = r8168g_mdio_write;
4158 ops->read = r8168g_mdio_read; 4466 ops->read = r8168g_mdio_read;
4159 break; 4467 break;
@@ -4212,6 +4520,9 @@ static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4212 case RTL_GIGA_MAC_VER_46: 4520 case RTL_GIGA_MAC_VER_46:
4213 case RTL_GIGA_MAC_VER_47: 4521 case RTL_GIGA_MAC_VER_47:
4214 case RTL_GIGA_MAC_VER_48: 4522 case RTL_GIGA_MAC_VER_48:
4523 case RTL_GIGA_MAC_VER_49:
4524 case RTL_GIGA_MAC_VER_50:
4525 case RTL_GIGA_MAC_VER_51:
4215 RTL_W32(RxConfig, RTL_R32(RxConfig) | 4526 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4216 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 4527 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4217 break; 4528 break;
@@ -4356,7 +4667,10 @@ static void r8168_pll_power_down(struct rtl8169_private *tp)
4356 4667
4357 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || 4668 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4358 tp->mac_version == RTL_GIGA_MAC_VER_28 || 4669 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4359 tp->mac_version == RTL_GIGA_MAC_VER_31) && 4670 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4671 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4672 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4673 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4360 r8168_check_dash(tp)) { 4674 r8168_check_dash(tp)) {
4361 return; 4675 return;
4362 } 4676 }
@@ -4387,10 +4701,13 @@ static void r8168_pll_power_down(struct rtl8169_private *tp)
4387 case RTL_GIGA_MAC_VER_44: 4701 case RTL_GIGA_MAC_VER_44:
4388 case RTL_GIGA_MAC_VER_45: 4702 case RTL_GIGA_MAC_VER_45:
4389 case RTL_GIGA_MAC_VER_46: 4703 case RTL_GIGA_MAC_VER_46:
4704 case RTL_GIGA_MAC_VER_50:
4705 case RTL_GIGA_MAC_VER_51:
4390 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); 4706 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4391 break; 4707 break;
4392 case RTL_GIGA_MAC_VER_40: 4708 case RTL_GIGA_MAC_VER_40:
4393 case RTL_GIGA_MAC_VER_41: 4709 case RTL_GIGA_MAC_VER_41:
4710 case RTL_GIGA_MAC_VER_49:
4394 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000, 4711 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4395 0xfc000000, ERIAR_EXGMAC); 4712 0xfc000000, ERIAR_EXGMAC);
4396 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); 4713 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
@@ -4415,10 +4732,13 @@ static void r8168_pll_power_up(struct rtl8169_private *tp)
4415 case RTL_GIGA_MAC_VER_44: 4732 case RTL_GIGA_MAC_VER_44:
4416 case RTL_GIGA_MAC_VER_45: 4733 case RTL_GIGA_MAC_VER_45:
4417 case RTL_GIGA_MAC_VER_46: 4734 case RTL_GIGA_MAC_VER_46:
4735 case RTL_GIGA_MAC_VER_50:
4736 case RTL_GIGA_MAC_VER_51:
4418 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0); 4737 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4419 break; 4738 break;
4420 case RTL_GIGA_MAC_VER_40: 4739 case RTL_GIGA_MAC_VER_40:
4421 case RTL_GIGA_MAC_VER_41: 4740 case RTL_GIGA_MAC_VER_41:
4741 case RTL_GIGA_MAC_VER_49:
4422 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0); 4742 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4423 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000, 4743 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4424 0x00000000, ERIAR_EXGMAC); 4744 0x00000000, ERIAR_EXGMAC);
@@ -4493,6 +4813,9 @@ static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4493 case RTL_GIGA_MAC_VER_44: 4813 case RTL_GIGA_MAC_VER_44:
4494 case RTL_GIGA_MAC_VER_45: 4814 case RTL_GIGA_MAC_VER_45:
4495 case RTL_GIGA_MAC_VER_46: 4815 case RTL_GIGA_MAC_VER_46:
4816 case RTL_GIGA_MAC_VER_49:
4817 case RTL_GIGA_MAC_VER_50:
4818 case RTL_GIGA_MAC_VER_51:
4496 ops->down = r8168_pll_power_down; 4819 ops->down = r8168_pll_power_down;
4497 ops->up = r8168_pll_power_up; 4820 ops->up = r8168_pll_power_up;
4498 break; 4821 break;
@@ -4547,6 +4870,9 @@ static void rtl_init_rxcfg(struct rtl8169_private *tp)
4547 case RTL_GIGA_MAC_VER_46: 4870 case RTL_GIGA_MAC_VER_46:
4548 case RTL_GIGA_MAC_VER_47: 4871 case RTL_GIGA_MAC_VER_47:
4549 case RTL_GIGA_MAC_VER_48: 4872 case RTL_GIGA_MAC_VER_48:
4873 case RTL_GIGA_MAC_VER_49:
4874 case RTL_GIGA_MAC_VER_50:
4875 case RTL_GIGA_MAC_VER_51:
4550 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF); 4876 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4551 break; 4877 break;
4552 default: 4878 default:
@@ -4712,6 +5038,9 @@ static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4712 case RTL_GIGA_MAC_VER_46: 5038 case RTL_GIGA_MAC_VER_46:
4713 case RTL_GIGA_MAC_VER_47: 5039 case RTL_GIGA_MAC_VER_47:
4714 case RTL_GIGA_MAC_VER_48: 5040 case RTL_GIGA_MAC_VER_48:
5041 case RTL_GIGA_MAC_VER_49:
5042 case RTL_GIGA_MAC_VER_50:
5043 case RTL_GIGA_MAC_VER_51:
4715 default: 5044 default:
4716 ops->disable = NULL; 5045 ops->disable = NULL;
4717 ops->enable = NULL; 5046 ops->enable = NULL;
@@ -4828,7 +5157,10 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp)
4828 tp->mac_version == RTL_GIGA_MAC_VER_45 || 5157 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
4829 tp->mac_version == RTL_GIGA_MAC_VER_46 || 5158 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
4830 tp->mac_version == RTL_GIGA_MAC_VER_47 || 5159 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
4831 tp->mac_version == RTL_GIGA_MAC_VER_48) { 5160 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5161 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5162 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5163 tp->mac_version == RTL_GIGA_MAC_VER_51) {
4832 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); 5164 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4833 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 5165 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4834 } else { 5166 } else {
@@ -5754,6 +6086,120 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5754 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 6086 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5755} 6087}
5756 6088
6089static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6090{
6091 void __iomem *ioaddr = tp->mmio_addr;
6092 struct pci_dev *pdev = tp->pci_dev;
6093
6094 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6095
6096 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6097 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6098 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6099 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6100
6101 rtl_csi_access_enable_1(tp);
6102
6103 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6104
6105 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6106 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6107
6108 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6109
6110 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6111
6112 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6113 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6114 RTL_W8(MaxTxPacketSize, EarlySize);
6115
6116 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6117 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6118
6119 /* Adjust EEE LED frequency */
6120 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6121
6122 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6123
6124 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6125
6126 rtl_pcie_state_l2l3_enable(tp, false);
6127}
6128
6129static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6130{
6131 void __iomem *ioaddr = tp->mmio_addr;
6132 static const struct ephy_info e_info_8168ep_1[] = {
6133 { 0x00, 0xffff, 0x10ab },
6134 { 0x06, 0xffff, 0xf030 },
6135 { 0x08, 0xffff, 0x2006 },
6136 { 0x0d, 0xffff, 0x1666 },
6137 { 0x0c, 0x3ff0, 0x0000 }
6138 };
6139
6140 /* disable aspm and clock request before access ephy */
6141 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6142 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6143 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6144
6145 rtl_hw_start_8168ep(tp);
6146}
6147
6148static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6149{
6150 void __iomem *ioaddr = tp->mmio_addr;
6151 static const struct ephy_info e_info_8168ep_2[] = {
6152 { 0x00, 0xffff, 0x10a3 },
6153 { 0x19, 0xffff, 0xfc00 },
6154 { 0x1e, 0xffff, 0x20ea }
6155 };
6156
6157 /* disable aspm and clock request before access ephy */
6158 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6159 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6160 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6161
6162 rtl_hw_start_8168ep(tp);
6163
6164 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6165 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6166}
6167
6168static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6169{
6170 void __iomem *ioaddr = tp->mmio_addr;
6171 u32 data;
6172 static const struct ephy_info e_info_8168ep_3[] = {
6173 { 0x00, 0xffff, 0x10a3 },
6174 { 0x19, 0xffff, 0x7c00 },
6175 { 0x1e, 0xffff, 0x20eb },
6176 { 0x0d, 0xffff, 0x1666 }
6177 };
6178
6179 /* disable aspm and clock request before access ephy */
6180 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6181 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6182 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6183
6184 rtl_hw_start_8168ep(tp);
6185
6186 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6187 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6188
6189 data = r8168_mac_ocp_read(tp, 0xd3e2);
6190 data &= 0xf000;
6191 data |= 0x0271;
6192 r8168_mac_ocp_write(tp, 0xd3e2, data);
6193
6194 data = r8168_mac_ocp_read(tp, 0xd3e4);
6195 data &= 0xff00;
6196 r8168_mac_ocp_write(tp, 0xd3e4, data);
6197
6198 data = r8168_mac_ocp_read(tp, 0xe860);
6199 data |= 0x0080;
6200 r8168_mac_ocp_write(tp, 0xe860, data);
6201}
6202
5757static void rtl_hw_start_8168(struct net_device *dev) 6203static void rtl_hw_start_8168(struct net_device *dev)
5758{ 6204{
5759 struct rtl8169_private *tp = netdev_priv(dev); 6205 struct rtl8169_private *tp = netdev_priv(dev);
@@ -5869,6 +6315,18 @@ static void rtl_hw_start_8168(struct net_device *dev)
5869 rtl_hw_start_8168h_1(tp); 6315 rtl_hw_start_8168h_1(tp);
5870 break; 6316 break;
5871 6317
6318 case RTL_GIGA_MAC_VER_49:
6319 rtl_hw_start_8168ep_1(tp);
6320 break;
6321
6322 case RTL_GIGA_MAC_VER_50:
6323 rtl_hw_start_8168ep_2(tp);
6324 break;
6325
6326 case RTL_GIGA_MAC_VER_51:
6327 rtl_hw_start_8168ep_3(tp);
6328 break;
6329
5872 default: 6330 default:
5873 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", 6331 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5874 dev->name, tp->mac_version); 6332 dev->name, tp->mac_version);
@@ -7399,7 +7857,10 @@ static void rtl_remove_one(struct pci_dev *pdev)
7399 7857
7400 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || 7858 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7401 tp->mac_version == RTL_GIGA_MAC_VER_28 || 7859 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7402 tp->mac_version == RTL_GIGA_MAC_VER_31) && 7860 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
7861 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
7862 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
7863 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
7403 r8168_check_dash(tp)) { 7864 r8168_check_dash(tp)) {
7404 rtl8168_driver_stop(tp); 7865 rtl8168_driver_stop(tp);
7405 } 7866 }
@@ -7556,6 +8017,9 @@ static void rtl_hw_initialize(struct rtl8169_private *tp)
7556 case RTL_GIGA_MAC_VER_46: 8017 case RTL_GIGA_MAC_VER_46:
7557 case RTL_GIGA_MAC_VER_47: 8018 case RTL_GIGA_MAC_VER_47:
7558 case RTL_GIGA_MAC_VER_48: 8019 case RTL_GIGA_MAC_VER_48:
8020 case RTL_GIGA_MAC_VER_49:
8021 case RTL_GIGA_MAC_VER_50:
8022 case RTL_GIGA_MAC_VER_51:
7559 rtl_hw_init_8168g(tp); 8023 rtl_hw_init_8168g(tp);
7560 break; 8024 break;
7561 8025
@@ -7708,6 +8172,9 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7708 case RTL_GIGA_MAC_VER_46: 8172 case RTL_GIGA_MAC_VER_46:
7709 case RTL_GIGA_MAC_VER_47: 8173 case RTL_GIGA_MAC_VER_47:
7710 case RTL_GIGA_MAC_VER_48: 8174 case RTL_GIGA_MAC_VER_48:
8175 case RTL_GIGA_MAC_VER_49:
8176 case RTL_GIGA_MAC_VER_50:
8177 case RTL_GIGA_MAC_VER_51:
7711 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2) 8178 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
7712 tp->features |= RTL_FEATURE_WOL; 8179 tp->features |= RTL_FEATURE_WOL;
7713 if ((RTL_R8(Config3) & LinkUp) != 0) 8180 if ((RTL_R8(Config3) & LinkUp) != 0)
@@ -7756,7 +8223,10 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7756 tp->mac_version == RTL_GIGA_MAC_VER_45 || 8223 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
7757 tp->mac_version == RTL_GIGA_MAC_VER_46 || 8224 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
7758 tp->mac_version == RTL_GIGA_MAC_VER_47 || 8225 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
7759 tp->mac_version == RTL_GIGA_MAC_VER_48) { 8226 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8227 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8228 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8229 tp->mac_version == RTL_GIGA_MAC_VER_51) {
7760 u16 mac_addr[3]; 8230 u16 mac_addr[3];
7761 8231
7762 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC); 8232 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
@@ -7835,7 +8305,10 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7835 8305
7836 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || 8306 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7837 tp->mac_version == RTL_GIGA_MAC_VER_28 || 8307 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7838 tp->mac_version == RTL_GIGA_MAC_VER_31) && 8308 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8309 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8310 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8311 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
7839 r8168_check_dash(tp)) { 8312 r8168_check_dash(tp)) {
7840 rtl8168_driver_start(tp); 8313 rtl8168_driver_start(tp);
7841 } 8314 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 20:04:44 -0500