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authorEli Cohen <eli@mellanox.com>2014-10-02 05:19:43 -0400
committerDavid S. Miller <davem@davemloft.net>2014-10-03 18:42:31 -0400
commitd29b796adada8780db3512c4a34b339f9aeef1ae (patch)
tree0a115b543505a3e9d5d7a4c2d22f058497e1076e /drivers/net/ethernet/mellanox
parentc7a08ac7ee68b9af0d5af99c7b34b574cac4d144 (diff)
net/mlx5_core: Use hardware registers description header file
Add an auto generated header file that describes hardware registers along with set of macros that set/get values. The macros do static checks to avoid overflow, handle endianess, and overall provide a clean way to code commands. Currently the header file is small and we will add structs as we make use of the macros. A few commands were removed from the commands enum since they are not supported currently and will be added when support is available. Signed-off-by: Eli Cohen <eli@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/mellanox')
-rw-r--r--drivers/net/ethernet/mellanox/mlx5/core/cmd.c36
-rw-r--r--drivers/net/ethernet/mellanox/mlx5/core/qp.c3
2 files changed, 0 insertions, 39 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c
index 6eb0f85cf872..3ecef1310bae 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c
@@ -357,60 +357,24 @@ const char *mlx5_command_str(int command)
357 case MLX5_CMD_OP_2ERR_QP: 357 case MLX5_CMD_OP_2ERR_QP:
358 return "2ERR_QP"; 358 return "2ERR_QP";
359 359
360 case MLX5_CMD_OP_RTS2SQD_QP:
361 return "RTS2SQD_QP";
362
363 case MLX5_CMD_OP_SQD2RTS_QP:
364 return "SQD2RTS_QP";
365
366 case MLX5_CMD_OP_2RST_QP: 360 case MLX5_CMD_OP_2RST_QP:
367 return "2RST_QP"; 361 return "2RST_QP";
368 362
369 case MLX5_CMD_OP_QUERY_QP: 363 case MLX5_CMD_OP_QUERY_QP:
370 return "QUERY_QP"; 364 return "QUERY_QP";
371 365
372 case MLX5_CMD_OP_CONF_SQP:
373 return "CONF_SQP";
374
375 case MLX5_CMD_OP_MAD_IFC: 366 case MLX5_CMD_OP_MAD_IFC:
376 return "MAD_IFC"; 367 return "MAD_IFC";
377 368
378 case MLX5_CMD_OP_INIT2INIT_QP: 369 case MLX5_CMD_OP_INIT2INIT_QP:
379 return "INIT2INIT_QP"; 370 return "INIT2INIT_QP";
380 371
381 case MLX5_CMD_OP_SUSPEND_QP:
382 return "SUSPEND_QP";
383
384 case MLX5_CMD_OP_UNSUSPEND_QP:
385 return "UNSUSPEND_QP";
386
387 case MLX5_CMD_OP_SQD2SQD_QP:
388 return "SQD2SQD_QP";
389
390 case MLX5_CMD_OP_ALLOC_QP_COUNTER_SET:
391 return "ALLOC_QP_COUNTER_SET";
392
393 case MLX5_CMD_OP_DEALLOC_QP_COUNTER_SET:
394 return "DEALLOC_QP_COUNTER_SET";
395
396 case MLX5_CMD_OP_QUERY_QP_COUNTER_SET:
397 return "QUERY_QP_COUNTER_SET";
398
399 case MLX5_CMD_OP_CREATE_PSV: 372 case MLX5_CMD_OP_CREATE_PSV:
400 return "CREATE_PSV"; 373 return "CREATE_PSV";
401 374
402 case MLX5_CMD_OP_DESTROY_PSV: 375 case MLX5_CMD_OP_DESTROY_PSV:
403 return "DESTROY_PSV"; 376 return "DESTROY_PSV";
404 377
405 case MLX5_CMD_OP_QUERY_PSV:
406 return "QUERY_PSV";
407
408 case MLX5_CMD_OP_QUERY_SIG_RULE_TABLE:
409 return "QUERY_SIG_RULE_TABLE";
410
411 case MLX5_CMD_OP_QUERY_BLOCK_SIZE_TABLE:
412 return "QUERY_BLOCK_SIZE_TABLE";
413
414 case MLX5_CMD_OP_CREATE_SRQ: 378 case MLX5_CMD_OP_CREATE_SRQ:
415 return "CREATE_SRQ"; 379 return "CREATE_SRQ";
416 380
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/qp.c b/drivers/net/ethernet/mellanox/mlx5/core/qp.c
index 8145b4668229..415b67ce379e 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/qp.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/qp.c
@@ -184,13 +184,10 @@ int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
184 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 184 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
185 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 185 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
186 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 186 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
187 [MLX5_QP_STATE_SQD] = MLX5_CMD_OP_RTS2SQD_QP,
188 }, 187 },
189 [MLX5_QP_STATE_SQD] = { 188 [MLX5_QP_STATE_SQD] = {
190 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 189 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
191 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 190 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
192 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQD2RTS_QP,
193 [MLX5_QP_STATE_SQD] = MLX5_CMD_OP_SQD2SQD_QP,
194 }, 191 },
195 [MLX5_QP_STATE_SQER] = { 192 [MLX5_QP_STATE_SQER] = {
196 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 193 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,