diff options
author | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2013-10-01 07:33:53 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2013-10-01 12:49:49 -0400 |
commit | b00074846732985972741baa49ec677f42e886a2 (patch) | |
tree | 70c3464d2d72aeaa31659d4693bf3c1d9dbd817b /drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h | |
parent | 51e409f106cb890b11fe78a5c2e3cab36b5947ac (diff) |
ixgbe: Cleanup the use of tabs and spaces
Cleans up the whitespace issues noticed during code review where
a mix of tabs and spaces were used for indentation.
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h')
-rw-r--r-- | drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h index 24af12e3719e..aae900a256da 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h | |||
@@ -57,28 +57,28 @@ | |||
57 | #define IXGBE_SFF_QSFP_DEVICE_TECH 0x93 | 57 | #define IXGBE_SFF_QSFP_DEVICE_TECH 0x93 |
58 | 58 | ||
59 | /* Bitmasks */ | 59 | /* Bitmasks */ |
60 | #define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 | 60 | #define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 |
61 | #define IXGBE_SFF_DA_ACTIVE_CABLE 0x8 | 61 | #define IXGBE_SFF_DA_ACTIVE_CABLE 0x8 |
62 | #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 | 62 | #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 |
63 | #define IXGBE_SFF_1GBASESX_CAPABLE 0x1 | 63 | #define IXGBE_SFF_1GBASESX_CAPABLE 0x1 |
64 | #define IXGBE_SFF_1GBASELX_CAPABLE 0x2 | 64 | #define IXGBE_SFF_1GBASELX_CAPABLE 0x2 |
65 | #define IXGBE_SFF_1GBASET_CAPABLE 0x8 | 65 | #define IXGBE_SFF_1GBASET_CAPABLE 0x8 |
66 | #define IXGBE_SFF_10GBASESR_CAPABLE 0x10 | 66 | #define IXGBE_SFF_10GBASESR_CAPABLE 0x10 |
67 | #define IXGBE_SFF_10GBASELR_CAPABLE 0x20 | 67 | #define IXGBE_SFF_10GBASELR_CAPABLE 0x20 |
68 | #define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8 | 68 | #define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8 |
69 | #define IXGBE_SFF_SOFT_RS_SELECT_10G 0x8 | 69 | #define IXGBE_SFF_SOFT_RS_SELECT_10G 0x8 |
70 | #define IXGBE_SFF_SOFT_RS_SELECT_1G 0x0 | 70 | #define IXGBE_SFF_SOFT_RS_SELECT_1G 0x0 |
71 | #define IXGBE_SFF_ADDRESSING_MODE 0x4 | 71 | #define IXGBE_SFF_ADDRESSING_MODE 0x4 |
72 | #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1 | 72 | #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1 |
73 | #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8 | 73 | #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8 |
74 | #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23 | 74 | #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23 |
75 | #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0 | 75 | #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0 |
76 | #define IXGBE_I2C_EEPROM_READ_MASK 0x100 | 76 | #define IXGBE_I2C_EEPROM_READ_MASK 0x100 |
77 | #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 | 77 | #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 |
78 | #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 | 78 | #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 |
79 | #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 | 79 | #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 |
80 | #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 | 80 | #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 |
81 | #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 | 81 | #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 |
82 | 82 | ||
83 | /* Flow control defines */ | 83 | /* Flow control defines */ |
84 | #define IXGBE_TAF_SYM_PAUSE 0x400 | 84 | #define IXGBE_TAF_SYM_PAUSE 0x400 |