ixgbe: Update link flow control to correctly handle multiple packet buffer DCB

This change updates the link flow control configuration so that we
correctly set the link flow control settings for DCB.  Previously we would
have to call the fc_enable call 8 times, once for each packet buffer.  If
we move that logic into the fc_enable call itself we can avoid multiple
unnecessary register writes.

This change also corrects an issue in which we were only shifting the water
marks for 82599 parts by 6 instead of 10.  This was resulting in us only
using 1/16 of the packet buffer when flow control was enabled.

Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 1 insertions, 12 deletions

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
index 888a419dc3d9..65913c5a616e 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
@@ -278,18 +278,7 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
 
         } else {
-                /* X540 devices have a RX bit that should be cleared
-                 * if PFC is disabled on all TCs but PFC features is
-                 * enabled.
-                 */
-                if (hw->mac.type == ixgbe_mac_X540) {
-                        reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
-                        reg &= ~IXGBE_MFLCN_RPFCE_MASK;
-                        IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
-                }
-
-                for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
-                        hw->mac.ops.fc_enable(hw, i);
+                hw->mac.ops.fc_enable(hw);
         }
 
         return 0;