i40e/i40evf: Add nvmupdate support

This implements a state machine intended to support the userland tool for
updating the device eeprom. The state machine implements one-shot reads,
writes, multi-step write sessions, and checksum requests. If we're in the middle
of a multi-step write session, no one should fire off other writes, however, one
shot reads are valid. The userland tool is expected to keep track of its session
status, arrange the placement and ordering of the writes, and deal with the
checksum requirement.

This patch also adds nvmupdate support to ethtool callbacks.
The get_eeprom() and set_eeprom() services in ethtool are used here to
facilitate the userland NVMUpdate tool.  The 'magic' value in the get and
set commands is used to pass additional control information for managing
the read and write steps.

The read operation works both as normally expected in the standard ethtool
method, as well as with the extra NVM controls.  The write operation
works only for the expanded NVM functions - the normal ethtool method is
not allowed because of the NVM semaphore management needed for multipart
writes, as well as the checksum requirement.

Change-ID: I1d84a170153a9f437906744e2e350fd68fe7563d
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Tested-by: Jim Young <jamesx.m.young@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

3 files changed, 94 insertions, 6 deletions

diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c b/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
index 8330744b02f1..ee3a934043bb 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
+++ b/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
@@ -708,12 +708,6 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
                 goto asq_send_command_exit;
         }
 
-        if (i40e_is_nvm_update_op(desc) && hw->aq.nvm_busy) {
-                i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: NVM busy.\n");
-                status = I40E_ERR_NVM;
-                goto asq_send_command_exit;
-        }
-
         details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
         if (cmd_details) {
                 *details = *cmd_details;
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq.h b/drivers/net/ethernet/intel/i40evf/i40e_adminq.h
index 162845589bf7..91a5c5bd80f3 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_adminq.h
+++ b/drivers/net/ethernet/intel/i40evf/i40e_adminq.h
@@ -94,6 +94,7 @@ struct i40e_adminq_info {
         u16 api_maj_ver;                /* api major version */
         u16 api_min_ver;                /* api minor version */
         bool nvm_busy;
+        bool nvm_release_on_done;
 
         struct mutex asq_mutex; /* Send queue lock */
         struct mutex arq_mutex; /* Receive queue lock */
@@ -103,6 +104,41 @@ struct i40e_adminq_info {
         enum i40e_admin_queue_err arq_last_status;
 };
 
+/**
+ * i40e_aq_rc_to_posix - convert errors to user-land codes
+ * aq_rc: AdminQ error code to convert
+ **/
+static inline int i40e_aq_rc_to_posix(u16 aq_rc)
+{
+        int aq_to_posix[] = {
+                0,           /* I40E_AQ_RC_OK */
+                -EPERM,      /* I40E_AQ_RC_EPERM */
+                -ENOENT,     /* I40E_AQ_RC_ENOENT */
+                -ESRCH,      /* I40E_AQ_RC_ESRCH */
+                -EINTR,      /* I40E_AQ_RC_EINTR */
+                -EIO,        /* I40E_AQ_RC_EIO */
+                -ENXIO,      /* I40E_AQ_RC_ENXIO */
+                -E2BIG,      /* I40E_AQ_RC_E2BIG */
+                -EAGAIN,     /* I40E_AQ_RC_EAGAIN */
+                -ENOMEM,     /* I40E_AQ_RC_ENOMEM */
+                -EACCES,     /* I40E_AQ_RC_EACCES */
+                -EFAULT,     /* I40E_AQ_RC_EFAULT */
+                -EBUSY,      /* I40E_AQ_RC_EBUSY */
+                -EEXIST,     /* I40E_AQ_RC_EEXIST */
+                -EINVAL,     /* I40E_AQ_RC_EINVAL */
+                -ENOTTY,     /* I40E_AQ_RC_ENOTTY */
+                -ENOSPC,     /* I40E_AQ_RC_ENOSPC */
+                -ENOSYS,     /* I40E_AQ_RC_ENOSYS */
+                -ERANGE,     /* I40E_AQ_RC_ERANGE */
+                -EPIPE,      /* I40E_AQ_RC_EFLUSHED */
+                -ESPIPE,     /* I40E_AQ_RC_BAD_ADDR */
+                -EROFS,      /* I40E_AQ_RC_EMODE */
+                -EFBIG,      /* I40E_AQ_RC_EFBIG */
+        };
+
+        return aq_to_posix[aq_rc];
+}
+
 /* general information */
 #define I40E_AQ_LARGE_BUF       512
 #define I40E_ASQ_CMD_TIMEOUT    100000  /* usecs */
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_type.h b/drivers/net/ethernet/intel/i40evf/i40e_type.h
index 6dd72ad58e7d..15376436cead 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_type.h
+++ b/drivers/net/ethernet/intel/i40evf/i40e_type.h
@@ -268,6 +268,61 @@ struct i40e_nvm_info {
         u32 eetrack;              /* NVM data version */
 };
 
+/* definitions used in NVM update support */
+
+enum i40e_nvmupd_cmd {
+        I40E_NVMUPD_INVALID,
+        I40E_NVMUPD_READ_CON,
+        I40E_NVMUPD_READ_SNT,
+        I40E_NVMUPD_READ_LCB,
+        I40E_NVMUPD_READ_SA,
+        I40E_NVMUPD_WRITE_ERA,
+        I40E_NVMUPD_WRITE_CON,
+        I40E_NVMUPD_WRITE_SNT,
+        I40E_NVMUPD_WRITE_LCB,
+        I40E_NVMUPD_WRITE_SA,
+        I40E_NVMUPD_CSUM_CON,
+        I40E_NVMUPD_CSUM_SA,
+        I40E_NVMUPD_CSUM_LCB,
+};
+
+enum i40e_nvmupd_state {
+        I40E_NVMUPD_STATE_INIT,
+        I40E_NVMUPD_STATE_READING,
+        I40E_NVMUPD_STATE_WRITING
+};
+
+/* nvm_access definition and its masks/shifts need to be accessible to
+ * application, core driver, and shared code.  Where is the right file?
+ */
+#define I40E_NVM_READ   0xB
+#define I40E_NVM_WRITE  0xC
+
+#define I40E_NVM_MOD_PNT_MASK 0xFF
+
+#define I40E_NVM_TRANS_SHIFT    8
+#define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
+#define I40E_NVM_CON            0x0
+#define I40E_NVM_SNT            0x1
+#define I40E_NVM_LCB            0x2
+#define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
+#define I40E_NVM_ERA            0x4
+#define I40E_NVM_CSUM           0x8
+
+#define I40E_NVM_ADAPT_SHIFT    16
+#define I40E_NVM_ADAPT_MASK     (0xffff << I40E_NVM_ADAPT_SHIFT)
+
+#define I40E_NVMUPD_MAX_DATA    4096
+#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
+
+struct i40e_nvm_access {
+        u32 command;
+        u32 config;
+        u32 offset;     /* in bytes */
+        u32 data_size;  /* in bytes */
+        u8 data[1];
+};
+
 /* PCI bus types */
 enum i40e_bus_type {
         i40e_bus_type_unknown = 0,
@@ -403,6 +458,9 @@ struct i40e_hw {
         /* Admin Queue info */
         struct i40e_adminq_info aq;
 
+        /* state of nvm update process */
+        enum i40e_nvmupd_state nvmupd_state;
+
         /* HMC info */
         struct i40e_hmc_info hmc; /* HMC info struct */