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authorPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>2014-06-04 01:35:54 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2014-06-26 07:44:57 -0400
commit3ba3faeb62220411284551a6443395ce7960b17d (patch)
tree63892bf8f4377bb19930813a83ae57e9326c8176 /drivers/net/ethernet/intel/i40evf
parent7a208e83fcedc0b845facc17d05ead0b9b73a967 (diff)
i40e/i40evf: Big endian fixes for handling HMC
Fix HMC handling for big endian architectures. Change-ID: Id8c46fc341815d47bfe0af8b819f0ab9a1e9e515 Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/i40evf')
-rw-r--r--drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h28
1 files changed, 20 insertions, 8 deletions
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h b/drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h
index d6f762241537..a5d79877354c 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h
+++ b/drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h
@@ -32,16 +32,22 @@ struct i40e_hw;
32 32
33/* HMC element context information */ 33/* HMC element context information */
34 34
35/* Rx queue context data */ 35/* Rx queue context data
36 *
37 * The sizes of the variables may be larger than needed due to crossing byte
38 * boundaries. If we do not have the width of the variable set to the correct
39 * size then we could end up shifting bits off the top of the variable when the
40 * variable is at the top of a byte and crosses over into the next byte.
41 */
36struct i40e_hmc_obj_rxq { 42struct i40e_hmc_obj_rxq {
37 u16 head; 43 u16 head;
38 u8 cpuid; 44 u16 cpuid; /* bigger than needed, see above for reason */
39 u64 base; 45 u64 base;
40 u16 qlen; 46 u16 qlen;
41#define I40E_RXQ_CTX_DBUFF_SHIFT 7 47#define I40E_RXQ_CTX_DBUFF_SHIFT 7
42 u8 dbuff; 48 u16 dbuff; /* bigger than needed, see above for reason */
43#define I40E_RXQ_CTX_HBUFF_SHIFT 6 49#define I40E_RXQ_CTX_HBUFF_SHIFT 6
44 u8 hbuff; 50 u16 hbuff; /* bigger than needed, see above for reason */
45 u8 dtype; 51 u8 dtype;
46 u8 dsize; 52 u8 dsize;
47 u8 crcstrip; 53 u8 crcstrip;
@@ -50,16 +56,22 @@ struct i40e_hmc_obj_rxq {
50 u8 hsplit_0; 56 u8 hsplit_0;
51 u8 hsplit_1; 57 u8 hsplit_1;
52 u8 showiv; 58 u8 showiv;
53 u16 rxmax; 59 u32 rxmax; /* bigger than needed, see above for reason */
54 u8 tphrdesc_ena; 60 u8 tphrdesc_ena;
55 u8 tphwdesc_ena; 61 u8 tphwdesc_ena;
56 u8 tphdata_ena; 62 u8 tphdata_ena;
57 u8 tphhead_ena; 63 u8 tphhead_ena;
58 u8 lrxqthresh; 64 u16 lrxqthresh; /* bigger than needed, see above for reason */
59 u8 prefena; /* NOTE: normally must be set to 1 at init */ 65 u8 prefena; /* NOTE: normally must be set to 1 at init */
60}; 66};
61 67
62/* Tx queue context data */ 68/* Tx queue context data
69*
70* The sizes of the variables may be larger than needed due to crossing byte
71* boundaries. If we do not have the width of the variable set to the correct
72* size then we could end up shifting bits off the top of the variable when the
73* variable is at the top of a byte and crosses over into the next byte.
74*/
63struct i40e_hmc_obj_txq { 75struct i40e_hmc_obj_txq {
64 u16 head; 76 u16 head;
65 u8 new_context; 77 u8 new_context;
@@ -69,7 +81,7 @@ struct i40e_hmc_obj_txq {
69 u8 fd_ena; 81 u8 fd_ena;
70 u8 alt_vlan_ena; 82 u8 alt_vlan_ena;
71 u16 thead_wb; 83 u16 thead_wb;
72 u16 cpuid; 84 u8 cpuid;
73 u8 head_wb_ena; 85 u8 head_wb_ena;
74 u16 qlen; 86 u16 qlen;
75 u8 tphrdesc_ena; 87 u8 tphrdesc_ena;