e1000e: cosmetic cleanup of comments

Update comments to conform to the preferred style for networking code as
described in ./Documentation/CodingStyle and checked for in the recently
added checkpatch NETWORKING_BLOCK_COMMENT_STYLE test.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 47 insertions, 94 deletions

diff --git a/drivers/net/ethernet/intel/e1000e/phy.c b/drivers/net/ethernet/intel/e1000e/phy.c
index fc62a3f3a5be..28b38ff37e84 100644
--- a/drivers/net/ethernet/intel/e1000e/phy.c
+++ b/drivers/net/ethernet/intel/e1000e/phy.c
@@ -193,8 +193,7 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
                 return -E1000_ERR_PARAM;
         }
 
-        /*
-         * Set up Op-code, Phy Address, and register offset in the MDI
+        /* Set up Op-code, Phy Address, and register offset in the MDI
          * Control register.  The MAC will take care of interfacing with the
          * PHY to retrieve the desired data.
          */
@@ -204,8 +203,7 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
 
         ew32(MDIC, mdic);
 
-        /*
-         * Poll the ready bit to see if the MDI read completed
+        /* Poll the ready bit to see if the MDI read completed
          * Increasing the time out as testing showed failures with
          * the lower time out
          */
@@ -225,8 +223,7 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
         }
         *data = (u16) mdic;
 
-        /*
-         * Allow some time after each MDIC transaction to avoid
+        /* Allow some time after each MDIC transaction to avoid
          * reading duplicate data in the next MDIC transaction.
          */
         if (hw->mac.type == e1000_pch2lan)
@@ -253,8 +250,7 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
                 return -E1000_ERR_PARAM;
         }
 
-        /*
-         * Set up Op-code, Phy Address, and register offset in the MDI
+        /* Set up Op-code, Phy Address, and register offset in the MDI
          * Control register.  The MAC will take care of interfacing with the
          * PHY to retrieve the desired data.
          */
@@ -265,8 +261,7 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
 
         ew32(MDIC, mdic);
 
-        /*
-         * Poll the ready bit to see if the MDI read completed
+        /* Poll the ready bit to see if the MDI read completed
          * Increasing the time out as testing showed failures with
          * the lower time out
          */
@@ -285,8 +280,7 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
                 return -E1000_ERR_PHY;
         }
 
-        /*
-         * Allow some time after each MDIC transaction to avoid
+        /* Allow some time after each MDIC transaction to avoid
          * reading duplicate data in the next MDIC transaction.
          */
         if (hw->mac.type == e1000_pch2lan)
@@ -708,8 +702,7 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
         if (ret_val)
                 return ret_val;
         phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
-        /*
-         * Options:
+        /* Options:
          *   0 - Auto (default)
          *   1 - MDI mode
          *   2 - MDI-X mode
@@ -754,8 +747,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
         if (phy->type != e1000_phy_bm)
                 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
 
-        /*
-         * Options:
+        /* Options:
          *   MDI/MDI-X = 0 (default)
          *   0 - Auto for all speeds
          *   1 - MDI mode
@@ -780,8 +772,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
                 break;
         }
 
-        /*
-         * Options:
+        /* Options:
          *   disable_polarity_correction = 0 (default)
          *       Automatic Correction for Reversed Cable Polarity
          *   0 - Disabled
@@ -818,8 +809,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
         if ((phy->type == e1000_phy_m88) &&
             (phy->revision < E1000_REVISION_4) &&
             (phy->id != BME1000_E_PHY_ID_R2)) {
-                /*
-                 * Force TX_CLK in the Extended PHY Specific Control Register
+                /* Force TX_CLK in the Extended PHY Specific Control Register
                  * to 25MHz clock.
                  */
                 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
@@ -899,8 +889,7 @@ s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
                 return ret_val;
         }
 
-        /*
-         * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
+        /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
          * timeout issues when LFS is enabled.
          */
         msleep(100);
@@ -936,8 +925,7 @@ s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
 
         /* set auto-master slave resolution settings */
         if (hw->mac.autoneg) {
-                /*
-                 * when autonegotiation advertisement is only 1000Mbps then we
+                /* when autonegotiation advertisement is only 1000Mbps then we
                  * should disable SmartSpeed and enable Auto MasterSlave
                  * resolution as hardware default.
                  */
@@ -1001,16 +989,14 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
                         return ret_val;
         }
 
-        /*
-         * Need to parse both autoneg_advertised and fc and set up
+        /* Need to parse both autoneg_advertised and fc and set up
          * the appropriate PHY registers.  First we will parse for
          * autoneg_advertised software override.  Since we can advertise
          * a plethora of combinations, we need to check each bit
          * individually.
          */
 
-        /*
-         * First we clear all the 10/100 mb speed bits in the Auto-Neg
+        /* First we clear all the 10/100 mb speed bits in the Auto-Neg
          * Advertisement Register (Address 4) and the 1000 mb speed bits in
          * the  1000Base-T Control Register (Address 9).
          */
@@ -1056,8 +1042,7 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
         }
 
-        /*
-         * Check for a software override of the flow control settings, and
+        /* Check for a software override of the flow control settings, and
          * setup the PHY advertisement registers accordingly.  If
          * auto-negotiation is enabled, then software will have to set the
          * "PAUSE" bits to the correct value in the Auto-Negotiation
@@ -1076,15 +1061,13 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
          */
         switch (hw->fc.current_mode) {
         case e1000_fc_none:
-                /*
-                 * Flow control (Rx & Tx) is completely disabled by a
+                /* Flow control (Rx & Tx) is completely disabled by a
                  * software over-ride.
                  */
                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
                 break;
         case e1000_fc_rx_pause:
-                /*
-                 * Rx Flow control is enabled, and Tx Flow control is
+                /* Rx Flow control is enabled, and Tx Flow control is
                  * disabled, by a software over-ride.
                  *
                  * Since there really isn't a way to advertise that we are
@@ -1096,16 +1079,14 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
                 break;
         case e1000_fc_tx_pause:
-                /*
-                 * Tx Flow control is enabled, and Rx Flow control is
+                /* Tx Flow control is enabled, and Rx Flow control is
                  * disabled, by a software over-ride.
                  */
                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
                 break;
         case e1000_fc_full:
-                /*
-                 * Flow control (both Rx and Tx) is enabled by a software
+                /* Flow control (both Rx and Tx) is enabled by a software
                  * over-ride.
                  */
                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
@@ -1142,14 +1123,12 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
         s32 ret_val;
         u16 phy_ctrl;
 
-        /*
-         * Perform some bounds checking on the autoneg advertisement
+        /* Perform some bounds checking on the autoneg advertisement
          * parameter.
          */
         phy->autoneg_advertised &= phy->autoneg_mask;
 
-        /*
-         * If autoneg_advertised is zero, we assume it was not defaulted
+        /* If autoneg_advertised is zero, we assume it was not defaulted
          * by the calling code so we set to advertise full capability.
          */
         if (!phy->autoneg_advertised)
@@ -1163,8 +1142,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
         }
         e_dbg("Restarting Auto-Neg\n");
 
-        /*
-         * Restart auto-negotiation by setting the Auto Neg Enable bit and
+        /* Restart auto-negotiation by setting the Auto Neg Enable bit and
          * the Auto Neg Restart bit in the PHY control register.
          */
         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
@@ -1176,8 +1154,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
         if (ret_val)
                 return ret_val;
 
-        /*
-         * Does the user want to wait for Auto-Neg to complete here, or
+        /* Does the user want to wait for Auto-Neg to complete here, or
          * check at a later time (for example, callback routine).
          */
         if (phy->autoneg_wait_to_complete) {
@@ -1208,16 +1185,14 @@ s32 e1000e_setup_copper_link(struct e1000_hw *hw)
         bool link;
 
         if (hw->mac.autoneg) {
-                /*
-                 * Setup autoneg and flow control advertisement and perform
+                /* Setup autoneg and flow control advertisement and perform
                  * autonegotiation.
                  */
                 ret_val = e1000_copper_link_autoneg(hw);
                 if (ret_val)
                         return ret_val;
         } else {
-                /*
-                 * PHY will be set to 10H, 10F, 100H or 100F
+                /* PHY will be set to 10H, 10F, 100H or 100F
                  * depending on user settings.
                  */
                 e_dbg("Forcing Speed and Duplex\n");
@@ -1228,8 +1203,7 @@ s32 e1000e_setup_copper_link(struct e1000_hw *hw)
                 }
         }
 
-        /*
-         * Check link status. Wait up to 100 microseconds for link to become
+        /* Check link status. Wait up to 100 microseconds for link to become
          * valid.
          */
         ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
@@ -1273,8 +1247,7 @@ s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
         if (ret_val)
                 return ret_val;
 
-        /*
-         * Clear Auto-Crossover to force MDI manually.  IGP requires MDI
+        /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
          * forced whenever speed and duplex are forced.
          */
         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
@@ -1328,8 +1301,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
         u16 phy_data;
         bool link;
 
-        /*
-         * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
+        /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
          * forced whenever speed and duplex are forced.
          */
         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -1370,8 +1342,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
                         if (hw->phy.type != e1000_phy_m88) {
                                 e_dbg("Link taking longer than expected.\n");
                         } else {
-                                /*
-                                 * We didn't get link.
+                                /* We didn't get link.
                                  * Reset the DSP and cross our fingers.
                                  */
                                 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
@@ -1398,8 +1369,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
         if (ret_val)
                 return ret_val;
 
-        /*
-         * Resetting the phy means we need to re-force TX_CLK in the
+        /* Resetting the phy means we need to re-force TX_CLK in the
          * Extended PHY Specific Control Register to 25MHz clock from
          * the reset value of 2.5MHz.
          */
@@ -1408,8 +1378,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
         if (ret_val)
                 return ret_val;
 
-        /*
-         * In addition, we must re-enable CRS on Tx for both half and full
+        /* In addition, we must re-enable CRS on Tx for both half and full
          * duplex.
          */
         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -1573,8 +1542,7 @@ s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
                 if (ret_val)
                         return ret_val;
-                /*
-                 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
+                /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
                  * during Dx states where the power conservation is most
                  * important.  During driver activity we should enable
                  * SmartSpeed, so performance is maintained.
@@ -1702,8 +1670,7 @@ s32 e1000_check_polarity_igp(struct e1000_hw *hw)
         s32 ret_val;
         u16 data, offset, mask;
 
-        /*
-         * Polarity is determined based on the speed of
+        /* Polarity is determined based on the speed of
          * our connection.
          */
         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
@@ -1715,8 +1682,7 @@ s32 e1000_check_polarity_igp(struct e1000_hw *hw)
                 offset  = IGP01E1000_PHY_PCS_INIT_REG;
                 mask    = IGP01E1000_PHY_POLARITY_MASK;
         } else {
-                /*
-                 * This really only applies to 10Mbps since
+                /* This really only applies to 10Mbps since
                  * there is no polarity for 100Mbps (always 0).
                  */
                 offset  = IGP01E1000_PHY_PORT_STATUS;
@@ -1745,8 +1711,7 @@ s32 e1000_check_polarity_ife(struct e1000_hw *hw)
         s32 ret_val;
         u16 phy_data, offset, mask;
 
-        /*
-         * Polarity is determined based on the reversal feature being enabled.
+        /* Polarity is determined based on the reversal feature being enabled.
          */
         if (phy->polarity_correction) {
                 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
@@ -1791,8 +1756,7 @@ static s32 e1000_wait_autoneg(struct e1000_hw *hw)
                 msleep(100);
         }
 
-        /*
-         * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
+        /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
          * has completed.
          */
         return ret_val;
@@ -1814,15 +1778,13 @@ s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
         u16 i, phy_status;
 
         for (i = 0; i < iterations; i++) {
-                /*
-                 * Some PHYs require the PHY_STATUS register to be read
+                /* Some PHYs require the PHY_STATUS register to be read
                  * twice due to the link bit being sticky.  No harm doing
                  * it across the board.
                  */
                 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
                 if (ret_val)
-                        /*
-                         * If the first read fails, another entity may have
+                        /* If the first read fails, another entity may have
                          * ownership of the resources, wait and try again to
                          * see if they have relinquished the resources yet.
                          */
@@ -1913,8 +1875,7 @@ s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
                 if (ret_val)
                         return ret_val;
 
-                /*
-                 * Getting bits 15:9, which represent the combination of
+                /* Getting bits 15:9, which represent the combination of
                  * coarse and fine gain values.  The result is a number
                  * that can be put into the lookup table to obtain the
                  * approximate cable length.
@@ -2285,15 +2246,13 @@ s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
         e1e_wphy(hw, 0x1796, 0x0008);
         /* Change cg_icount + enable integbp for channels BCD */
         e1e_wphy(hw, 0x1798, 0xD008);
-        /*
-         * Change cg_icount + enable integbp + change prop_factor_master
+        /* Change cg_icount + enable integbp + change prop_factor_master
          * to 8 for channel A
          */
         e1e_wphy(hw, 0x1898, 0xD918);
         /* Disable AHT in Slave mode on channel A */
         e1e_wphy(hw, 0x187A, 0x0800);
-        /*
-         * Enable LPLU and disable AN to 1000 in non-D0a states,
+        /* Enable LPLU and disable AN to 1000 in non-D0a states,
          * Enable SPD+B2B
          */
         e1e_wphy(hw, 0x0019, 0x008D);
@@ -2417,8 +2376,7 @@ s32 e1000e_determine_phy_address(struct e1000_hw *hw)
                         e1000e_get_phy_id(hw);
                         phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
 
-                        /*
-                         * If phy_type is valid, break - we found our
+                        /* If phy_type is valid, break - we found our
                          * PHY address
                          */
                         if (phy_type  != e1000_phy_unknown)
@@ -2478,8 +2436,7 @@ s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
         if (offset > MAX_PHY_MULTI_PAGE_REG) {
                 u32 page_shift, page_select;
 
-                /*
-                 * Page select is register 31 for phy address 1 and 22 for
+                /* Page select is register 31 for phy address 1 and 22 for
                  * phy address 2 and 3. Page select is shifted only for
                  * phy address 1.
                  */
@@ -2537,8 +2494,7 @@ s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
         if (offset > MAX_PHY_MULTI_PAGE_REG) {
                 u32 page_shift, page_select;
 
-                /*
-                 * Page select is register 31 for phy address 1 and 22 for
+                /* Page select is register 31 for phy address 1 and 22 for
                  * phy address 2 and 3. Page select is shifted only for
                  * phy address 1.
                  */
@@ -2683,8 +2639,7 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
                 return ret_val;
         }
 
-        /*
-         * Enable both PHY wakeup mode and Wakeup register page writes.
+        /* Enable both PHY wakeup mode and Wakeup register page writes.
          * Prevent a power state change by disabling ME and Host PHY wakeup.
          */
         temp = *phy_reg;
@@ -2698,8 +2653,7 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
                 return ret_val;
         }
 
-        /*
-         * Select Host Wakeup Registers page - caller now able to write
+        /* Select Host Wakeup Registers page - caller now able to write
          * registers on the Wakeup registers page
          */
         return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
@@ -3038,8 +2992,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
                 if (page == HV_INTC_FC_PAGE_START)
                         page = 0;
 
-                /*
-                 * Workaround MDIO accesses being disabled after entering IEEE
+                /* Workaround MDIO accesses being disabled after entering IEEE
                  * Power Down (when bit 11 of the PHY Control register is set)
                  */
                 if ((hw->phy.type == e1000_phy_82578) &&