net: fec: enable pause frame to improve rx prefomance for 1G network

The limition of imx6 internal bus cause fec can't achieve 1G perfomance.
There will be many packages lost because FIFO over run.

This patch enable pause frame flow control.

Before this patch
iperf -s -i 1
TCP window size: 85.3 KByte (default)
------------------------------------------------------------
[  4] local 10.192.242.153 port 5001 connected with 10.192.242.94 port 49773
[ ID] Interval       Transfer     Bandwidth
[  4]  0.0- 1.0 sec  6.35 MBytes  53.3 Mbits/sec
[  4]  1.0- 2.0 sec  3.39 MBytes  28.5 Mbits/sec
[  4]  2.0- 3.0 sec  2.63 MBytes  22.1 Mbits/sec
[  4]  3.0- 4.0 sec  1.10 MBytes  9.23 Mbits/sec

ifconfig
   RX packets:46195 errors:1859 dropped:1 overruns:1859 frame:1859

After this patch
iperf -s -i 1

[  4] local 10.192.242.153 port 5001 connected with 10.192.242.94 port 49757
[ ID] Interval       Transfer     Bandwidth
[  4]  0.0- 1.0 sec  49.8 MBytes   418 Mbits/sec
[  4]  1.0- 2.0 sec  50.1 MBytes   420 Mbits/sec
[  4]  2.0- 3.0 sec  47.5 MBytes   399 Mbits/sec
[  4]  3.0- 4.0 sec  45.9 MBytes   385 Mbits/sec
[  4]  4.0- 5.0 sec  44.8 MBytes   376 Mbits/sec

ifconfig
   RX packets:2348454 errors:0 dropped:16 overruns:0 frame:0

Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 5 insertions, 0 deletions

diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
index 48623947d956..2ebedaf7ad81 100644
--- a/drivers/net/ethernet/freescale/fec.h
+++ b/drivers/net/ethernet/freescale/fec.h
@@ -48,6 +48,10 @@
 #define FEC_R_DES_START         0x180 /* Receive descriptor ring */
 #define FEC_X_DES_START         0x184 /* Transmit descriptor ring */
 #define FEC_R_BUFF_SIZE         0x188 /* Maximum receive buff size */
+#define FEC_R_FIFO_RSFL         0x190 /* Receive FIFO section full threshold */
+#define FEC_R_FIFO_RSEM         0x194 /* Receive FIFO section empty threshold */
+#define FEC_R_FIFO_RAEM         0x198 /* Receive FIFO almost empty threshold */
+#define FEC_R_FIFO_RAFL         0x19c /* Receive FIFO almost full threshold */
 #define FEC_MIIGSK_CFGR         0x300 /* MIIGSK Configuration reg */
 #define FEC_MIIGSK_ENR          0x308 /* MIIGSK Enable reg */
 
@@ -243,6 +247,7 @@ struct fec_enet_private {
         struct  completion mdio_done;
         int     irq[FEC_IRQ_NUM];
         int     bufdesc_ex;
+        int     pause_flag;
 
         struct ptp_clock *ptp_clock;
         struct ptp_clock_info ptp_caps;