diff options
author | Vipul Pandya <vipul@chelsio.com> | 2013-04-29 00:04:40 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2013-04-29 15:24:44 -0400 |
commit | b407a4a90800ff4a89b7280302602245806bf498 (patch) | |
tree | 6f70112f317703015ac9f5d2b400fc946e9c9b29 /drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h | |
parent | 9ef603a04121eee3e6b9bdaf95e18006a64cf2c4 (diff) |
cxgb4: Support CPL_SGE_EGR_UPDATEs encapsulated in a CPL_FW4_MSG
Newer firmware can post CPL_SGE_EGR_UPDATE message encapsulated in a
CPL_FW4_MSG as follows
flit0 rss_header (if DropRSS == 0 in IQ context)
flit1 CPL_FW4_MSG cpl
flit2 rss_header w/opcode CPL_SGE_EGR_UPDATE
flit3 CPL_SGE_EGR_UPDATE cpl
So FW4_MSG CPLs with a newly created type of FW_TYPE_RSSCPL have the
CPL_SGE_EGR_UPDATE CPL message in flit 2 of the FW4_MSG. Firmware can still
post regular CPL_SGE_EGR_UPDATE messages, so the drivers need to handle
both.
This patch also writes a new parameter to firmware requesting encapsulated
EGR_UPDATE. This allows firmware with this support to not break older drivers.
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h')
-rw-r--r-- | drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h | 38 |
1 files changed, 35 insertions, 3 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h index 93444325b1e8..d1c755f78aaf 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h +++ b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h | |||
@@ -973,7 +973,9 @@ enum fw_params_param_pfvf { | |||
973 | FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, | 973 | FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, |
974 | FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, | 974 | FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, |
975 | FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, | 975 | FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, |
976 | FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E | 976 | FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, |
977 | FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, | ||
978 | FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 | ||
977 | }; | 979 | }; |
978 | 980 | ||
979 | /* | 981 | /* |
@@ -1758,6 +1760,25 @@ enum fw_port_module_type { | |||
1758 | FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK | 1760 | FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK |
1759 | }; | 1761 | }; |
1760 | 1762 | ||
1763 | enum fw_port_mod_sub_type { | ||
1764 | FW_PORT_MOD_SUB_TYPE_NA, | ||
1765 | FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, | ||
1766 | FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, | ||
1767 | FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, | ||
1768 | FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, | ||
1769 | FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, | ||
1770 | FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, | ||
1771 | |||
1772 | /* The following will never been in the VPD. They are TWINAX cable | ||
1773 | * lengths decoded from SFP+ module i2c PROMs. These should | ||
1774 | * almost certainly go somewhere else ... | ||
1775 | */ | ||
1776 | FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, | ||
1777 | FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, | ||
1778 | FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, | ||
1779 | FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, | ||
1780 | }; | ||
1781 | |||
1761 | /* port stats */ | 1782 | /* port stats */ |
1762 | #define FW_NUM_PORT_STATS 50 | 1783 | #define FW_NUM_PORT_STATS 50 |
1763 | #define FW_NUM_PORT_TX_STATS 23 | 1784 | #define FW_NUM_PORT_TX_STATS 23 |
@@ -2123,11 +2144,11 @@ struct fw_hdr { | |||
2123 | u8 intfver_ri; | 2144 | u8 intfver_ri; |
2124 | u8 intfver_iscsipdu; | 2145 | u8 intfver_iscsipdu; |
2125 | u8 intfver_iscsi; | 2146 | u8 intfver_iscsi; |
2147 | u8 intfver_fcoepdu; | ||
2126 | u8 intfver_fcoe; | 2148 | u8 intfver_fcoe; |
2127 | u8 reserved2; | 2149 | __u32 reserved2; |
2128 | __u32 reserved3; | 2150 | __u32 reserved3; |
2129 | __u32 reserved4; | 2151 | __u32 reserved4; |
2130 | __u32 reserved5; | ||
2131 | __be32 flags; | 2152 | __be32 flags; |
2132 | __be32 reserved6[23]; | 2153 | __be32 reserved6[23]; |
2133 | }; | 2154 | }; |
@@ -2137,6 +2158,17 @@ struct fw_hdr { | |||
2137 | #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff) | 2158 | #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff) |
2138 | #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff) | 2159 | #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff) |
2139 | 2160 | ||
2161 | enum fw_hdr_intfver { | ||
2162 | FW_HDR_INTFVER_NIC = 0x00, | ||
2163 | FW_HDR_INTFVER_VNIC = 0x00, | ||
2164 | FW_HDR_INTFVER_OFLD = 0x00, | ||
2165 | FW_HDR_INTFVER_RI = 0x00, | ||
2166 | FW_HDR_INTFVER_ISCSIPDU = 0x00, | ||
2167 | FW_HDR_INTFVER_ISCSI = 0x00, | ||
2168 | FW_HDR_INTFVER_FCOEPDU = 0x00, | ||
2169 | FW_HDR_INTFVER_FCOE = 0x00, | ||
2170 | }; | ||
2171 | |||
2140 | enum fw_hdr_flags { | 2172 | enum fw_hdr_flags { |
2141 | FW_HDR_FLAGS_RESET_HALT = 0x00000001, | 2173 | FW_HDR_FLAGS_RESET_HALT = 0x00000001, |
2142 | }; | 2174 | }; |