cxgb4: Use FW interface to get BAR0 value

Use the firmware interface to get the BAR0 value since we really don't want
to use the PCI-E Configuration Space Backdoor access which is owned by the
firmware.

Set up PCI-E Memory Window registers using the true values programmed into
BAR registers.  When the PF4 "Master Function" is exported to a Virtual
Machine, the values returned by pci_resource_start() will be for the
synthetic PCI-E Configuration Space and not the real addresses. But we need
to program the PCI-E Memory Window address decoders with the real addresses
that we're going to be using in order to have accesses through the Memory
Windows work.

Based on origninal work by Casey Leedom <leedom@chelsio.com>

Signed-off-by: Casey Leedom <leedom@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 24 insertions, 0 deletions

diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index 4536ea9f7018..2c3d00d77ef6 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -144,6 +144,30 @@ void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 }
 
 /*
+ * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
+ * mechanism.  This guarantees that we get the real value even if we're
+ * operating within a Virtual Machine and the Hypervisor is trapping our
+ * Configuration Space accesses.
+ */
+void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
+{
+        u32 req = ENABLE | FUNCTION(adap->fn) | reg;
+
+        if (is_t4(adap->params.chip))
+                req |= F_LOCALCFG;
+
+        t4_write_reg(adap, PCIE_CFG_SPACE_REQ, req);
+        *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA);
+
+        /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
+         * Configuration Space read.  (None of the other fields matter when
+         * ENABLE is 0 so a simple register write is easier than a
+         * read-modify-write via t4_set_reg_field().)
+         */
+        t4_write_reg(adap, PCIE_CFG_SPACE_REQ, 0);
+}
+
+/*
  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
  */
 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,