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authorMichael Chan <mchan@broadcom.com>2012-09-28 03:12:39 -0400
committerDavid S. Miller <davem@davemloft.net>2012-09-30 02:10:35 -0400
commita489b6d999547799b789ad0683f867d3ae5ed128 (patch)
tree4483282f76ead7975da0ddc7ec3d4c2db8ebf64a /drivers/net/ethernet/broadcom
parent9102426a87f9b7edb943e17f76d46ee412083e10 (diff)
tg3: Separate coalescing setup for rx and tx
since the number of rings can be different. Reviewed-by: Nithin Nayak Sujir <nsujir@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom')
-rw-r--r--drivers/net/ethernet/broadcom/tg3.c74
1 files changed, 45 insertions, 29 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 330356bdaf0c..ddf260cc2db7 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -8331,9 +8331,10 @@ static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
8331 nic_addr); 8331 nic_addr);
8332} 8332}
8333 8333
8334static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) 8334
8335static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
8335{ 8336{
8336 int i; 8337 int i = 0;
8337 8338
8338 if (!tg3_flag(tp, ENABLE_TSS)) { 8339 if (!tg3_flag(tp, ENABLE_TSS)) {
8339 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); 8340 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
@@ -8343,31 +8344,43 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
8343 tw32(HOSTCC_TXCOL_TICKS, 0); 8344 tw32(HOSTCC_TXCOL_TICKS, 0);
8344 tw32(HOSTCC_TXMAX_FRAMES, 0); 8345 tw32(HOSTCC_TXMAX_FRAMES, 0);
8345 tw32(HOSTCC_TXCOAL_MAXF_INT, 0); 8346 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
8347
8348 for (; i < tp->txq_cnt; i++) {
8349 u32 reg;
8350
8351 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8352 tw32(reg, ec->tx_coalesce_usecs);
8353 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8354 tw32(reg, ec->tx_max_coalesced_frames);
8355 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8356 tw32(reg, ec->tx_max_coalesced_frames_irq);
8357 }
8358 }
8359
8360 for (; i < tp->irq_max - 1; i++) {
8361 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
8362 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
8363 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8346 } 8364 }
8365}
8366
8367static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
8368{
8369 int i = 0;
8370 u32 limit = tp->rxq_cnt;
8347 8371
8348 if (!tg3_flag(tp, ENABLE_RSS)) { 8372 if (!tg3_flag(tp, ENABLE_RSS)) {
8349 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); 8373 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
8350 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); 8374 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
8351 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); 8375 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
8376 limit--;
8352 } else { 8377 } else {
8353 tw32(HOSTCC_RXCOL_TICKS, 0); 8378 tw32(HOSTCC_RXCOL_TICKS, 0);
8354 tw32(HOSTCC_RXMAX_FRAMES, 0); 8379 tw32(HOSTCC_RXMAX_FRAMES, 0);
8355 tw32(HOSTCC_RXCOAL_MAXF_INT, 0); 8380 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
8356 } 8381 }
8357 8382
8358 if (!tg3_flag(tp, 5705_PLUS)) { 8383 for (; i < limit; i++) {
8359 u32 val = ec->stats_block_coalesce_usecs;
8360
8361 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8362 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8363
8364 if (!netif_carrier_ok(tp->dev))
8365 val = 0;
8366
8367 tw32(HOSTCC_STAT_COAL_TICKS, val);
8368 }
8369
8370 for (i = 0; i < tp->irq_cnt - 1; i++) {
8371 u32 reg; 8384 u32 reg;
8372 8385
8373 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; 8386 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
@@ -8376,27 +8389,30 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
8376 tw32(reg, ec->rx_max_coalesced_frames); 8389 tw32(reg, ec->rx_max_coalesced_frames);
8377 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; 8390 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
8378 tw32(reg, ec->rx_max_coalesced_frames_irq); 8391 tw32(reg, ec->rx_max_coalesced_frames_irq);
8379
8380 if (tg3_flag(tp, ENABLE_TSS)) {
8381 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8382 tw32(reg, ec->tx_coalesce_usecs);
8383 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8384 tw32(reg, ec->tx_max_coalesced_frames);
8385 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8386 tw32(reg, ec->tx_max_coalesced_frames_irq);
8387 }
8388 } 8392 }
8389 8393
8390 for (; i < tp->irq_max - 1; i++) { 8394 for (; i < tp->irq_max - 1; i++) {
8391 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); 8395 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
8392 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); 8396 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
8393 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); 8397 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8398 }
8399}
8394 8400
8395 if (tg3_flag(tp, ENABLE_TSS)) { 8401static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
8396 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); 8402{
8397 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); 8403 tg3_coal_tx_init(tp, ec);
8398 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); 8404 tg3_coal_rx_init(tp, ec);
8399 } 8405
8406 if (!tg3_flag(tp, 5705_PLUS)) {
8407 u32 val = ec->stats_block_coalesce_usecs;
8408
8409 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8410 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8411
8412 if (!netif_carrier_ok(tp->dev))
8413 val = 0;
8414
8415 tw32(HOSTCC_STAT_COAL_TICKS, val);
8400 } 8416 }
8401} 8417}
8402 8418