diff options
author | Yaniv Rosner <yanivr@broadcom.com> | 2012-11-26 22:46:34 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2012-11-28 10:59:22 -0500 |
commit | 503976e99842665b3ebd6aec602525b9e8f38812 (patch) | |
tree | f1cae8d50529f48db37be88af2de56ca07a09c8e /drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | |
parent | 8203c4b6c9debbf19517cc6594d5d6779e2c57bf (diff) |
bnx2x: Cosmetic changes
This patch makes some cosmetic changes to the code:
1. Code alignment.
2. Merge read-modify-write into a single function (read_or_write /
read_and_write).
3. Merge several write registers into a for-loop write using a static array.
4. Remove empty lines.
5. Fix comments.
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c')
-rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 310 |
1 files changed, 126 insertions, 184 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c index a5d7003eb8b4..661d3ea21635 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | |||
@@ -2176,7 +2176,7 @@ static void bnx2x_update_pfc_nig(struct link_params *params, | |||
2176 | if (CHIP_IS_E3(bp)) | 2176 | if (CHIP_IS_E3(bp)) |
2177 | ppp_enable = 0; | 2177 | ppp_enable = 0; |
2178 | else | 2178 | else |
2179 | ppp_enable = 1; | 2179 | ppp_enable = 1; |
2180 | xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : | 2180 | xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : |
2181 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | 2181 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); |
2182 | xcm_out_en = 0; | 2182 | xcm_out_en = 0; |
@@ -2297,7 +2297,6 @@ int bnx2x_update_pfc(struct link_params *params, | |||
2297 | return bnx2x_status; | 2297 | return bnx2x_status; |
2298 | } | 2298 | } |
2299 | 2299 | ||
2300 | |||
2301 | static int bnx2x_bmac1_enable(struct link_params *params, | 2300 | static int bnx2x_bmac1_enable(struct link_params *params, |
2302 | struct link_vars *vars, | 2301 | struct link_vars *vars, |
2303 | u8 is_lb) | 2302 | u8 is_lb) |
@@ -3713,11 +3712,11 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, | |||
3713 | reg_set[i].val); | 3712 | reg_set[i].val); |
3714 | 3713 | ||
3715 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 3714 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
3716 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); | 3715 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); |
3717 | cl72_ctrl &= 0x08ff; | 3716 | cl72_ctrl &= 0x08ff; |
3718 | cl72_ctrl |= 0x3800; | 3717 | cl72_ctrl |= 0x3800; |
3719 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | 3718 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
3720 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); | 3719 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); |
3721 | 3720 | ||
3722 | /* Check adding advertisement for 1G KX */ | 3721 | /* Check adding advertisement for 1G KX */ |
3723 | if (((vars->line_speed == SPEED_AUTO_NEG) && | 3722 | if (((vars->line_speed == SPEED_AUTO_NEG) && |
@@ -3916,27 +3915,21 @@ static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, | |||
3916 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); | 3915 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); |
3917 | 3916 | ||
3918 | /* Disable 100FX Enable and Auto-Detect */ | 3917 | /* Disable 100FX Enable and Auto-Detect */ |
3919 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 3918 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
3920 | MDIO_WC_REG_FX100_CTRL1, &val); | 3919 | MDIO_WC_REG_FX100_CTRL1, 0xFFFA); |
3921 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | ||
3922 | MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA)); | ||
3923 | 3920 | ||
3924 | /* Disable 100FX Idle detect */ | 3921 | /* Disable 100FX Idle detect */ |
3925 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | 3922 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3926 | MDIO_WC_REG_FX100_CTRL3, 0x0080); | 3923 | MDIO_WC_REG_FX100_CTRL3, 0x0080); |
3927 | 3924 | ||
3928 | /* Set Block address to Remote PHY & Clear forced_speed[5] */ | 3925 | /* Set Block address to Remote PHY & Clear forced_speed[5] */ |
3929 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 3926 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
3930 | MDIO_WC_REG_DIGITAL4_MISC3, &val); | 3927 | MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); |
3931 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | ||
3932 | MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F)); | ||
3933 | 3928 | ||
3934 | /* Turn off auto-detect & fiber mode */ | 3929 | /* Turn off auto-detect & fiber mode */ |
3935 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 3930 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
3936 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val); | 3931 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, |
3937 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | 3932 | 0xFFEE); |
3938 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | ||
3939 | (val & 0xFFEE)); | ||
3940 | 3933 | ||
3941 | /* Set filter_force_link, disable_false_link and parallel_detect */ | 3934 | /* Set filter_force_link, disable_false_link and parallel_detect */ |
3942 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 3935 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
@@ -3998,16 +3991,12 @@ static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, | |||
3998 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); | 3991 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); |
3999 | 3992 | ||
4000 | /* Release tx_fifo_reset */ | 3993 | /* Release tx_fifo_reset */ |
4001 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 3994 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4002 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val); | 3995 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, |
4003 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | 3996 | 0xFFFE); |
4004 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE); | ||
4005 | |||
4006 | /* Release rxSeqStart */ | 3997 | /* Release rxSeqStart */ |
4007 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 3998 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4008 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val); | 3999 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); |
4009 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | ||
4010 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF)); | ||
4011 | } | 4000 | } |
4012 | 4001 | ||
4013 | static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, | 4002 | static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, |
@@ -4130,20 +4119,16 @@ static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, | |||
4130 | u16 val16, digctrl_kx1, digctrl_kx2; | 4119 | u16 val16, digctrl_kx1, digctrl_kx2; |
4131 | 4120 | ||
4132 | /* Clear XFI clock comp in non-10G single lane mode. */ | 4121 | /* Clear XFI clock comp in non-10G single lane mode. */ |
4133 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 4122 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4134 | MDIO_WC_REG_RX66_CONTROL, &val16); | 4123 | MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); |
4135 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | ||
4136 | MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13)); | ||
4137 | 4124 | ||
4138 | bnx2x_warpcore_set_lpi_passthrough(phy, params); | 4125 | bnx2x_warpcore_set_lpi_passthrough(phy, params); |
4139 | 4126 | ||
4140 | if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { | 4127 | if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { |
4141 | /* SGMII Autoneg */ | 4128 | /* SGMII Autoneg */ |
4142 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 4129 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4143 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | 4130 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, |
4144 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | 4131 | 0x1000); |
4145 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, | ||
4146 | val16 | 0x1000); | ||
4147 | DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); | 4132 | DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); |
4148 | } else { | 4133 | } else { |
4149 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 4134 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
@@ -4285,7 +4270,7 @@ static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, | |||
4285 | if ((cfg_pin < PIN_CFG_GPIO0_P0) || | 4270 | if ((cfg_pin < PIN_CFG_GPIO0_P0) || |
4286 | (cfg_pin > PIN_CFG_GPIO3_P1)) { | 4271 | (cfg_pin > PIN_CFG_GPIO3_P1)) { |
4287 | DP(NETIF_MSG_LINK, | 4272 | DP(NETIF_MSG_LINK, |
4288 | "ERROR: Invalid cfg pin %x for module detect indication\n", | 4273 | "No cfg pin %x for module detect indication\n", |
4289 | cfg_pin); | 4274 | cfg_pin); |
4290 | return -EINVAL; | 4275 | return -EINVAL; |
4291 | } | 4276 | } |
@@ -4296,7 +4281,7 @@ static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, | |||
4296 | *gpio_num = MISC_REGISTERS_GPIO_3; | 4281 | *gpio_num = MISC_REGISTERS_GPIO_3; |
4297 | *gpio_port = port; | 4282 | *gpio_port = port; |
4298 | } | 4283 | } |
4299 | DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port); | 4284 | |
4300 | return 0; | 4285 | return 0; |
4301 | } | 4286 | } |
4302 | 4287 | ||
@@ -4319,7 +4304,7 @@ static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, | |||
4319 | return 0; | 4304 | return 0; |
4320 | } | 4305 | } |
4321 | static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, | 4306 | static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, |
4322 | struct link_params *params) | 4307 | struct link_params *params) |
4323 | { | 4308 | { |
4324 | u16 gp2_status_reg0, lane; | 4309 | u16 gp2_status_reg0, lane; |
4325 | struct bnx2x *bp = params->bp; | 4310 | struct bnx2x *bp = params->bp; |
@@ -4333,8 +4318,8 @@ static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, | |||
4333 | } | 4318 | } |
4334 | 4319 | ||
4335 | static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, | 4320 | static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, |
4336 | struct link_params *params, | 4321 | struct link_params *params, |
4337 | struct link_vars *vars) | 4322 | struct link_vars *vars) |
4338 | { | 4323 | { |
4339 | struct bnx2x *bp = params->bp; | 4324 | struct bnx2x *bp = params->bp; |
4340 | u32 serdes_net_if; | 4325 | u32 serdes_net_if; |
@@ -4362,7 +4347,7 @@ static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, | |||
4362 | case PORT_HW_CFG_NET_SERDES_IF_KR: | 4347 | case PORT_HW_CFG_NET_SERDES_IF_KR: |
4363 | /* Do we get link yet? */ | 4348 | /* Do we get link yet? */ |
4364 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, | 4349 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, |
4365 | &gp_status1); | 4350 | &gp_status1); |
4366 | lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ | 4351 | lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ |
4367 | /*10G KR*/ | 4352 | /*10G KR*/ |
4368 | lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; | 4353 | lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; |
@@ -4552,34 +4537,22 @@ static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, | |||
4552 | 4537 | ||
4553 | /* Clear loopback settings (if any) */ | 4538 | /* Clear loopback settings (if any) */ |
4554 | /* 10G & 20G */ | 4539 | /* 10G & 20G */ |
4555 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 4540 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4556 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | 4541 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); |
4557 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | ||
4558 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 & | ||
4559 | 0xBFFF); | ||
4560 | 4542 | ||
4561 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 4543 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4562 | MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16); | 4544 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); |
4563 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | ||
4564 | MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe); | ||
4565 | 4545 | ||
4566 | /* Update those 1-copy registers */ | 4546 | /* Update those 1-copy registers */ |
4567 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | 4547 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
4568 | MDIO_AER_BLOCK_AER_REG, 0); | 4548 | MDIO_AER_BLOCK_AER_REG, 0); |
4569 | /* Enable 1G MDIO (1-copy) */ | 4549 | /* Enable 1G MDIO (1-copy) */ |
4570 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 4550 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4571 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | 4551 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, |
4572 | &val16); | 4552 | ~0x10); |
4573 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | ||
4574 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | ||
4575 | val16 & ~0x10); | ||
4576 | |||
4577 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | ||
4578 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); | ||
4579 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | ||
4580 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, | ||
4581 | val16 & 0xff00); | ||
4582 | 4553 | ||
4554 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, | ||
4555 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); | ||
4583 | lane = bnx2x_get_warpcore_lane(phy, params); | 4556 | lane = bnx2x_get_warpcore_lane(phy, params); |
4584 | /* Disable CL36 PCS Tx */ | 4557 | /* Disable CL36 PCS Tx */ |
4585 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 4558 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
@@ -4634,8 +4607,8 @@ static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, | |||
4634 | if (phy->flags & FLAGS_WC_DUAL_MODE) | 4607 | if (phy->flags & FLAGS_WC_DUAL_MODE) |
4635 | val16 |= (2<<lane); | 4608 | val16 |= (2<<lane); |
4636 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | 4609 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
4637 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, | 4610 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, |
4638 | val16); | 4611 | val16); |
4639 | 4612 | ||
4640 | /* Switch back to 4-copy registers */ | 4613 | /* Switch back to 4-copy registers */ |
4641 | bnx2x_set_aer_mmd(params, phy); | 4614 | bnx2x_set_aer_mmd(params, phy); |
@@ -6911,7 +6884,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars) | |||
6911 | } else if (prev_line_speed != vars->line_speed) { | 6884 | } else if (prev_line_speed != vars->line_speed) { |
6912 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, | 6885 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, |
6913 | 0); | 6886 | 0); |
6914 | usleep_range(1000, 2000); | 6887 | usleep_range(1000, 2000); |
6915 | } | 6888 | } |
6916 | } | 6889 | } |
6917 | 6890 | ||
@@ -6981,7 +6954,7 @@ void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) | |||
6981 | { | 6954 | { |
6982 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | 6955 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
6983 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); | 6956 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
6984 | usleep_range(1000, 2000); | 6957 | usleep_range(1000, 2000); |
6985 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | 6958 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
6986 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); | 6959 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); |
6987 | } | 6960 | } |
@@ -7122,7 +7095,7 @@ static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, | |||
7122 | MDIO_PMA_DEVAD, | 7095 | MDIO_PMA_DEVAD, |
7123 | MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); | 7096 | MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); |
7124 | 7097 | ||
7125 | usleep_range(1000, 2000); | 7098 | usleep_range(1000, 2000); |
7126 | } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || | 7099 | } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || |
7127 | ((fw_msgout & 0xff) != 0x03 && (phy->type == | 7100 | ((fw_msgout & 0xff) != 0x03 && (phy->type == |
7128 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); | 7101 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); |
@@ -7832,7 +7805,7 @@ static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, | |||
7832 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == | 7805 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7833 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | 7806 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) |
7834 | return 0; | 7807 | return 0; |
7835 | usleep_range(1000, 2000); | 7808 | usleep_range(1000, 2000); |
7836 | } | 7809 | } |
7837 | return -EINVAL; | 7810 | return -EINVAL; |
7838 | } | 7811 | } |
@@ -7942,7 +7915,7 @@ static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, | |||
7942 | /* Wait appropriate time for two-wire command to finish before | 7915 | /* Wait appropriate time for two-wire command to finish before |
7943 | * polling the status register | 7916 | * polling the status register |
7944 | */ | 7917 | */ |
7945 | usleep_range(1000, 2000); | 7918 | usleep_range(1000, 2000); |
7946 | 7919 | ||
7947 | /* Wait up to 500us for command complete status */ | 7920 | /* Wait up to 500us for command complete status */ |
7948 | for (i = 0; i < 100; i++) { | 7921 | for (i = 0; i < 100; i++) { |
@@ -7978,7 +7951,7 @@ static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, | |||
7978 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == | 7951 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7979 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | 7952 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) |
7980 | return 0; | 7953 | return 0; |
7981 | usleep_range(1000, 2000); | 7954 | usleep_range(1000, 2000); |
7982 | } | 7955 | } |
7983 | 7956 | ||
7984 | return -EINVAL; | 7957 | return -EINVAL; |
@@ -9517,7 +9490,15 @@ static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | |||
9517 | struct bnx2x *bp, | 9490 | struct bnx2x *bp, |
9518 | u8 port) | 9491 | u8 port) |
9519 | { | 9492 | { |
9520 | u16 val, fw_ver1, fw_ver2, cnt; | 9493 | u16 val, fw_ver2, cnt, i; |
9494 | static struct bnx2x_reg_set reg_set[] = { | ||
9495 | {MDIO_PMA_DEVAD, 0xA819, 0x0014}, | ||
9496 | {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, | ||
9497 | {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, | ||
9498 | {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, | ||
9499 | {MDIO_PMA_DEVAD, 0xA817, 0x0009} | ||
9500 | }; | ||
9501 | u16 fw_ver1; | ||
9521 | 9502 | ||
9522 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || | 9503 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
9523 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { | 9504 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { |
@@ -9527,11 +9508,10 @@ static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | |||
9527 | } else { | 9508 | } else { |
9528 | /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ | 9509 | /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ |
9529 | /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ | 9510 | /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ |
9530 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014); | 9511 | for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); |
9531 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | 9512 | i++) |
9532 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000); | 9513 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, |
9533 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300); | 9514 | reg_set[i].reg, reg_set[i].val); |
9534 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009); | ||
9535 | 9515 | ||
9536 | for (cnt = 0; cnt < 100; cnt++) { | 9516 | for (cnt = 0; cnt < 100; cnt++) { |
9537 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | 9517 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); |
@@ -9579,8 +9559,16 @@ static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | |||
9579 | static void bnx2x_848xx_set_led(struct bnx2x *bp, | 9559 | static void bnx2x_848xx_set_led(struct bnx2x *bp, |
9580 | struct bnx2x_phy *phy) | 9560 | struct bnx2x_phy *phy) |
9581 | { | 9561 | { |
9582 | u16 val, offset; | 9562 | u16 val, offset, i; |
9583 | 9563 | static struct bnx2x_reg_set reg_set[] = { | |
9564 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, | ||
9565 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, | ||
9566 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, | ||
9567 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, | ||
9568 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, | ||
9569 | MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, | ||
9570 | {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} | ||
9571 | }; | ||
9584 | /* PHYC_CTL_LED_CTL */ | 9572 | /* PHYC_CTL_LED_CTL */ |
9585 | bnx2x_cl45_read(bp, phy, | 9573 | bnx2x_cl45_read(bp, phy, |
9586 | MDIO_PMA_DEVAD, | 9574 | MDIO_PMA_DEVAD, |
@@ -9592,33 +9580,9 @@ static void bnx2x_848xx_set_led(struct bnx2x *bp, | |||
9592 | MDIO_PMA_DEVAD, | 9580 | MDIO_PMA_DEVAD, |
9593 | MDIO_PMA_REG_8481_LINK_SIGNAL, val); | 9581 | MDIO_PMA_REG_8481_LINK_SIGNAL, val); |
9594 | 9582 | ||
9595 | bnx2x_cl45_write(bp, phy, | 9583 | for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); i++) |
9596 | MDIO_PMA_DEVAD, | 9584 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
9597 | MDIO_PMA_REG_8481_LED1_MASK, | 9585 | reg_set[i].val); |
9598 | 0x80); | ||
9599 | |||
9600 | bnx2x_cl45_write(bp, phy, | ||
9601 | MDIO_PMA_DEVAD, | ||
9602 | MDIO_PMA_REG_8481_LED2_MASK, | ||
9603 | 0x18); | ||
9604 | |||
9605 | /* Select activity source by Tx and Rx, as suggested by PHY AE */ | ||
9606 | bnx2x_cl45_write(bp, phy, | ||
9607 | MDIO_PMA_DEVAD, | ||
9608 | MDIO_PMA_REG_8481_LED3_MASK, | ||
9609 | 0x0006); | ||
9610 | |||
9611 | /* Select the closest activity blink rate to that in 10/100/1000 */ | ||
9612 | bnx2x_cl45_write(bp, phy, | ||
9613 | MDIO_PMA_DEVAD, | ||
9614 | MDIO_PMA_REG_8481_LED3_BLINK, | ||
9615 | 0); | ||
9616 | |||
9617 | /* Configure the blink rate to ~15.9 Hz */ | ||
9618 | bnx2x_cl45_write(bp, phy, | ||
9619 | MDIO_PMA_DEVAD, | ||
9620 | MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, | ||
9621 | MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ); | ||
9622 | 9586 | ||
9623 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || | 9587 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
9624 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) | 9588 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) |
@@ -9626,16 +9590,10 @@ static void bnx2x_848xx_set_led(struct bnx2x *bp, | |||
9626 | else | 9590 | else |
9627 | offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; | 9591 | offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; |
9628 | 9592 | ||
9629 | bnx2x_cl45_read(bp, phy, | 9593 | /* stretch_en for LED3*/ |
9630 | MDIO_PMA_DEVAD, offset, &val); | 9594 | bnx2x_cl45_read_or_write(bp, phy, |
9631 | val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/ | 9595 | MDIO_PMA_DEVAD, offset, |
9632 | bnx2x_cl45_write(bp, phy, | 9596 | MDIO_PMA_REG_84823_LED3_STRETCH_EN); |
9633 | MDIO_PMA_DEVAD, offset, val); | ||
9634 | |||
9635 | /* 'Interrupt Mask' */ | ||
9636 | bnx2x_cl45_write(bp, phy, | ||
9637 | MDIO_AN_DEVAD, | ||
9638 | 0xFFFB, 0xFFFD); | ||
9639 | } | 9597 | } |
9640 | 9598 | ||
9641 | static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, | 9599 | static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, |
@@ -9667,7 +9625,7 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, | |||
9667 | struct link_vars *vars) | 9625 | struct link_vars *vars) |
9668 | { | 9626 | { |
9669 | struct bnx2x *bp = params->bp; | 9627 | struct bnx2x *bp = params->bp; |
9670 | u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val; | 9628 | u16 autoneg_val, an_1000_val, an_10_100_val; |
9671 | 9629 | ||
9672 | bnx2x_848xx_specific_func(phy, params, PHY_INIT); | 9630 | bnx2x_848xx_specific_func(phy, params, PHY_INIT); |
9673 | bnx2x_cl45_write(bp, phy, | 9631 | bnx2x_cl45_write(bp, phy, |
@@ -9771,7 +9729,7 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, | |||
9771 | */ | 9729 | */ |
9772 | if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && | 9730 | if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && |
9773 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || | 9731 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || |
9774 | ((autoneg_val & (1<<12)) == 0)) | 9732 | ((autoneg_val & (1<<12)) == 0)) |
9775 | bnx2x_cl45_write(bp, phy, | 9733 | bnx2x_cl45_write(bp, phy, |
9776 | MDIO_AN_DEVAD, | 9734 | MDIO_AN_DEVAD, |
9777 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); | 9735 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); |
@@ -9783,14 +9741,11 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, | |||
9783 | DP(NETIF_MSG_LINK, "Advertising 10G\n"); | 9741 | DP(NETIF_MSG_LINK, "Advertising 10G\n"); |
9784 | /* Restart autoneg for 10G*/ | 9742 | /* Restart autoneg for 10G*/ |
9785 | 9743 | ||
9786 | bnx2x_cl45_read(bp, phy, | 9744 | bnx2x_cl45_read_or_write( |
9787 | MDIO_AN_DEVAD, | 9745 | bp, phy, |
9788 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | 9746 | MDIO_AN_DEVAD, |
9789 | &an_10g_val); | 9747 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, |
9790 | bnx2x_cl45_write(bp, phy, | 9748 | 0x1000); |
9791 | MDIO_AN_DEVAD, | ||
9792 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | ||
9793 | an_10g_val | 0x1000); | ||
9794 | bnx2x_cl45_write(bp, phy, | 9749 | bnx2x_cl45_write(bp, phy, |
9795 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, | 9750 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, |
9796 | 0x3200); | 9751 | 0x3200); |
@@ -9823,9 +9778,8 @@ static int bnx2x_8481_config_init(struct bnx2x_phy *phy, | |||
9823 | #define PHY84833_CMDHDLR_WAIT 300 | 9778 | #define PHY84833_CMDHDLR_WAIT 300 |
9824 | #define PHY84833_CMDHDLR_MAX_ARGS 5 | 9779 | #define PHY84833_CMDHDLR_MAX_ARGS 5 |
9825 | static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, | 9780 | static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, |
9826 | struct link_params *params, | 9781 | struct link_params *params, u16 fw_cmd, |
9827 | u16 fw_cmd, | 9782 | u16 cmd_args[], int argc) |
9828 | u16 cmd_args[], int argc) | ||
9829 | { | 9783 | { |
9830 | int idx; | 9784 | int idx; |
9831 | u16 val; | 9785 | u16 val; |
@@ -9839,7 +9793,7 @@ static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, | |||
9839 | MDIO_84833_CMD_HDLR_STATUS, &val); | 9793 | MDIO_84833_CMD_HDLR_STATUS, &val); |
9840 | if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) | 9794 | if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) |
9841 | break; | 9795 | break; |
9842 | usleep_range(1000, 2000); | 9796 | usleep_range(1000, 2000); |
9843 | } | 9797 | } |
9844 | if (idx >= PHY84833_CMDHDLR_WAIT) { | 9798 | if (idx >= PHY84833_CMDHDLR_WAIT) { |
9845 | DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); | 9799 | DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); |
@@ -9860,7 +9814,7 @@ static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, | |||
9860 | if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || | 9814 | if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || |
9861 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) | 9815 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) |
9862 | break; | 9816 | break; |
9863 | usleep_range(1000, 2000); | 9817 | usleep_range(1000, 2000); |
9864 | } | 9818 | } |
9865 | if ((idx >= PHY84833_CMDHDLR_WAIT) || | 9819 | if ((idx >= PHY84833_CMDHDLR_WAIT) || |
9866 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { | 9820 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { |
@@ -9879,7 +9833,6 @@ static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, | |||
9879 | return 0; | 9833 | return 0; |
9880 | } | 9834 | } |
9881 | 9835 | ||
9882 | |||
9883 | static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, | 9836 | static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, |
9884 | struct link_params *params, | 9837 | struct link_params *params, |
9885 | struct link_vars *vars) | 9838 | struct link_vars *vars) |
@@ -10027,11 +9980,11 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, | |||
10027 | struct bnx2x *bp = params->bp; | 9980 | struct bnx2x *bp = params->bp; |
10028 | u8 port, initialize = 1; | 9981 | u8 port, initialize = 1; |
10029 | u16 val; | 9982 | u16 val; |
10030 | u32 actual_phy_selection, cms_enable; | 9983 | u32 actual_phy_selection; |
10031 | u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; | 9984 | u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; |
10032 | int rc = 0; | 9985 | int rc = 0; |
10033 | 9986 | ||
10034 | usleep_range(1000, 2000); | 9987 | usleep_range(1000, 2000); |
10035 | 9988 | ||
10036 | if (!(CHIP_IS_E1x(bp))) | 9989 | if (!(CHIP_IS_E1x(bp))) |
10037 | port = BP_PATH(bp); | 9990 | port = BP_PATH(bp); |
@@ -10131,7 +10084,7 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, | |||
10131 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); | 10084 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); |
10132 | /* 84833 PHY has a better feature and doesn't need to support this. */ | 10085 | /* 84833 PHY has a better feature and doesn't need to support this. */ |
10133 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | 10086 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { |
10134 | cms_enable = REG_RD(bp, params->shmem_base + | 10087 | u32 cms_enable = REG_RD(bp, params->shmem_base + |
10135 | offsetof(struct shmem_region, | 10088 | offsetof(struct shmem_region, |
10136 | dev_info.port_hw_config[params->port].default_cfg)) & | 10089 | dev_info.port_hw_config[params->port].default_cfg)) & |
10137 | PORT_HW_CFG_ENABLE_CMS_MASK; | 10090 | PORT_HW_CFG_ENABLE_CMS_MASK; |
@@ -10178,13 +10131,10 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, | |||
10178 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || | 10131 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
10179 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { | 10132 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { |
10180 | /* Bring PHY out of super isolate mode as the final step. */ | 10133 | /* Bring PHY out of super isolate mode as the final step. */ |
10181 | bnx2x_cl45_read(bp, phy, | 10134 | bnx2x_cl45_read_and_write(bp, phy, |
10182 | MDIO_CTL_DEVAD, | 10135 | MDIO_CTL_DEVAD, |
10183 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); | 10136 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, |
10184 | val &= ~MDIO_84833_SUPER_ISOLATE; | 10137 | (u16)~MDIO_84833_SUPER_ISOLATE); |
10185 | bnx2x_cl45_write(bp, phy, | ||
10186 | MDIO_CTL_DEVAD, | ||
10187 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); | ||
10188 | } | 10138 | } |
10189 | return rc; | 10139 | return rc; |
10190 | } | 10140 | } |
@@ -10318,7 +10268,6 @@ static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, | |||
10318 | return link_up; | 10268 | return link_up; |
10319 | } | 10269 | } |
10320 | 10270 | ||
10321 | |||
10322 | static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) | 10271 | static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) |
10323 | { | 10272 | { |
10324 | int status = 0; | 10273 | int status = 0; |
@@ -11190,7 +11139,7 @@ static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, | |||
11190 | /* STATIC PHY DECLARATION */ | 11139 | /* STATIC PHY DECLARATION */ |
11191 | /******************************************************************/ | 11140 | /******************************************************************/ |
11192 | 11141 | ||
11193 | static struct bnx2x_phy phy_null = { | 11142 | static const struct bnx2x_phy phy_null = { |
11194 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, | 11143 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, |
11195 | .addr = 0, | 11144 | .addr = 0, |
11196 | .def_md_devad = 0, | 11145 | .def_md_devad = 0, |
@@ -11216,7 +11165,7 @@ static struct bnx2x_phy phy_null = { | |||
11216 | .phy_specific_func = (phy_specific_func_t)NULL | 11165 | .phy_specific_func = (phy_specific_func_t)NULL |
11217 | }; | 11166 | }; |
11218 | 11167 | ||
11219 | static struct bnx2x_phy phy_serdes = { | 11168 | static const struct bnx2x_phy phy_serdes = { |
11220 | .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, | 11169 | .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, |
11221 | .addr = 0xff, | 11170 | .addr = 0xff, |
11222 | .def_md_devad = 0, | 11171 | .def_md_devad = 0, |
@@ -11251,7 +11200,7 @@ static struct bnx2x_phy phy_serdes = { | |||
11251 | .phy_specific_func = (phy_specific_func_t)NULL | 11200 | .phy_specific_func = (phy_specific_func_t)NULL |
11252 | }; | 11201 | }; |
11253 | 11202 | ||
11254 | static struct bnx2x_phy phy_xgxs = { | 11203 | static const struct bnx2x_phy phy_xgxs = { |
11255 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | 11204 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, |
11256 | .addr = 0xff, | 11205 | .addr = 0xff, |
11257 | .def_md_devad = 0, | 11206 | .def_md_devad = 0, |
@@ -11286,7 +11235,7 @@ static struct bnx2x_phy phy_xgxs = { | |||
11286 | .set_link_led = (set_link_led_t)NULL, | 11235 | .set_link_led = (set_link_led_t)NULL, |
11287 | .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func | 11236 | .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func |
11288 | }; | 11237 | }; |
11289 | static struct bnx2x_phy phy_warpcore = { | 11238 | static const struct bnx2x_phy phy_warpcore = { |
11290 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | 11239 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, |
11291 | .addr = 0xff, | 11240 | .addr = 0xff, |
11292 | .def_md_devad = 0, | 11241 | .def_md_devad = 0, |
@@ -11324,7 +11273,7 @@ static struct bnx2x_phy phy_warpcore = { | |||
11324 | }; | 11273 | }; |
11325 | 11274 | ||
11326 | 11275 | ||
11327 | static struct bnx2x_phy phy_7101 = { | 11276 | static const struct bnx2x_phy phy_7101 = { |
11328 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, | 11277 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, |
11329 | .addr = 0xff, | 11278 | .addr = 0xff, |
11330 | .def_md_devad = 0, | 11279 | .def_md_devad = 0, |
@@ -11353,7 +11302,7 @@ static struct bnx2x_phy phy_7101 = { | |||
11353 | .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, | 11302 | .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, |
11354 | .phy_specific_func = (phy_specific_func_t)NULL | 11303 | .phy_specific_func = (phy_specific_func_t)NULL |
11355 | }; | 11304 | }; |
11356 | static struct bnx2x_phy phy_8073 = { | 11305 | static const struct bnx2x_phy phy_8073 = { |
11357 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, | 11306 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, |
11358 | .addr = 0xff, | 11307 | .addr = 0xff, |
11359 | .def_md_devad = 0, | 11308 | .def_md_devad = 0, |
@@ -11384,7 +11333,7 @@ static struct bnx2x_phy phy_8073 = { | |||
11384 | .set_link_led = (set_link_led_t)NULL, | 11333 | .set_link_led = (set_link_led_t)NULL, |
11385 | .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func | 11334 | .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func |
11386 | }; | 11335 | }; |
11387 | static struct bnx2x_phy phy_8705 = { | 11336 | static const struct bnx2x_phy phy_8705 = { |
11388 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, | 11337 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, |
11389 | .addr = 0xff, | 11338 | .addr = 0xff, |
11390 | .def_md_devad = 0, | 11339 | .def_md_devad = 0, |
@@ -11412,7 +11361,7 @@ static struct bnx2x_phy phy_8705 = { | |||
11412 | .set_link_led = (set_link_led_t)NULL, | 11361 | .set_link_led = (set_link_led_t)NULL, |
11413 | .phy_specific_func = (phy_specific_func_t)NULL | 11362 | .phy_specific_func = (phy_specific_func_t)NULL |
11414 | }; | 11363 | }; |
11415 | static struct bnx2x_phy phy_8706 = { | 11364 | static const struct bnx2x_phy phy_8706 = { |
11416 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, | 11365 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, |
11417 | .addr = 0xff, | 11366 | .addr = 0xff, |
11418 | .def_md_devad = 0, | 11367 | .def_md_devad = 0, |
@@ -11442,7 +11391,7 @@ static struct bnx2x_phy phy_8706 = { | |||
11442 | .phy_specific_func = (phy_specific_func_t)NULL | 11391 | .phy_specific_func = (phy_specific_func_t)NULL |
11443 | }; | 11392 | }; |
11444 | 11393 | ||
11445 | static struct bnx2x_phy phy_8726 = { | 11394 | static const struct bnx2x_phy phy_8726 = { |
11446 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, | 11395 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, |
11447 | .addr = 0xff, | 11396 | .addr = 0xff, |
11448 | .def_md_devad = 0, | 11397 | .def_md_devad = 0, |
@@ -11474,7 +11423,7 @@ static struct bnx2x_phy phy_8726 = { | |||
11474 | .phy_specific_func = (phy_specific_func_t)NULL | 11423 | .phy_specific_func = (phy_specific_func_t)NULL |
11475 | }; | 11424 | }; |
11476 | 11425 | ||
11477 | static struct bnx2x_phy phy_8727 = { | 11426 | static const struct bnx2x_phy phy_8727 = { |
11478 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, | 11427 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, |
11479 | .addr = 0xff, | 11428 | .addr = 0xff, |
11480 | .def_md_devad = 0, | 11429 | .def_md_devad = 0, |
@@ -11504,7 +11453,7 @@ static struct bnx2x_phy phy_8727 = { | |||
11504 | .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, | 11453 | .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, |
11505 | .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func | 11454 | .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func |
11506 | }; | 11455 | }; |
11507 | static struct bnx2x_phy phy_8481 = { | 11456 | static const struct bnx2x_phy phy_8481 = { |
11508 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, | 11457 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, |
11509 | .addr = 0xff, | 11458 | .addr = 0xff, |
11510 | .def_md_devad = 0, | 11459 | .def_md_devad = 0, |
@@ -11540,7 +11489,7 @@ static struct bnx2x_phy phy_8481 = { | |||
11540 | .phy_specific_func = (phy_specific_func_t)NULL | 11489 | .phy_specific_func = (phy_specific_func_t)NULL |
11541 | }; | 11490 | }; |
11542 | 11491 | ||
11543 | static struct bnx2x_phy phy_84823 = { | 11492 | static const struct bnx2x_phy phy_84823 = { |
11544 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, | 11493 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, |
11545 | .addr = 0xff, | 11494 | .addr = 0xff, |
11546 | .def_md_devad = 0, | 11495 | .def_md_devad = 0, |
@@ -11577,7 +11526,7 @@ static struct bnx2x_phy phy_84823 = { | |||
11577 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func | 11526 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func |
11578 | }; | 11527 | }; |
11579 | 11528 | ||
11580 | static struct bnx2x_phy phy_84833 = { | 11529 | static const struct bnx2x_phy phy_84833 = { |
11581 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, | 11530 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, |
11582 | .addr = 0xff, | 11531 | .addr = 0xff, |
11583 | .def_md_devad = 0, | 11532 | .def_md_devad = 0, |
@@ -11646,7 +11595,7 @@ static const struct bnx2x_phy phy_84834 = { | |||
11646 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func | 11595 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func |
11647 | }; | 11596 | }; |
11648 | 11597 | ||
11649 | static struct bnx2x_phy phy_54618se = { | 11598 | static const struct bnx2x_phy phy_54618se = { |
11650 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, | 11599 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, |
11651 | .addr = 0xff, | 11600 | .addr = 0xff, |
11652 | .def_md_devad = 0, | 11601 | .def_md_devad = 0, |
@@ -12123,7 +12072,6 @@ u32 bnx2x_phy_selection(struct link_params *params) | |||
12123 | return return_cfg; | 12072 | return return_cfg; |
12124 | } | 12073 | } |
12125 | 12074 | ||
12126 | |||
12127 | int bnx2x_phy_probe(struct link_params *params) | 12075 | int bnx2x_phy_probe(struct link_params *params) |
12128 | { | 12076 | { |
12129 | u8 phy_index, actual_phy_idx; | 12077 | u8 phy_index, actual_phy_idx; |
@@ -12283,11 +12231,11 @@ static void bnx2x_init_xgxs_loopback(struct link_params *params, | |||
12283 | { | 12231 | { |
12284 | struct bnx2x *bp = params->bp; | 12232 | struct bnx2x *bp = params->bp; |
12285 | struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; | 12233 | struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; |
12286 | vars->link_up = 1; | 12234 | vars->link_up = 1; |
12287 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | 12235 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
12288 | vars->duplex = DUPLEX_FULL; | 12236 | vars->duplex = DUPLEX_FULL; |
12289 | if (params->req_line_speed[0] == SPEED_1000) | 12237 | if (params->req_line_speed[0] == SPEED_1000) |
12290 | vars->line_speed = SPEED_1000; | 12238 | vars->line_speed = SPEED_1000; |
12291 | else if ((params->req_line_speed[0] == SPEED_20000) || | 12239 | else if ((params->req_line_speed[0] == SPEED_20000) || |
12292 | (int_phy->flags & FLAGS_WC_DUAL_MODE)) | 12240 | (int_phy->flags & FLAGS_WC_DUAL_MODE)) |
12293 | vars->line_speed = SPEED_20000; | 12241 | vars->line_speed = SPEED_20000; |
@@ -12312,24 +12260,20 @@ static void bnx2x_init_xgxs_loopback(struct link_params *params, | |||
12312 | bnx2x_bmac_enable(params, vars, 0, 1); | 12260 | bnx2x_bmac_enable(params, vars, 0, 1); |
12313 | } | 12261 | } |
12314 | 12262 | ||
12315 | if (params->loopback_mode == LOOPBACK_XGXS) { | 12263 | if (params->loopback_mode == LOOPBACK_XGXS) { |
12316 | /* set 10G XGXS loopback */ | 12264 | /* Set 10G XGXS loopback */ |
12317 | params->phy[INT_PHY].config_loopback( | 12265 | int_phy->config_loopback(int_phy, params); |
12318 | ¶ms->phy[INT_PHY], | 12266 | } else { |
12319 | params); | 12267 | /* Set external phy loopback */ |
12320 | 12268 | u8 phy_index; | |
12321 | } else { | 12269 | for (phy_index = EXT_PHY1; |
12322 | /* set external phy loopback */ | 12270 | phy_index < params->num_phys; phy_index++) |
12323 | u8 phy_index; | 12271 | if (params->phy[phy_index].config_loopback) |
12324 | for (phy_index = EXT_PHY1; | 12272 | params->phy[phy_index].config_loopback( |
12325 | phy_index < params->num_phys; phy_index++) { | 12273 | ¶ms->phy[phy_index], |
12326 | if (params->phy[phy_index].config_loopback) | 12274 | params); |
12327 | params->phy[phy_index].config_loopback( | 12275 | } |
12328 | ¶ms->phy[phy_index], | 12276 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
12329 | params); | ||
12330 | } | ||
12331 | } | ||
12332 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | ||
12333 | 12277 | ||
12334 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); | 12278 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
12335 | } | 12279 | } |
@@ -12339,7 +12283,7 @@ void bnx2x_set_rx_filter(struct link_params *params, u8 en) | |||
12339 | struct bnx2x *bp = params->bp; | 12283 | struct bnx2x *bp = params->bp; |
12340 | u8 val = en * 0x1F; | 12284 | u8 val = en * 0x1F; |
12341 | 12285 | ||
12342 | /* Open the gate between the NIG to the BRB */ | 12286 | /* Open / close the gate between the NIG and the BRB */ |
12343 | if (!CHIP_IS_E1x(bp)) | 12287 | if (!CHIP_IS_E1x(bp)) |
12344 | val |= en * 0x20; | 12288 | val |= en * 0x20; |
12345 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); | 12289 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); |
@@ -12964,7 +12908,7 @@ static int bnx2x_8727_common_init_phy(struct bnx2x *bp, | |||
12964 | /* Initiate PHY reset*/ | 12908 | /* Initiate PHY reset*/ |
12965 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, | 12909 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, |
12966 | port); | 12910 | port); |
12967 | usleep_range(1000, 2000); | 12911 | usleep_range(1000, 2000); |
12968 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, | 12912 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
12969 | port); | 12913 | port); |
12970 | 12914 | ||
@@ -13063,7 +13007,7 @@ static int bnx2x_84833_pre_init_phy(struct bnx2x *bp, | |||
13063 | MDIO_PMA_REG_CTRL, &val); | 13007 | MDIO_PMA_REG_CTRL, &val); |
13064 | if (!(val & (1<<15))) | 13008 | if (!(val & (1<<15))) |
13065 | break; | 13009 | break; |
13066 | usleep_range(1000, 2000); | 13010 | usleep_range(1000, 2000); |
13067 | } | 13011 | } |
13068 | if (cnt >= 1500) { | 13012 | if (cnt >= 1500) { |
13069 | DP(NETIF_MSG_LINK, "84833 reset timeout\n"); | 13013 | DP(NETIF_MSG_LINK, "84833 reset timeout\n"); |
@@ -13555,9 +13499,7 @@ void bnx2x_period_func(struct link_params *params, struct link_vars *vars) | |||
13555 | bnx2x_update_mng(params, vars->link_status); | 13499 | bnx2x_update_mng(params, vars->link_status); |
13556 | } | 13500 | } |
13557 | } | 13501 | } |
13558 | |||
13559 | } | 13502 | } |
13560 | |||
13561 | } | 13503 | } |
13562 | 13504 | ||
13563 | u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, | 13505 | u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, |