bcm63xx_enet: add support for Broadcom BCM63xx integrated gigabit switch

Newer Broadcom BCM63xx SoCs: 6328, 6362 and 6368 have an integrated switch
which needs to be driven slightly differently from the traditional
external switches. This patch introduces changes in arch/mips/bcm63xx in order
to:

- register a bcm63xx_enetsw driver instead of bcm63xx_enet driver
- update DMA channels configuration & state RAM base addresses
- add a new platform data configuration knob to define the number of
  ports per switch/device and force link on some ports
- define the required switch registers

On the driver side, the following changes are required:

- the switch ports need to be polled to ensure the link is up and
  running and RX/TX can properly work
- basic switch configuration needs to be performed for the switch to
  forward packets to the CPU
- update the MIB counters since the integrated

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 71 insertions, 0 deletions

diff --git a/drivers/net/ethernet/broadcom/bcm63xx_enet.h b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
index 133d5857b9e2..721ffbaef8d2 100644
--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
@@ -18,6 +18,7 @@
 
 /* maximum burst len for dma (4 bytes unit) */
 #define BCMENET_DMA_MAXBURST    16
+#define BCMENETSW_DMA_MAXBURST  8
 
 /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
  * must be low enough so that a DMA transfer of above burst length can
@@ -84,11 +85,60 @@
 #define ETH_MIB_RX_CNTRL                        54
 
 
+/*
+ * SW MIB Counters register definitions
+*/
+#define ETHSW_MIB_TX_ALL_OCT                    0
+#define ETHSW_MIB_TX_DROP_PKTS                  2
+#define ETHSW_MIB_TX_QOS_PKTS                   3
+#define ETHSW_MIB_TX_BRDCAST                    4
+#define ETHSW_MIB_TX_MULT                       5
+#define ETHSW_MIB_TX_UNI                        6
+#define ETHSW_MIB_TX_COL                        7
+#define ETHSW_MIB_TX_1_COL                      8
+#define ETHSW_MIB_TX_M_COL                      9
+#define ETHSW_MIB_TX_DEF                        10
+#define ETHSW_MIB_TX_LATE                       11
+#define ETHSW_MIB_TX_EX_COL                     12
+#define ETHSW_MIB_TX_PAUSE                      14
+#define ETHSW_MIB_TX_QOS_OCT                    15
+
+#define ETHSW_MIB_RX_ALL_OCT                    17
+#define ETHSW_MIB_RX_UND                        19
+#define ETHSW_MIB_RX_PAUSE                      20
+#define ETHSW_MIB_RX_64                         21
+#define ETHSW_MIB_RX_65_127                     22
+#define ETHSW_MIB_RX_128_255                    23
+#define ETHSW_MIB_RX_256_511                    24
+#define ETHSW_MIB_RX_512_1023                   25
+#define ETHSW_MIB_RX_1024_1522                  26
+#define ETHSW_MIB_RX_OVR                        27
+#define ETHSW_MIB_RX_JAB                        28
+#define ETHSW_MIB_RX_ALIGN                      29
+#define ETHSW_MIB_RX_CRC                        30
+#define ETHSW_MIB_RX_GD_OCT                     31
+#define ETHSW_MIB_RX_DROP                       33
+#define ETHSW_MIB_RX_UNI                        34
+#define ETHSW_MIB_RX_MULT                       35
+#define ETHSW_MIB_RX_BRDCAST                    36
+#define ETHSW_MIB_RX_SA_CHANGE                  37
+#define ETHSW_MIB_RX_FRAG                       38
+#define ETHSW_MIB_RX_OVR_DISC                   39
+#define ETHSW_MIB_RX_SYM                        40
+#define ETHSW_MIB_RX_QOS_PKTS                   41
+#define ETHSW_MIB_RX_QOS_OCT                    42
+#define ETHSW_MIB_RX_1523_2047                  44
+#define ETHSW_MIB_RX_2048_4095                  45
+#define ETHSW_MIB_RX_4096_8191                  46
+#define ETHSW_MIB_RX_8192_9728                  47
+
+
 struct bcm_enet_mib_counters {
         u64 tx_gd_octets;
         u32 tx_gd_pkts;
         u32 tx_all_octets;
         u32 tx_all_pkts;
+        u32 tx_unicast;
         u32 tx_brdcast;
         u32 tx_mult;
         u32 tx_64;
@@ -97,7 +147,12 @@ struct bcm_enet_mib_counters {
         u32 tx_256_511;
         u32 tx_512_1023;
         u32 tx_1024_max;
+        u32 tx_1523_2047;
+        u32 tx_2048_4095;
+        u32 tx_4096_8191;
+        u32 tx_8192_9728;
         u32 tx_jab;
+        u32 tx_drop;
         u32 tx_ovr;
         u32 tx_frag;
         u32 tx_underrun;
@@ -114,6 +169,7 @@ struct bcm_enet_mib_counters {
         u32 rx_all_octets;
         u32 rx_all_pkts;
         u32 rx_brdcast;
+        u32 rx_unicast;
         u32 rx_mult;
         u32 rx_64;
         u32 rx_65_127;
@@ -197,6 +253,9 @@ struct bcm_enet_priv {
         /* number of dma desc in tx ring */
         int tx_ring_size;
 
+        /* maximum dma burst size */
+        int dma_maxburst;
+
         /* cpu view of rx dma ring */
         struct bcm_enet_desc *tx_desc_cpu;
 
@@ -269,6 +328,18 @@ struct bcm_enet_priv {
 
         /* maximum hardware transmit/receive size */
         unsigned int hw_mtu;
+
+        bool enet_is_sw;
+
+        /* port mapping for switch devices */
+        int num_ports;
+        struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
+        int sw_port_link[ENETSW_MAX_PORT];
+
+        /* used to poll switch port state */
+        struct timer_list swphy_poll;
+        spinlock_t enetsw_mdio_lock;
 };
 
+
 #endif /* ! BCM63XX_ENET_H_ */