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authorHuang, Xiong <xiong@qca.qualcomm.com>2012-04-18 18:01:28 -0400
committerDavid S. Miller <davem@davemloft.net>2012-04-19 20:14:20 -0400
commit024e1e4dcde98eff0fa5bf2881e4b304c147bd86 (patch)
tree31ae0fcb37f8dce374e2fe3b361cd604775407bf /drivers/net/ethernet/atheros
parent5cbdcc2f49b4a8372052952799d2cb1de387443b (diff)
atl1c: refine/update ASPM configuration
some platforms(BIOS or OS) may change ASPM configuration in PCI Express Link Control Register directly and dynamically regardless the device driver installation. Checking if ASPM support during the driver init phase by reading PCI Express Link Contrl Register doesn't make sense. This refine/update assume L0S/L1 is defalut enabled as hw->ctrl_flags inited. atl1c_set_aspm will set real configuration based on chip capability to hardware register. atl1c_disable_l0s_l1 and register definition of REG_PM_CTRL are refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/atheros')
-rw-r--r--drivers/net/ethernet/atheros/atl1c/atl1c_hw.h66
-rw-r--r--drivers/net/ethernet/atheros/atl1c/atl1c_main.c167
2 files changed, 111 insertions, 122 deletions
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index 9779b830bafa..5e49ea28d33b 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -121,30 +121,50 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
121#define OTP_CTRL_CLK_EN 0x0002 121#define OTP_CTRL_CLK_EN 0x0002
122 122
123#define REG_PM_CTRL 0x12F8 123#define REG_PM_CTRL 0x12F8
124#define PM_CTRL_SDES_EN 0x00000001 124#define PM_CTRL_HOTRST BIT(31)
125#define PM_CTRL_RBER_EN 0x00000002 125#define PM_CTRL_MAC_ASPM_CHK BIT(30) /* L0s/L1 dis by MAC based on
126#define PM_CTRL_CLK_REQ_EN 0x00000004 126 * thrghput(setting in 15A0) */
127#define PM_CTRL_ASPM_L1_EN 0x00000008 127#define PM_CTRL_SA_DLY_EN BIT(29)
128#define PM_CTRL_SERDES_L1_EN 0x00000010 128#define PM_CTRL_L0S_BUFSRX_EN BIT(28)
129#define PM_CTRL_SERDES_PLL_L1_EN 0x00000020 129#define PM_CTRL_LCKDET_TIMER_MASK 0xFUL
130#define PM_CTRL_SERDES_PD_EX_L1 0x00000040
131#define PM_CTRL_SERDES_BUDS_RX_L1_EN 0x00000080
132#define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xF
133#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8
134#define PM_CTRL_ASPM_L0S_EN 0x00001000
135#define PM_CTRL_CLK_SWH_L1 0x00002000
136#define PM_CTRL_CLK_PWM_VER1_1 0x00004000
137#define PM_CTRL_RCVR_WT_TIMER 0x00008000
138#define PM_CTRL_L1_ENTRY_TIMER_MASK 0xF
139#define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16
140#define PM_CTRL_PM_REQ_TIMER_MASK 0xF
141#define PM_CTRL_PM_REQ_TIMER_SHIFT 20
142#define PM_CTRL_LCKDET_TIMER_MASK 0xF
143#define PM_CTRL_LCKDET_TIMER_SHIFT 24 130#define PM_CTRL_LCKDET_TIMER_SHIFT 24
144#define PM_CTRL_EN_BUFS_RX_L0S 0x10000000 131#define PM_CTRL_LCKDET_TIMER_DEF 0xC
145#define PM_CTRL_SA_DLY_EN 0x20000000 132#define PM_CTRL_PM_REQ_TIMER_MASK 0xFUL
146#define PM_CTRL_MAC_ASPM_CHK 0x40000000 133#define PM_CTRL_PM_REQ_TIMER_SHIFT 20 /* pm_request_l1 time > @
147#define PM_CTRL_HOTRST 0x80000000 134 * ->L0s not L1 */
135#define PM_CTRL_PM_REQ_TO_DEF 0xC
136#define PMCTRL_TXL1_AFTER_L0S BIT(19) /* l1dv2.0+ */
137#define L1D_PMCTRL_L1_ENTRY_TM_MASK 7UL /* l1dv2.0+, 3bits */
138#define L1D_PMCTRL_L1_ENTRY_TM_SHIFT 16
139#define L1D_PMCTRL_L1_ENTRY_TM_DIS 0
140#define L1D_PMCTRL_L1_ENTRY_TM_2US 1
141#define L1D_PMCTRL_L1_ENTRY_TM_4US 2
142#define L1D_PMCTRL_L1_ENTRY_TM_8US 3
143#define L1D_PMCTRL_L1_ENTRY_TM_16US 4
144#define L1D_PMCTRL_L1_ENTRY_TM_24US 5
145#define L1D_PMCTRL_L1_ENTRY_TM_32US 6
146#define L1D_PMCTRL_L1_ENTRY_TM_63US 7
147#define PM_CTRL_L1_ENTRY_TIMER_MASK 0xFUL /* l1C 4bits */
148#define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16
149#define L2CB1_PM_CTRL_L1_ENTRY_TM 7
150#define L1C_PM_CTRL_L1_ENTRY_TM 0xF
151#define PM_CTRL_RCVR_WT_TIMER BIT(15) /* 1:1us, 0:2ms */
152#define PM_CTRL_CLK_PWM_VER1_1 BIT(14) /* 0:1.0a,1:1.1 */
153#define PM_CTRL_CLK_SWH_L1 BIT(13) /* en pcie clk sw in L1 */
154#define PM_CTRL_ASPM_L0S_EN BIT(12)
155#define PM_CTRL_RXL1_AFTER_L0S BIT(11) /* l1dv2.0+ */
156#define L1D_PMCTRL_L0S_TIMER_MASK 7UL /* l1d2.0+, 3bits*/
157#define L1D_PMCTRL_L0S_TIMER_SHIFT 8
158#define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xFUL /* l1c, 4bits */
159#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8
160#define PM_CTRL_SERDES_BUFS_RX_L1_EN BIT(7)
161#define PM_CTRL_SERDES_PD_EX_L1 BIT(6) /* power down serdes rx */
162#define PM_CTRL_SERDES_PLL_L1_EN BIT(5)
163#define PM_CTRL_SERDES_L1_EN BIT(4)
164#define PM_CTRL_ASPM_L1_EN BIT(3)
165#define PM_CTRL_CLK_REQ_EN BIT(2)
166#define PM_CTRL_RBER_EN BIT(1)
167#define PM_CTRL_SPRSDWER_EN BIT(0)
148 168
149#define REG_LTSSM_ID_CTRL 0x12FC 169#define REG_LTSSM_ID_CTRL 0x12FC
150#define LTSSM_ID_EN_WRO 0x1000 170#define LTSSM_ID_EN_WRO 0x1000
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 9783afc8cb38..47fe6adf0f45 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -64,7 +64,7 @@ static int atl1c_stop_mac(struct atl1c_hw *hw);
64static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw); 64static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw);
65static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw); 65static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw);
66static void atl1c_disable_l0s_l1(struct atl1c_hw *hw); 66static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
67static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup); 67static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed);
68static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter); 68static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter);
69static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, 69static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
70 int *work_done, int work_to_do); 70 int *work_done, int work_to_do);
@@ -255,7 +255,7 @@ static void atl1c_check_link_status(struct atl1c_adapter *adapter)
255 if (atl1c_stop_mac(hw) != 0) 255 if (atl1c_stop_mac(hw) != 0)
256 if (netif_msg_hw(adapter)) 256 if (netif_msg_hw(adapter))
257 dev_warn(&pdev->dev, "stop mac failed\n"); 257 dev_warn(&pdev->dev, "stop mac failed\n");
258 atl1c_set_aspm(hw, false); 258 atl1c_set_aspm(hw, SPEED_0);
259 netif_carrier_off(netdev); 259 netif_carrier_off(netdev);
260 netif_stop_queue(netdev); 260 netif_stop_queue(netdev);
261 atl1c_phy_reset(hw); 261 atl1c_phy_reset(hw);
@@ -273,7 +273,7 @@ static void atl1c_check_link_status(struct atl1c_adapter *adapter)
273 adapter->link_duplex != duplex) { 273 adapter->link_duplex != duplex) {
274 adapter->link_speed = speed; 274 adapter->link_speed = speed;
275 adapter->link_duplex = duplex; 275 adapter->link_duplex = duplex;
276 atl1c_set_aspm(hw, true); 276 atl1c_set_aspm(hw, speed);
277 atl1c_enable_tx_ctrl(hw); 277 atl1c_enable_tx_ctrl(hw);
278 atl1c_enable_rx_ctrl(hw); 278 atl1c_enable_rx_ctrl(hw);
279 atl1c_setup_mac_ctrl(adapter); 279 atl1c_setup_mac_ctrl(adapter);
@@ -691,12 +691,8 @@ static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
691 691
692 hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE | 692 hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
693 ATL1C_TXQ_MODE_ENHANCE; 693 ATL1C_TXQ_MODE_ENHANCE;
694 if (link_ctrl_data & LINK_CTRL_L0S_EN) 694 hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT |
695 hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT; 695 ATL1C_ASPM_L1_SUPPORT;
696 if (link_ctrl_data & LINK_CTRL_L1_EN)
697 hw->ctrl_flags |= ATL1C_ASPM_L1_SUPPORT;
698 if (link_ctrl_data & LINK_CTRL_EXT_SYNC)
699 hw->ctrl_flags |= ATL1C_LINK_EXT_SYNC;
700 hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON; 696 hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
701 697
702 if (hw->nic_type == athr_l1c || 698 if (hw->nic_type == athr_l1c ||
@@ -1203,112 +1199,83 @@ static int atl1c_reset_mac(struct atl1c_hw *hw)
1203 1199
1204static void atl1c_disable_l0s_l1(struct atl1c_hw *hw) 1200static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
1205{ 1201{
1206 u32 pm_ctrl_data; 1202 u16 ctrl_flags = hw->ctrl_flags;
1207 1203
1208 AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data); 1204 hw->ctrl_flags &= ~(ATL1C_ASPM_L0S_SUPPORT | ATL1C_ASPM_L1_SUPPORT);
1209 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK << 1205 atl1c_set_aspm(hw, SPEED_0);
1210 PM_CTRL_L1_ENTRY_TIMER_SHIFT); 1206 hw->ctrl_flags = ctrl_flags;
1211 pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
1212 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1213 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1214 pm_ctrl_data &= ~PM_CTRL_MAC_ASPM_CHK;
1215 pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
1216
1217 pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
1218 pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
1219 pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
1220 AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
1221} 1207}
1222 1208
1223/* 1209/*
1224 * Set ASPM state. 1210 * Set ASPM state.
1225 * Enable/disable L0s/L1 depend on link state. 1211 * Enable/disable L0s/L1 depend on link state.
1226 */ 1212 */
1227static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup) 1213static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
1228{ 1214{
1229 u32 pm_ctrl_data; 1215 u32 pm_ctrl_data;
1230 u32 link_ctrl_data; 1216 u32 link_l1_timer;
1231 u32 link_l1_timer = 0xF;
1232 1217
1233 AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data); 1218 AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
1234 AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data); 1219 pm_ctrl_data &= ~(PM_CTRL_ASPM_L1_EN |
1220 PM_CTRL_ASPM_L0S_EN |
1221 PM_CTRL_MAC_ASPM_CHK);
1222 /* L1 timer */
1223 if (hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
1224 pm_ctrl_data &= ~PMCTRL_TXL1_AFTER_L0S;
1225 link_l1_timer =
1226 link_speed == SPEED_1000 || link_speed == SPEED_100 ?
1227 L1D_PMCTRL_L1_ENTRY_TM_16US : 1;
1228 pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
1229 L1D_PMCTRL_L1_ENTRY_TM, link_l1_timer);
1230 } else {
1231 link_l1_timer = hw->nic_type == athr_l2c_b ?
1232 L2CB1_PM_CTRL_L1_ENTRY_TM : L1C_PM_CTRL_L1_ENTRY_TM;
1233 if (link_speed != SPEED_1000 && link_speed != SPEED_100)
1234 link_l1_timer = 1;
1235 pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
1236 PM_CTRL_L1_ENTRY_TIMER, link_l1_timer);
1237 }
1235 1238
1236 pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1; 1239 /* L0S/L1 enable */
1237 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK << 1240 if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT)
1238 PM_CTRL_L1_ENTRY_TIMER_SHIFT); 1241 pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN | PM_CTRL_MAC_ASPM_CHK;
1239 pm_ctrl_data &= ~(PM_CTRL_LCKDET_TIMER_MASK << 1242 if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
1240 PM_CTRL_LCKDET_TIMER_SHIFT); 1243 pm_ctrl_data |= PM_CTRL_ASPM_L1_EN | PM_CTRL_MAC_ASPM_CHK;
1241 pm_ctrl_data |= AT_LCKDET_TIMER << PM_CTRL_LCKDET_TIMER_SHIFT;
1242 1244
1245 /* l2cb & l1d & l2cb2 & l1d2 */
1243 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d || 1246 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
1244 hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) { 1247 hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
1245 link_ctrl_data &= ~LINK_CTRL_EXT_SYNC; 1248 pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
1246 if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE)) { 1249 PM_CTRL_PM_REQ_TIMER, PM_CTRL_PM_REQ_TO_DEF);
1247 if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) 1250 pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER |
1248 link_ctrl_data |= LINK_CTRL_EXT_SYNC; 1251 PM_CTRL_SERDES_PD_EX_L1 |
1249 } 1252 PM_CTRL_CLK_SWH_L1;
1250 1253 pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
1251 AT_WRITE_REG(hw, REG_LINK_CTRL, link_ctrl_data); 1254 PM_CTRL_SERDES_PLL_L1_EN |
1252 1255 PM_CTRL_SERDES_BUFS_RX_L1_EN |
1253 pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER; 1256 PM_CTRL_SA_DLY_EN |
1254 pm_ctrl_data &= ~(PM_CTRL_PM_REQ_TIMER_MASK << 1257 PM_CTRL_HOTRST);
1255 PM_CTRL_PM_REQ_TIMER_SHIFT); 1258 /* disable l0s if link down or l2cb */
1256 pm_ctrl_data |= AT_ASPM_L1_TIMER << 1259 if (link_speed == SPEED_0 || hw->nic_type == athr_l2c_b)
1257 PM_CTRL_PM_REQ_TIMER_SHIFT;
1258 pm_ctrl_data &= ~PM_CTRL_SA_DLY_EN;
1259 pm_ctrl_data &= ~PM_CTRL_HOTRST;
1260 pm_ctrl_data |= 1 << PM_CTRL_L1_ENTRY_TIMER_SHIFT;
1261 pm_ctrl_data |= PM_CTRL_SERDES_PD_EX_L1;
1262 }
1263 pm_ctrl_data |= PM_CTRL_MAC_ASPM_CHK;
1264 if (linkup) {
1265 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1266 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1267 if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
1268 pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
1269 if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT)
1270 pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN;
1271
1272 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
1273 hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
1274 if (hw->nic_type == athr_l2c_b)
1275 if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE))
1276 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1277 pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
1278 pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
1279 pm_ctrl_data &= ~PM_CTRL_SERDES_BUDS_RX_L1_EN;
1280 pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
1281 if (hw->adapter->link_speed == SPEED_100 ||
1282 hw->adapter->link_speed == SPEED_1000) {
1283 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
1284 PM_CTRL_L1_ENTRY_TIMER_SHIFT);
1285 if (hw->nic_type == athr_l2c_b)
1286 link_l1_timer = 7;
1287 else if (hw->nic_type == athr_l2c_b2 ||
1288 hw->nic_type == athr_l1d_2)
1289 link_l1_timer = 4;
1290 pm_ctrl_data |= link_l1_timer <<
1291 PM_CTRL_L1_ENTRY_TIMER_SHIFT;
1292 }
1293 } else {
1294 pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
1295 pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
1296 pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
1297 pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
1298 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN; 1260 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1299 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN; 1261 } else { /* l1c */
1300 1262 pm_ctrl_data =
1263 FIELD_SETX(pm_ctrl_data, PM_CTRL_L1_ENTRY_TIMER, 0);
1264 if (link_speed != SPEED_0) {
1265 pm_ctrl_data |= PM_CTRL_SERDES_L1_EN |
1266 PM_CTRL_SERDES_PLL_L1_EN |
1267 PM_CTRL_SERDES_BUFS_RX_L1_EN;
1268 pm_ctrl_data &= ~(PM_CTRL_SERDES_PD_EX_L1 |
1269 PM_CTRL_CLK_SWH_L1 |
1270 PM_CTRL_ASPM_L0S_EN |
1271 PM_CTRL_ASPM_L1_EN);
1272 } else { /* link down */
1273 pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
1274 pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
1275 PM_CTRL_SERDES_PLL_L1_EN |
1276 PM_CTRL_SERDES_BUFS_RX_L1_EN |
1277 PM_CTRL_ASPM_L0S_EN);
1301 } 1278 }
1302 } else {
1303 pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
1304 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1305 pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
1306 pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
1307
1308 if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
1309 pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
1310 else
1311 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1312 } 1279 }
1313 AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data); 1280 AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
1314 1281
@@ -2235,6 +2202,8 @@ static void atl1c_down(struct atl1c_adapter *adapter)
2235 napi_disable(&adapter->napi); 2202 napi_disable(&adapter->napi);
2236 atl1c_irq_disable(adapter); 2203 atl1c_irq_disable(adapter);
2237 atl1c_free_irq(adapter); 2204 atl1c_free_irq(adapter);
2205 /* disable ASPM if device inactive */
2206 atl1c_disable_l0s_l1(&adapter->hw);
2238 /* reset MAC to disable all RX/TX */ 2207 /* reset MAC to disable all RX/TX */
2239 atl1c_reset_mac(&adapter->hw); 2208 atl1c_reset_mac(&adapter->hw);
2240 msleep(1); 2209 msleep(1);