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authorLendacky, Thomas <Thomas.Lendacky@amd.com>2015-02-05 20:17:14 -0500
committerDavid S. Miller <davem@davemloft.net>2015-02-08 01:44:42 -0500
commitfd972b736bfec7e0297dac9501211abb91b436fd (patch)
tree4ae758cee05d2598d0940d11660d2ba1dbc2aeac /drivers/net/ethernet/amd
parent91e83133e70ebe1572746d1ad858b4eb28ab9b53 (diff)
amd-xgbe: Check per channel DMA interrupt use in main ISR
When using per channel DMA interrupts the transmit interrupt (TI) and the receive interrupt (RI) are masked off so as to not generate an interrupt to the main ISR. However, should another interrupt fire for the DMA channel that is handled by the main ISR the TI/RI bits can still be set. This will cause the wrong and uninitialized napi structure to be used causing a panic. Add a check to be sure per channel DMA interrupts are not enabled before acting on those bit flags. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/amd')
-rw-r--r--drivers/net/ethernet/amd/xgbe/xgbe-drv.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
index e5ffb2ccb67d..477a7e35d21a 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
@@ -337,12 +337,13 @@ static irqreturn_t xgbe_isr(int irq, void *data)
337 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); 337 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
338 DBGPR(" DMA_CH%u_ISR = %08x\n", i, dma_ch_isr); 338 DBGPR(" DMA_CH%u_ISR = %08x\n", i, dma_ch_isr);
339 339
340 /* If we get a TI or RI interrupt that means per channel DMA 340 /* The TI or RI interrupt bits may still be set even if using
341 * interrupts are not enabled, so we use the private data napi 341 * per channel DMA interrupts. Check to be sure those are not
342 * structure, not the per channel napi structure 342 * enabled before using the private data napi structure.
343 */ 343 */
344 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || 344 if (!pdata->per_channel_irq &&
345 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI)) { 345 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
346 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
346 if (napi_schedule_prep(&pdata->napi)) { 347 if (napi_schedule_prep(&pdata->napi)) {
347 /* Disable Tx and Rx interrupts */ 348 /* Disable Tx and Rx interrupts */
348 xgbe_disable_rx_tx_ints(pdata); 349 xgbe_disable_rx_tx_ints(pdata);