diff options
author | Bruce Allan <bruce.w.allan@intel.com> | 2010-01-07 11:32:13 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-01-08 03:35:31 -0500 |
commit | b7a9216c5a3205a6d721972bfd012c4eb5950e9c (patch) | |
tree | 9a33ba2afe538d12c97bd87649a2026230dba756 /drivers/net/e1000e | |
parent | ca777f9c098f1ea1c9ec61318cc909d0c8f465e1 (diff) |
e1000e: fix and commonize code for setting the receive address registers
Fix e1000e_rar_set() to flush consecutive register writes to avoid write
combining which some parts cannot handle. Update e1000e_init_rx_addrs()
to call the fixed e1000e_rar_set() instead of duplicating code.
Also change e1000e_rar_set() to _not_ set the Address Valid bit if the MAC
address is all zeros.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/e1000e')
-rw-r--r-- | drivers/net/e1000e/lib.c | 24 |
1 files changed, 15 insertions, 9 deletions
diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c index 97649bf53b05..2fa9b36a2c5a 100644 --- a/drivers/net/e1000e/lib.c +++ b/drivers/net/e1000e/lib.c | |||
@@ -125,6 +125,7 @@ void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) | |||
125 | void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) | 125 | void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) |
126 | { | 126 | { |
127 | u32 i; | 127 | u32 i; |
128 | u8 mac_addr[ETH_ALEN] = {0}; | ||
128 | 129 | ||
129 | /* Setup the receive address */ | 130 | /* Setup the receive address */ |
130 | e_dbg("Programming MAC Address into RAR[0]\n"); | 131 | e_dbg("Programming MAC Address into RAR[0]\n"); |
@@ -133,12 +134,8 @@ void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) | |||
133 | 134 | ||
134 | /* Zero out the other (rar_entry_count - 1) receive addresses */ | 135 | /* Zero out the other (rar_entry_count - 1) receive addresses */ |
135 | e_dbg("Clearing RAR[1-%u]\n", rar_count-1); | 136 | e_dbg("Clearing RAR[1-%u]\n", rar_count-1); |
136 | for (i = 1; i < rar_count; i++) { | 137 | for (i = 1; i < rar_count; i++) |
137 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); | 138 | e1000e_rar_set(hw, mac_addr, i); |
138 | e1e_flush(); | ||
139 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); | ||
140 | e1e_flush(); | ||
141 | } | ||
142 | } | 139 | } |
143 | 140 | ||
144 | /** | 141 | /** |
@@ -164,10 +161,19 @@ void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) | |||
164 | 161 | ||
165 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); | 162 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); |
166 | 163 | ||
167 | rar_high |= E1000_RAH_AV; | 164 | /* If MAC address zero, no need to set the AV bit */ |
165 | if (rar_low || rar_high) | ||
166 | rar_high |= E1000_RAH_AV; | ||
168 | 167 | ||
169 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); | 168 | /* |
170 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); | 169 | * Some bridges will combine consecutive 32-bit writes into |
170 | * a single burst write, which will malfunction on some parts. | ||
171 | * The flushes avoid this. | ||
172 | */ | ||
173 | ew32(RAL(index), rar_low); | ||
174 | e1e_flush(); | ||
175 | ew32(RAH(index), rar_high); | ||
176 | e1e_flush(); | ||
171 | } | 177 | } |
172 | 178 | ||
173 | /** | 179 | /** |