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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /drivers/net/e1000e/phy.c
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/net/e1000e/phy.c')
-rw-r--r--drivers/net/e1000e/phy.c585
1 files changed, 364 insertions, 221 deletions
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index 85f955f70417..7f3ceb9dad6a 100644
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/1000 Linux driver 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation. 4 Copyright(c) 1999 - 2009 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -44,6 +44,8 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
44/* Cable length tables */ 44/* Cable length tables */
45static const u16 e1000_m88_cable_length_table[] = 45static const u16 e1000_m88_cable_length_table[] =
46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 ARRAY_SIZE(e1000_m88_cable_length_table)
47 49
48static const u16 e1000_igp_2_cable_length_table[] = 50static const u16 e1000_igp_2_cable_length_table[] =
49 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 51 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
@@ -130,7 +132,7 @@ s32 e1000e_get_phy_id(struct e1000_hw *hw)
130 u16 phy_id; 132 u16 phy_id;
131 u16 retry_count = 0; 133 u16 retry_count = 0;
132 134
133 if (!(phy->ops.read_phy_reg)) 135 if (!(phy->ops.read_reg))
134 goto out; 136 goto out;
135 137
136 while (retry_count < 2) { 138 while (retry_count < 2) {
@@ -150,32 +152,9 @@ s32 e1000e_get_phy_id(struct e1000_hw *hw)
150 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 152 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
151 goto out; 153 goto out;
152 154
153 /*
154 * If the PHY ID is still unknown, we may have an 82577i
155 * without link. We will try again after setting Slow
156 * MDIC mode. No harm in trying again in this case since
157 * the PHY ID is unknown at this point anyway
158 */
159 ret_val = phy->ops.acquire_phy(hw);
160 if (ret_val)
161 goto out;
162 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
163 if (ret_val)
164 goto out;
165 phy->ops.release_phy(hw);
166
167 retry_count++; 155 retry_count++;
168 } 156 }
169out: 157out:
170 /* Revert to MDIO fast mode, if applicable */
171 if (retry_count) {
172 ret_val = phy->ops.acquire_phy(hw);
173 if (ret_val)
174 return ret_val;
175 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
176 phy->ops.release_phy(hw);
177 }
178
179 return ret_val; 158 return ret_val;
180} 159}
181 160
@@ -211,7 +190,7 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
211 u32 i, mdic = 0; 190 u32 i, mdic = 0;
212 191
213 if (offset > MAX_PHY_REG_ADDRESS) { 192 if (offset > MAX_PHY_REG_ADDRESS) {
214 hw_dbg(hw, "PHY Address %d is out of range\n", offset); 193 e_dbg("PHY Address %d is out of range\n", offset);
215 return -E1000_ERR_PARAM; 194 return -E1000_ERR_PARAM;
216 } 195 }
217 196
@@ -238,11 +217,11 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
238 break; 217 break;
239 } 218 }
240 if (!(mdic & E1000_MDIC_READY)) { 219 if (!(mdic & E1000_MDIC_READY)) {
241 hw_dbg(hw, "MDI Read did not complete\n"); 220 e_dbg("MDI Read did not complete\n");
242 return -E1000_ERR_PHY; 221 return -E1000_ERR_PHY;
243 } 222 }
244 if (mdic & E1000_MDIC_ERROR) { 223 if (mdic & E1000_MDIC_ERROR) {
245 hw_dbg(hw, "MDI Error\n"); 224 e_dbg("MDI Error\n");
246 return -E1000_ERR_PHY; 225 return -E1000_ERR_PHY;
247 } 226 }
248 *data = (u16) mdic; 227 *data = (u16) mdic;
@@ -264,7 +243,7 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
264 u32 i, mdic = 0; 243 u32 i, mdic = 0;
265 244
266 if (offset > MAX_PHY_REG_ADDRESS) { 245 if (offset > MAX_PHY_REG_ADDRESS) {
267 hw_dbg(hw, "PHY Address %d is out of range\n", offset); 246 e_dbg("PHY Address %d is out of range\n", offset);
268 return -E1000_ERR_PARAM; 247 return -E1000_ERR_PARAM;
269 } 248 }
270 249
@@ -292,11 +271,11 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
292 break; 271 break;
293 } 272 }
294 if (!(mdic & E1000_MDIC_READY)) { 273 if (!(mdic & E1000_MDIC_READY)) {
295 hw_dbg(hw, "MDI Write did not complete\n"); 274 e_dbg("MDI Write did not complete\n");
296 return -E1000_ERR_PHY; 275 return -E1000_ERR_PHY;
297 } 276 }
298 if (mdic & E1000_MDIC_ERROR) { 277 if (mdic & E1000_MDIC_ERROR) {
299 hw_dbg(hw, "MDI Error\n"); 278 e_dbg("MDI Error\n");
300 return -E1000_ERR_PHY; 279 return -E1000_ERR_PHY;
301 } 280 }
302 281
@@ -317,14 +296,14 @@ s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
317{ 296{
318 s32 ret_val; 297 s32 ret_val;
319 298
320 ret_val = hw->phy.ops.acquire_phy(hw); 299 ret_val = hw->phy.ops.acquire(hw);
321 if (ret_val) 300 if (ret_val)
322 return ret_val; 301 return ret_val;
323 302
324 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 303 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
325 data); 304 data);
326 305
327 hw->phy.ops.release_phy(hw); 306 hw->phy.ops.release(hw);
328 307
329 return ret_val; 308 return ret_val;
330} 309}
@@ -342,14 +321,14 @@ s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
342{ 321{
343 s32 ret_val; 322 s32 ret_val;
344 323
345 ret_val = hw->phy.ops.acquire_phy(hw); 324 ret_val = hw->phy.ops.acquire(hw);
346 if (ret_val) 325 if (ret_val)
347 return ret_val; 326 return ret_val;
348 327
349 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 328 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
350 data); 329 data);
351 330
352 hw->phy.ops.release_phy(hw); 331 hw->phy.ops.release(hw);
353 332
354 return ret_val; 333 return ret_val;
355} 334}
@@ -371,10 +350,10 @@ static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
371 s32 ret_val = 0; 350 s32 ret_val = 0;
372 351
373 if (!locked) { 352 if (!locked) {
374 if (!(hw->phy.ops.acquire_phy)) 353 if (!(hw->phy.ops.acquire))
375 goto out; 354 goto out;
376 355
377 ret_val = hw->phy.ops.acquire_phy(hw); 356 ret_val = hw->phy.ops.acquire(hw);
378 if (ret_val) 357 if (ret_val)
379 goto out; 358 goto out;
380 } 359 }
@@ -392,7 +371,7 @@ static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
392 371
393release: 372release:
394 if (!locked) 373 if (!locked)
395 hw->phy.ops.release_phy(hw); 374 hw->phy.ops.release(hw);
396out: 375out:
397 return ret_val; 376 return ret_val;
398} 377}
@@ -442,10 +421,10 @@ static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
442 s32 ret_val = 0; 421 s32 ret_val = 0;
443 422
444 if (!locked) { 423 if (!locked) {
445 if (!(hw->phy.ops.acquire_phy)) 424 if (!(hw->phy.ops.acquire))
446 goto out; 425 goto out;
447 426
448 ret_val = hw->phy.ops.acquire_phy(hw); 427 ret_val = hw->phy.ops.acquire(hw);
449 if (ret_val) 428 if (ret_val)
450 goto out; 429 goto out;
451 } 430 }
@@ -463,7 +442,7 @@ static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
463 442
464release: 443release:
465 if (!locked) 444 if (!locked)
466 hw->phy.ops.release_phy(hw); 445 hw->phy.ops.release(hw);
467 446
468out: 447out:
469 return ret_val; 448 return ret_val;
@@ -515,10 +494,10 @@ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
515 s32 ret_val = 0; 494 s32 ret_val = 0;
516 495
517 if (!locked) { 496 if (!locked) {
518 if (!(hw->phy.ops.acquire_phy)) 497 if (!(hw->phy.ops.acquire))
519 goto out; 498 goto out;
520 499
521 ret_val = hw->phy.ops.acquire_phy(hw); 500 ret_val = hw->phy.ops.acquire(hw);
522 if (ret_val) 501 if (ret_val)
523 goto out; 502 goto out;
524 } 503 }
@@ -533,7 +512,7 @@ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
533 *data = (u16)kmrnctrlsta; 512 *data = (u16)kmrnctrlsta;
534 513
535 if (!locked) 514 if (!locked)
536 hw->phy.ops.release_phy(hw); 515 hw->phy.ops.release(hw);
537 516
538out: 517out:
539 return ret_val; 518 return ret_val;
@@ -587,10 +566,10 @@ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
587 s32 ret_val = 0; 566 s32 ret_val = 0;
588 567
589 if (!locked) { 568 if (!locked) {
590 if (!(hw->phy.ops.acquire_phy)) 569 if (!(hw->phy.ops.acquire))
591 goto out; 570 goto out;
592 571
593 ret_val = hw->phy.ops.acquire_phy(hw); 572 ret_val = hw->phy.ops.acquire(hw);
594 if (ret_val) 573 if (ret_val)
595 goto out; 574 goto out;
596 } 575 }
@@ -602,7 +581,7 @@ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
602 udelay(2); 581 udelay(2);
603 582
604 if (!locked) 583 if (!locked)
605 hw->phy.ops.release_phy(hw); 584 hw->phy.ops.release(hw);
606 585
607out: 586out:
608 return ret_val; 587 return ret_val;
@@ -649,7 +628,7 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
649 u16 phy_data; 628 u16 phy_data;
650 629
651 /* Enable CRS on TX. This must be set for half-duplex operation. */ 630 /* Enable CRS on TX. This must be set for half-duplex operation. */
652 ret_val = phy->ops.read_phy_reg(hw, I82577_CFG_REG, &phy_data); 631 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data);
653 if (ret_val) 632 if (ret_val)
654 goto out; 633 goto out;
655 634
@@ -658,7 +637,7 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
658 /* Enable downshift */ 637 /* Enable downshift */
659 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 638 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
660 639
661 ret_val = phy->ops.write_phy_reg(hw, I82577_CFG_REG, phy_data); 640 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data);
662 641
663out: 642out:
664 return ret_val; 643 return ret_val;
@@ -776,12 +755,12 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
776 /* Commit the changes. */ 755 /* Commit the changes. */
777 ret_val = e1000e_commit_phy(hw); 756 ret_val = e1000e_commit_phy(hw);
778 if (ret_val) { 757 if (ret_val) {
779 hw_dbg(hw, "Error committing the PHY changes\n"); 758 e_dbg("Error committing the PHY changes\n");
780 return ret_val; 759 return ret_val;
781 } 760 }
782 761
783 if (phy->type == e1000_phy_82578) { 762 if (phy->type == e1000_phy_82578) {
784 ret_val = phy->ops.read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 763 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
785 &phy_data); 764 &phy_data);
786 if (ret_val) 765 if (ret_val)
787 return ret_val; 766 return ret_val;
@@ -789,7 +768,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
789 /* 82578 PHY - set the downshift count to 1x. */ 768 /* 82578 PHY - set the downshift count to 1x. */
790 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 769 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
791 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 770 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
792 ret_val = phy->ops.write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 771 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
793 phy_data); 772 phy_data);
794 if (ret_val) 773 if (ret_val)
795 return ret_val; 774 return ret_val;
@@ -813,7 +792,7 @@ s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
813 792
814 ret_val = e1000_phy_hw_reset(hw); 793 ret_val = e1000_phy_hw_reset(hw);
815 if (ret_val) { 794 if (ret_val) {
816 hw_dbg(hw, "Error resetting the PHY.\n"); 795 e_dbg("Error resetting the PHY.\n");
817 return ret_val; 796 return ret_val;
818 } 797 }
819 798
@@ -824,9 +803,9 @@ s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
824 msleep(100); 803 msleep(100);
825 804
826 /* disable lplu d0 during driver init */ 805 /* disable lplu d0 during driver init */
827 ret_val = e1000_set_d0_lplu_state(hw, 0); 806 ret_val = e1000_set_d0_lplu_state(hw, false);
828 if (ret_val) { 807 if (ret_val) {
829 hw_dbg(hw, "Error Disabling LPLU D0\n"); 808 e_dbg("Error Disabling LPLU D0\n");
830 return ret_val; 809 return ret_val;
831 } 810 }
832 /* Configure mdi-mdix settings */ 811 /* Configure mdi-mdix settings */
@@ -962,39 +941,39 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
962 NWAY_AR_10T_HD_CAPS); 941 NWAY_AR_10T_HD_CAPS);
963 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 942 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
964 943
965 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised); 944 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
966 945
967 /* Do we want to advertise 10 Mb Half Duplex? */ 946 /* Do we want to advertise 10 Mb Half Duplex? */
968 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 947 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
969 hw_dbg(hw, "Advertise 10mb Half duplex\n"); 948 e_dbg("Advertise 10mb Half duplex\n");
970 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 949 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
971 } 950 }
972 951
973 /* Do we want to advertise 10 Mb Full Duplex? */ 952 /* Do we want to advertise 10 Mb Full Duplex? */
974 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 953 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
975 hw_dbg(hw, "Advertise 10mb Full duplex\n"); 954 e_dbg("Advertise 10mb Full duplex\n");
976 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 955 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
977 } 956 }
978 957
979 /* Do we want to advertise 100 Mb Half Duplex? */ 958 /* Do we want to advertise 100 Mb Half Duplex? */
980 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 959 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
981 hw_dbg(hw, "Advertise 100mb Half duplex\n"); 960 e_dbg("Advertise 100mb Half duplex\n");
982 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 961 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
983 } 962 }
984 963
985 /* Do we want to advertise 100 Mb Full Duplex? */ 964 /* Do we want to advertise 100 Mb Full Duplex? */
986 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 965 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
987 hw_dbg(hw, "Advertise 100mb Full duplex\n"); 966 e_dbg("Advertise 100mb Full duplex\n");
988 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 967 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
989 } 968 }
990 969
991 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 970 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
992 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 971 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
993 hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n"); 972 e_dbg("Advertise 1000mb Half duplex request denied!\n");
994 973
995 /* Do we want to advertise 1000 Mb Full Duplex? */ 974 /* Do we want to advertise 1000 Mb Full Duplex? */
996 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 975 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
997 hw_dbg(hw, "Advertise 1000mb Full duplex\n"); 976 e_dbg("Advertise 1000mb Full duplex\n");
998 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 977 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
999 } 978 }
1000 979
@@ -1053,7 +1032,7 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1053 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1032 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1054 break; 1033 break;
1055 default: 1034 default:
1056 hw_dbg(hw, "Flow control param set incorrectly\n"); 1035 e_dbg("Flow control param set incorrectly\n");
1057 ret_val = -E1000_ERR_CONFIG; 1036 ret_val = -E1000_ERR_CONFIG;
1058 return ret_val; 1037 return ret_val;
1059 } 1038 }
@@ -1062,7 +1041,7 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1062 if (ret_val) 1041 if (ret_val)
1063 return ret_val; 1042 return ret_val;
1064 1043
1065 hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1044 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1066 1045
1067 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1046 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1068 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1047 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
@@ -1099,13 +1078,13 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1099 if (phy->autoneg_advertised == 0) 1078 if (phy->autoneg_advertised == 0)
1100 phy->autoneg_advertised = phy->autoneg_mask; 1079 phy->autoneg_advertised = phy->autoneg_mask;
1101 1080
1102 hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n"); 1081 e_dbg("Reconfiguring auto-neg advertisement params\n");
1103 ret_val = e1000_phy_setup_autoneg(hw); 1082 ret_val = e1000_phy_setup_autoneg(hw);
1104 if (ret_val) { 1083 if (ret_val) {
1105 hw_dbg(hw, "Error Setting up Auto-Negotiation\n"); 1084 e_dbg("Error Setting up Auto-Negotiation\n");
1106 return ret_val; 1085 return ret_val;
1107 } 1086 }
1108 hw_dbg(hw, "Restarting Auto-Neg\n"); 1087 e_dbg("Restarting Auto-Neg\n");
1109 1088
1110 /* 1089 /*
1111 * Restart auto-negotiation by setting the Auto Neg Enable bit and 1090 * Restart auto-negotiation by setting the Auto Neg Enable bit and
@@ -1127,7 +1106,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1127 if (phy->autoneg_wait_to_complete) { 1106 if (phy->autoneg_wait_to_complete) {
1128 ret_val = e1000_wait_autoneg(hw); 1107 ret_val = e1000_wait_autoneg(hw);
1129 if (ret_val) { 1108 if (ret_val) {
1130 hw_dbg(hw, "Error while waiting for " 1109 e_dbg("Error while waiting for "
1131 "autoneg to complete\n"); 1110 "autoneg to complete\n");
1132 return ret_val; 1111 return ret_val;
1133 } 1112 }
@@ -1165,10 +1144,10 @@ s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1165 * PHY will be set to 10H, 10F, 100H or 100F 1144 * PHY will be set to 10H, 10F, 100H or 100F
1166 * depending on user settings. 1145 * depending on user settings.
1167 */ 1146 */
1168 hw_dbg(hw, "Forcing Speed and Duplex\n"); 1147 e_dbg("Forcing Speed and Duplex\n");
1169 ret_val = e1000_phy_force_speed_duplex(hw); 1148 ret_val = e1000_phy_force_speed_duplex(hw);
1170 if (ret_val) { 1149 if (ret_val) {
1171 hw_dbg(hw, "Error Forcing Speed and Duplex\n"); 1150 e_dbg("Error Forcing Speed and Duplex\n");
1172 return ret_val; 1151 return ret_val;
1173 } 1152 }
1174 } 1153 }
@@ -1185,11 +1164,11 @@ s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1185 return ret_val; 1164 return ret_val;
1186 1165
1187 if (link) { 1166 if (link) {
1188 hw_dbg(hw, "Valid link established!!!\n"); 1167 e_dbg("Valid link established!!!\n");
1189 e1000e_config_collision_dist(hw); 1168 e1000e_config_collision_dist(hw);
1190 ret_val = e1000e_config_fc_after_link_up(hw); 1169 ret_val = e1000e_config_fc_after_link_up(hw);
1191 } else { 1170 } else {
1192 hw_dbg(hw, "Unable to establish link!!!\n"); 1171 e_dbg("Unable to establish link!!!\n");
1193 } 1172 }
1194 1173
1195 return ret_val; 1174 return ret_val;
@@ -1235,12 +1214,12 @@ s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1235 if (ret_val) 1214 if (ret_val)
1236 return ret_val; 1215 return ret_val;
1237 1216
1238 hw_dbg(hw, "IGP PSCR: %X\n", phy_data); 1217 e_dbg("IGP PSCR: %X\n", phy_data);
1239 1218
1240 udelay(1); 1219 udelay(1);
1241 1220
1242 if (phy->autoneg_wait_to_complete) { 1221 if (phy->autoneg_wait_to_complete) {
1243 hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n"); 1222 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1244 1223
1245 ret_val = e1000e_phy_has_link_generic(hw, 1224 ret_val = e1000e_phy_has_link_generic(hw,
1246 PHY_FORCE_LIMIT, 1225 PHY_FORCE_LIMIT,
@@ -1250,7 +1229,7 @@ s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1250 return ret_val; 1229 return ret_val;
1251 1230
1252 if (!link) 1231 if (!link)
1253 hw_dbg(hw, "Link taking longer than expected.\n"); 1232 e_dbg("Link taking longer than expected.\n");
1254 1233
1255 /* Try once more */ 1234 /* Try once more */
1256 ret_val = e1000e_phy_has_link_generic(hw, 1235 ret_val = e1000e_phy_has_link_generic(hw,
@@ -1294,7 +1273,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1294 if (ret_val) 1273 if (ret_val)
1295 return ret_val; 1274 return ret_val;
1296 1275
1297 hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data); 1276 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1298 1277
1299 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); 1278 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1300 if (ret_val) 1279 if (ret_val)
@@ -1312,7 +1291,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1312 return ret_val; 1291 return ret_val;
1313 1292
1314 if (phy->autoneg_wait_to_complete) { 1293 if (phy->autoneg_wait_to_complete) {
1315 hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n"); 1294 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1316 1295
1317 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1296 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1318 100000, &link); 1297 100000, &link);
@@ -1320,17 +1299,22 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1320 return ret_val; 1299 return ret_val;
1321 1300
1322 if (!link) { 1301 if (!link) {
1323 /* 1302 if (hw->phy.type != e1000_phy_m88) {
1324 * We didn't get link. 1303 e_dbg("Link taking longer than expected.\n");
1325 * Reset the DSP and cross our fingers. 1304 } else {
1326 */ 1305 /*
1327 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 1306 * We didn't get link.
1328 0x001d); 1307 * Reset the DSP and cross our fingers.
1329 if (ret_val) 1308 */
1330 return ret_val; 1309 ret_val = e1e_wphy(hw,
1331 ret_val = e1000e_phy_reset_dsp(hw); 1310 M88E1000_PHY_PAGE_SELECT,
1332 if (ret_val) 1311 0x001d);
1333 return ret_val; 1312 if (ret_val)
1313 return ret_val;
1314 ret_val = e1000e_phy_reset_dsp(hw);
1315 if (ret_val)
1316 return ret_val;
1317 }
1334 } 1318 }
1335 1319
1336 /* Try once more */ 1320 /* Try once more */
@@ -1340,6 +1324,9 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1340 return ret_val; 1324 return ret_val;
1341 } 1325 }
1342 1326
1327 if (hw->phy.type != e1000_phy_m88)
1328 return 0;
1329
1343 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1330 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1344 if (ret_val) 1331 if (ret_val)
1345 return ret_val; 1332 return ret_val;
@@ -1369,6 +1356,73 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1369} 1356}
1370 1357
1371/** 1358/**
1359 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1360 * @hw: pointer to the HW structure
1361 *
1362 * Forces the speed and duplex settings of the PHY.
1363 * This is a function pointer entry point only called by
1364 * PHY setup routines.
1365 **/
1366s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1367{
1368 struct e1000_phy_info *phy = &hw->phy;
1369 s32 ret_val;
1370 u16 data;
1371 bool link;
1372
1373 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
1374 if (ret_val)
1375 goto out;
1376
1377 e1000e_phy_force_speed_duplex_setup(hw, &data);
1378
1379 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
1380 if (ret_val)
1381 goto out;
1382
1383 /* Disable MDI-X support for 10/100 */
1384 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1385 if (ret_val)
1386 goto out;
1387
1388 data &= ~IFE_PMC_AUTO_MDIX;
1389 data &= ~IFE_PMC_FORCE_MDIX;
1390
1391 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1392 if (ret_val)
1393 goto out;
1394
1395 e_dbg("IFE PMC: %X\n", data);
1396
1397 udelay(1);
1398
1399 if (phy->autoneg_wait_to_complete) {
1400 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1401
1402 ret_val = e1000e_phy_has_link_generic(hw,
1403 PHY_FORCE_LIMIT,
1404 100000,
1405 &link);
1406 if (ret_val)
1407 goto out;
1408
1409 if (!link)
1410 e_dbg("Link taking longer than expected.\n");
1411
1412 /* Try once more */
1413 ret_val = e1000e_phy_has_link_generic(hw,
1414 PHY_FORCE_LIMIT,
1415 100000,
1416 &link);
1417 if (ret_val)
1418 goto out;
1419 }
1420
1421out:
1422 return ret_val;
1423}
1424
1425/**
1372 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1426 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1373 * @hw: pointer to the HW structure 1427 * @hw: pointer to the HW structure
1374 * @phy_ctrl: pointer to current value of PHY_CONTROL 1428 * @phy_ctrl: pointer to current value of PHY_CONTROL
@@ -1403,11 +1457,11 @@ void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1403 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1457 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1404 ctrl &= ~E1000_CTRL_FD; 1458 ctrl &= ~E1000_CTRL_FD;
1405 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1459 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1406 hw_dbg(hw, "Half Duplex\n"); 1460 e_dbg("Half Duplex\n");
1407 } else { 1461 } else {
1408 ctrl |= E1000_CTRL_FD; 1462 ctrl |= E1000_CTRL_FD;
1409 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1463 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1410 hw_dbg(hw, "Full Duplex\n"); 1464 e_dbg("Full Duplex\n");
1411 } 1465 }
1412 1466
1413 /* Forcing 10mb or 100mb? */ 1467 /* Forcing 10mb or 100mb? */
@@ -1415,12 +1469,12 @@ void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1415 ctrl |= E1000_CTRL_SPD_100; 1469 ctrl |= E1000_CTRL_SPD_100;
1416 *phy_ctrl |= MII_CR_SPEED_100; 1470 *phy_ctrl |= MII_CR_SPEED_100;
1417 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1471 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1418 hw_dbg(hw, "Forcing 100mb\n"); 1472 e_dbg("Forcing 100mb\n");
1419 } else { 1473 } else {
1420 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1474 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1421 *phy_ctrl |= MII_CR_SPEED_10; 1475 *phy_ctrl |= MII_CR_SPEED_10;
1422 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1476 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1423 hw_dbg(hw, "Forcing 10mb\n"); 1477 e_dbg("Forcing 10mb\n");
1424 } 1478 }
1425 1479
1426 e1000e_config_collision_dist(hw); 1480 e1000e_config_collision_dist(hw);
@@ -1523,8 +1577,8 @@ s32 e1000e_check_downshift(struct e1000_hw *hw)
1523 switch (phy->type) { 1577 switch (phy->type) {
1524 case e1000_phy_m88: 1578 case e1000_phy_m88:
1525 case e1000_phy_gg82563: 1579 case e1000_phy_gg82563:
1580 case e1000_phy_bm:
1526 case e1000_phy_82578: 1581 case e1000_phy_82578:
1527 case e1000_phy_82577:
1528 offset = M88E1000_PHY_SPEC_STATUS; 1582 offset = M88E1000_PHY_SPEC_STATUS;
1529 mask = M88E1000_PSSR_DOWNSHIFT; 1583 mask = M88E1000_PSSR_DOWNSHIFT;
1530 break; 1584 break;
@@ -1535,7 +1589,7 @@ s32 e1000e_check_downshift(struct e1000_hw *hw)
1535 break; 1589 break;
1536 default: 1590 default:
1537 /* speed downshift not supported */ 1591 /* speed downshift not supported */
1538 phy->speed_downgraded = 0; 1592 phy->speed_downgraded = false;
1539 return 0; 1593 return 0;
1540 } 1594 }
1541 1595
@@ -1555,7 +1609,7 @@ s32 e1000e_check_downshift(struct e1000_hw *hw)
1555 * 1609 *
1556 * Polarity is determined based on the PHY specific status register. 1610 * Polarity is determined based on the PHY specific status register.
1557 **/ 1611 **/
1558static s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1612s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1559{ 1613{
1560 struct e1000_phy_info *phy = &hw->phy; 1614 struct e1000_phy_info *phy = &hw->phy;
1561 s32 ret_val; 1615 s32 ret_val;
@@ -1580,7 +1634,7 @@ static s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1580 * Polarity is determined based on the PHY port status register, and the 1634 * Polarity is determined based on the PHY port status register, and the
1581 * current speed (since there is no polarity at 100Mbps). 1635 * current speed (since there is no polarity at 100Mbps).
1582 **/ 1636 **/
1583static s32 e1000_check_polarity_igp(struct e1000_hw *hw) 1637s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1584{ 1638{
1585 struct e1000_phy_info *phy = &hw->phy; 1639 struct e1000_phy_info *phy = &hw->phy;
1586 s32 ret_val; 1640 s32 ret_val;
@@ -1618,6 +1672,39 @@ static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1618} 1672}
1619 1673
1620/** 1674/**
1675 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1676 * @hw: pointer to the HW structure
1677 *
1678 * Polarity is determined on the polarity reversal feature being enabled.
1679 **/
1680s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1681{
1682 struct e1000_phy_info *phy = &hw->phy;
1683 s32 ret_val;
1684 u16 phy_data, offset, mask;
1685
1686 /*
1687 * Polarity is determined based on the reversal feature being enabled.
1688 */
1689 if (phy->polarity_correction) {
1690 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1691 mask = IFE_PESC_POLARITY_REVERSED;
1692 } else {
1693 offset = IFE_PHY_SPECIAL_CONTROL;
1694 mask = IFE_PSC_FORCE_POLARITY;
1695 }
1696
1697 ret_val = e1e_rphy(hw, offset, &phy_data);
1698
1699 if (!ret_val)
1700 phy->cable_polarity = (phy_data & mask)
1701 ? e1000_rev_polarity_reversed
1702 : e1000_rev_polarity_normal;
1703
1704 return ret_val;
1705}
1706
1707/**
1621 * e1000_wait_autoneg - Wait for auto-neg completion 1708 * e1000_wait_autoneg - Wait for auto-neg completion
1622 * @hw: pointer to the HW structure 1709 * @hw: pointer to the HW structure
1623 * 1710 *
@@ -1717,15 +1804,21 @@ s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1717 1804
1718 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1805 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1719 if (ret_val) 1806 if (ret_val)
1720 return ret_val; 1807 goto out;
1721 1808
1722 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1809 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1723 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1810 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1811 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1812 ret_val = -E1000_ERR_PHY;
1813 goto out;
1814 }
1815
1724 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1816 phy->min_cable_length = e1000_m88_cable_length_table[index];
1725 phy->max_cable_length = e1000_m88_cable_length_table[index+1]; 1817 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1726 1818
1727 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1819 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1728 1820
1821out:
1729 return ret_val; 1822 return ret_val;
1730} 1823}
1731 1824
@@ -1736,7 +1829,7 @@ s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1736 * The automatic gain control (agc) normalizes the amplitude of the 1829 * The automatic gain control (agc) normalizes the amplitude of the
1737 * received signal, adjusting for the attenuation produced by the 1830 * received signal, adjusting for the attenuation produced by the
1738 * cable. By reading the AGC registers, which represent the 1831 * cable. By reading the AGC registers, which represent the
1739 * combination of course and fine gain value, the value can be put 1832 * combination of coarse and fine gain value, the value can be put
1740 * into a lookup table to obtain the approximate cable length 1833 * into a lookup table to obtain the approximate cable length
1741 * for each channel. 1834 * for each channel.
1742 **/ 1835 **/
@@ -1761,7 +1854,7 @@ s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1761 1854
1762 /* 1855 /*
1763 * Getting bits 15:9, which represent the combination of 1856 * Getting bits 15:9, which represent the combination of
1764 * course and fine gain values. The result is a number 1857 * coarse and fine gain values. The result is a number
1765 * that can be put into the lookup table to obtain the 1858 * that can be put into the lookup table to obtain the
1766 * approximate cable length. 1859 * approximate cable length.
1767 */ 1860 */
@@ -1815,8 +1908,8 @@ s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1815 u16 phy_data; 1908 u16 phy_data;
1816 bool link; 1909 bool link;
1817 1910
1818 if (hw->phy.media_type != e1000_media_type_copper) { 1911 if (phy->media_type != e1000_media_type_copper) {
1819 hw_dbg(hw, "Phy info is only valid for copper media\n"); 1912 e_dbg("Phy info is only valid for copper media\n");
1820 return -E1000_ERR_CONFIG; 1913 return -E1000_ERR_CONFIG;
1821 } 1914 }
1822 1915
@@ -1825,7 +1918,7 @@ s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1825 return ret_val; 1918 return ret_val;
1826 1919
1827 if (!link) { 1920 if (!link) {
1828 hw_dbg(hw, "Phy info is only valid if link is up\n"); 1921 e_dbg("Phy info is only valid if link is up\n");
1829 return -E1000_ERR_CONFIG; 1922 return -E1000_ERR_CONFIG;
1830 } 1923 }
1831 1924
@@ -1893,11 +1986,11 @@ s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1893 return ret_val; 1986 return ret_val;
1894 1987
1895 if (!link) { 1988 if (!link) {
1896 hw_dbg(hw, "Phy info is only valid if link is up\n"); 1989 e_dbg("Phy info is only valid if link is up\n");
1897 return -E1000_ERR_CONFIG; 1990 return -E1000_ERR_CONFIG;
1898 } 1991 }
1899 1992
1900 phy->polarity_correction = 1; 1993 phy->polarity_correction = true;
1901 1994
1902 ret_val = e1000_check_polarity_igp(hw); 1995 ret_val = e1000_check_polarity_igp(hw);
1903 if (ret_val) 1996 if (ret_val)
@@ -1936,6 +2029,61 @@ s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1936} 2029}
1937 2030
1938/** 2031/**
2032 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2033 * @hw: pointer to the HW structure
2034 *
2035 * Populates "phy" structure with various feature states.
2036 **/
2037s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2038{
2039 struct e1000_phy_info *phy = &hw->phy;
2040 s32 ret_val;
2041 u16 data;
2042 bool link;
2043
2044 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2045 if (ret_val)
2046 goto out;
2047
2048 if (!link) {
2049 e_dbg("Phy info is only valid if link is up\n");
2050 ret_val = -E1000_ERR_CONFIG;
2051 goto out;
2052 }
2053
2054 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2055 if (ret_val)
2056 goto out;
2057 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2058 ? false : true;
2059
2060 if (phy->polarity_correction) {
2061 ret_val = e1000_check_polarity_ife(hw);
2062 if (ret_val)
2063 goto out;
2064 } else {
2065 /* Polarity is forced */
2066 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2067 ? e1000_rev_polarity_reversed
2068 : e1000_rev_polarity_normal;
2069 }
2070
2071 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2072 if (ret_val)
2073 goto out;
2074
2075 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
2076
2077 /* The following parameters are undefined for 10/100 operation. */
2078 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2079 phy->local_rx = e1000_1000t_rx_status_undefined;
2080 phy->remote_rx = e1000_1000t_rx_status_undefined;
2081
2082out:
2083 return ret_val;
2084}
2085
2086/**
1939 * e1000e_phy_sw_reset - PHY software reset 2087 * e1000e_phy_sw_reset - PHY software reset
1940 * @hw: pointer to the HW structure 2088 * @hw: pointer to the HW structure
1941 * 2089 *
@@ -1980,7 +2128,7 @@ s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
1980 if (ret_val) 2128 if (ret_val)
1981 return 0; 2129 return 0;
1982 2130
1983 ret_val = phy->ops.acquire_phy(hw); 2131 ret_val = phy->ops.acquire(hw);
1984 if (ret_val) 2132 if (ret_val)
1985 return ret_val; 2133 return ret_val;
1986 2134
@@ -1995,7 +2143,7 @@ s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
1995 2143
1996 udelay(150); 2144 udelay(150);
1997 2145
1998 phy->ops.release_phy(hw); 2146 phy->ops.release(hw);
1999 2147
2000 return e1000_get_phy_cfg_done(hw); 2148 return e1000_get_phy_cfg_done(hw);
2001} 2149}
@@ -2021,7 +2169,7 @@ s32 e1000e_get_cfg_done(struct e1000_hw *hw)
2021 **/ 2169 **/
2022s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) 2170s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2023{ 2171{
2024 hw_dbg(hw, "Running IGP 3 PHY init script\n"); 2172 e_dbg("Running IGP 3 PHY init script\n");
2025 2173
2026 /* PHY init IGP 3 */ 2174 /* PHY init IGP 3 */
2027 /* Enable rise/fall, 10-mode work in class-A */ 2175 /* Enable rise/fall, 10-mode work in class-A */
@@ -2189,28 +2337,34 @@ enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2189s32 e1000e_determine_phy_address(struct e1000_hw *hw) 2337s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2190{ 2338{
2191 s32 ret_val = -E1000_ERR_PHY_TYPE; 2339 s32 ret_val = -E1000_ERR_PHY_TYPE;
2192 u32 phy_addr= 0; 2340 u32 phy_addr = 0;
2193 u32 i = 0; 2341 u32 i;
2194 enum e1000_phy_type phy_type = e1000_phy_unknown; 2342 enum e1000_phy_type phy_type = e1000_phy_unknown;
2195 2343
2196 do { 2344 hw->phy.id = phy_type;
2197 for (phy_addr = 0; phy_addr < 4; phy_addr++) { 2345
2198 hw->phy.addr = phy_addr; 2346 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2347 hw->phy.addr = phy_addr;
2348 i = 0;
2349
2350 do {
2199 e1000e_get_phy_id(hw); 2351 e1000e_get_phy_id(hw);
2200 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); 2352 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2201 2353
2202 /* 2354 /*
2203 * If phy_type is valid, break - we found our 2355 * If phy_type is valid, break - we found our
2204 * PHY address 2356 * PHY address
2205 */ 2357 */
2206 if (phy_type != e1000_phy_unknown) { 2358 if (phy_type != e1000_phy_unknown) {
2207 ret_val = 0; 2359 ret_val = 0;
2208 break; 2360 goto out;
2209 } 2361 }
2210 } 2362 msleep(1);
2211 i++; 2363 i++;
2212 } while ((ret_val != 0) && (i < 100)); 2364 } while (i < 10);
2365 }
2213 2366
2367out:
2214 return ret_val; 2368 return ret_val;
2215} 2369}
2216 2370
@@ -2246,7 +2400,7 @@ s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2246 u32 page = offset >> IGP_PAGE_SHIFT; 2400 u32 page = offset >> IGP_PAGE_SHIFT;
2247 u32 page_shift = 0; 2401 u32 page_shift = 0;
2248 2402
2249 ret_val = hw->phy.ops.acquire_phy(hw); 2403 ret_val = hw->phy.ops.acquire(hw);
2250 if (ret_val) 2404 if (ret_val)
2251 return ret_val; 2405 return ret_val;
2252 2406
@@ -2284,7 +2438,7 @@ s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2284 data); 2438 data);
2285 2439
2286out: 2440out:
2287 hw->phy.ops.release_phy(hw); 2441 hw->phy.ops.release(hw);
2288 return ret_val; 2442 return ret_val;
2289} 2443}
2290 2444
@@ -2305,7 +2459,7 @@ s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2305 u32 page = offset >> IGP_PAGE_SHIFT; 2459 u32 page = offset >> IGP_PAGE_SHIFT;
2306 u32 page_shift = 0; 2460 u32 page_shift = 0;
2307 2461
2308 ret_val = hw->phy.ops.acquire_phy(hw); 2462 ret_val = hw->phy.ops.acquire(hw);
2309 if (ret_val) 2463 if (ret_val)
2310 return ret_val; 2464 return ret_val;
2311 2465
@@ -2342,7 +2496,7 @@ s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2342 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2496 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2343 data); 2497 data);
2344out: 2498out:
2345 hw->phy.ops.release_phy(hw); 2499 hw->phy.ops.release(hw);
2346 return ret_val; 2500 return ret_val;
2347} 2501}
2348 2502
@@ -2361,7 +2515,7 @@ s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2361 s32 ret_val; 2515 s32 ret_val;
2362 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2516 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2363 2517
2364 ret_val = hw->phy.ops.acquire_phy(hw); 2518 ret_val = hw->phy.ops.acquire(hw);
2365 if (ret_val) 2519 if (ret_val)
2366 return ret_val; 2520 return ret_val;
2367 2521
@@ -2387,7 +2541,7 @@ s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2387 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2541 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2388 data); 2542 data);
2389out: 2543out:
2390 hw->phy.ops.release_phy(hw); 2544 hw->phy.ops.release(hw);
2391 return ret_val; 2545 return ret_val;
2392} 2546}
2393 2547
@@ -2405,7 +2559,7 @@ s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2405 s32 ret_val; 2559 s32 ret_val;
2406 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2560 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2407 2561
2408 ret_val = hw->phy.ops.acquire_phy(hw); 2562 ret_val = hw->phy.ops.acquire(hw);
2409 if (ret_val) 2563 if (ret_val)
2410 return ret_val; 2564 return ret_val;
2411 2565
@@ -2431,7 +2585,7 @@ s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2431 data); 2585 data);
2432 2586
2433out: 2587out:
2434 hw->phy.ops.release_phy(hw); 2588 hw->phy.ops.release(hw);
2435 return ret_val; 2589 return ret_val;
2436} 2590}
2437 2591
@@ -2464,7 +2618,7 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2464 /* Gig must be disabled for MDIO accesses to page 800 */ 2618 /* Gig must be disabled for MDIO accesses to page 800 */
2465 if ((hw->mac.type == e1000_pchlan) && 2619 if ((hw->mac.type == e1000_pchlan) &&
2466 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 2620 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2467 hw_dbg(hw, "Attempting to access page 800 while gig enabled\n"); 2621 e_dbg("Attempting to access page 800 while gig enabled.\n");
2468 2622
2469 /* All operations in this function are phy address 1 */ 2623 /* All operations in this function are phy address 1 */
2470 hw->phy.addr = 1; 2624 hw->phy.addr = 1;
@@ -2474,20 +2628,26 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2474 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2628 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2475 2629
2476 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); 2630 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
2477 if (ret_val) 2631 if (ret_val) {
2632 e_dbg("Could not read PHY page 769\n");
2478 goto out; 2633 goto out;
2634 }
2479 2635
2480 /* First clear bit 4 to avoid a power state change */ 2636 /* First clear bit 4 to avoid a power state change */
2481 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 2637 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
2482 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2638 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2483 if (ret_val) 2639 if (ret_val) {
2640 e_dbg("Could not clear PHY page 769 bit 4\n");
2484 goto out; 2641 goto out;
2642 }
2485 2643
2486 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 2644 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2487 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, 2645 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
2488 phy_reg | BM_WUC_ENABLE_BIT); 2646 phy_reg | BM_WUC_ENABLE_BIT);
2489 if (ret_val) 2647 if (ret_val) {
2648 e_dbg("Could not write PHY page 769 bit 2\n");
2490 goto out; 2649 goto out;
2650 }
2491 2651
2492 /* Select page 800 */ 2652 /* Select page 800 */
2493 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2653 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
@@ -2495,21 +2655,25 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2495 2655
2496 /* Write the page 800 offset value using opcode 0x11 */ 2656 /* Write the page 800 offset value using opcode 0x11 */
2497 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2657 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2498 if (ret_val) 2658 if (ret_val) {
2659 e_dbg("Could not write address opcode to page 800\n");
2499 goto out; 2660 goto out;
2661 }
2500 2662
2501 if (read) { 2663 if (read) {
2502 /* Read the page 800 value using opcode 0x12 */ 2664 /* Read the page 800 value using opcode 0x12 */
2503 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2665 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2504 data); 2666 data);
2505 } else { 2667 } else {
2506 /* Read the page 800 value using opcode 0x12 */ 2668 /* Write the page 800 value using opcode 0x12 */
2507 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2669 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2508 *data); 2670 *data);
2509 } 2671 }
2510 2672
2511 if (ret_val) 2673 if (ret_val) {
2674 e_dbg("Could not access data value from page 800\n");
2512 goto out; 2675 goto out;
2676 }
2513 2677
2514 /* 2678 /*
2515 * Restore 769_17.2 to its original value 2679 * Restore 769_17.2 to its original value
@@ -2520,12 +2684,53 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2520 2684
2521 /* Clear 769_17.2 */ 2685 /* Clear 769_17.2 */
2522 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2686 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2687 if (ret_val) {
2688 e_dbg("Could not clear PHY page 769 bit 2\n");
2689 goto out;
2690 }
2523 2691
2524out: 2692out:
2525 return ret_val; 2693 return ret_val;
2526} 2694}
2527 2695
2528/** 2696/**
2697 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2698 * @hw: pointer to the HW structure
2699 *
2700 * In the case of a PHY power down to save power, or to turn off link during a
2701 * driver unload, or wake on lan is not enabled, restore the link to previous
2702 * settings.
2703 **/
2704void e1000_power_up_phy_copper(struct e1000_hw *hw)
2705{
2706 u16 mii_reg = 0;
2707
2708 /* The PHY will retain its settings across a power down/up cycle */
2709 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2710 mii_reg &= ~MII_CR_POWER_DOWN;
2711 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2712}
2713
2714/**
2715 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2716 * @hw: pointer to the HW structure
2717 *
2718 * In the case of a PHY power down to save power, or to turn off link during a
2719 * driver unload, or wake on lan is not enabled, restore the link to previous
2720 * settings.
2721 **/
2722void e1000_power_down_phy_copper(struct e1000_hw *hw)
2723{
2724 u16 mii_reg = 0;
2725
2726 /* The PHY will retain its settings across a power down/up cycle */
2727 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2728 mii_reg |= MII_CR_POWER_DOWN;
2729 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2730 msleep(1);
2731}
2732
2733/**
2529 * e1000e_commit_phy - Soft PHY reset 2734 * e1000e_commit_phy - Soft PHY reset
2530 * @hw: pointer to the HW structure 2735 * @hw: pointer to the HW structure
2531 * 2736 *
@@ -2534,8 +2739,8 @@ out:
2534 **/ 2739 **/
2535s32 e1000e_commit_phy(struct e1000_hw *hw) 2740s32 e1000e_commit_phy(struct e1000_hw *hw)
2536{ 2741{
2537 if (hw->phy.ops.commit_phy) 2742 if (hw->phy.ops.commit)
2538 return hw->phy.ops.commit_phy(hw); 2743 return hw->phy.ops.commit(hw);
2539 2744
2540 return 0; 2745 return 0;
2541} 2746}
@@ -2563,38 +2768,6 @@ static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2563} 2768}
2564 2769
2565/** 2770/**
2566 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2567 * @hw: pointer to the HW structure
2568 * @slow: true for slow mode, false for normal mode
2569 *
2570 * Assumes semaphore already acquired.
2571 **/
2572s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow)
2573{
2574 s32 ret_val = 0;
2575 u16 data = 0;
2576
2577 /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */
2578 hw->phy.addr = 1;
2579 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2580 (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2581 if (ret_val)
2582 goto out;
2583
2584 ret_val = e1000e_write_phy_reg_mdic(hw, BM_CS_CTRL1,
2585 (0x2180 | (slow << 10)));
2586 if (ret_val)
2587 goto out;
2588
2589 /* dummy read when reverting to fast mode - throw away result */
2590 if (!slow)
2591 ret_val = e1000e_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data);
2592
2593out:
2594 return ret_val;
2595}
2596
2597/**
2598 * __e1000_read_phy_reg_hv - Read HV PHY register 2771 * __e1000_read_phy_reg_hv - Read HV PHY register
2599 * @hw: pointer to the HW structure 2772 * @hw: pointer to the HW structure
2600 * @offset: register offset to be read 2773 * @offset: register offset to be read
@@ -2611,24 +2784,13 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2611 s32 ret_val; 2784 s32 ret_val;
2612 u16 page = BM_PHY_REG_PAGE(offset); 2785 u16 page = BM_PHY_REG_PAGE(offset);
2613 u16 reg = BM_PHY_REG_NUM(offset); 2786 u16 reg = BM_PHY_REG_NUM(offset);
2614 bool in_slow_mode = false;
2615 2787
2616 if (!locked) { 2788 if (!locked) {
2617 ret_val = hw->phy.ops.acquire_phy(hw); 2789 ret_val = hw->phy.ops.acquire(hw);
2618 if (ret_val) 2790 if (ret_val)
2619 return ret_val; 2791 return ret_val;
2620 } 2792 }
2621 2793
2622 /* Workaround failure in MDIO access while cable is disconnected */
2623 if ((hw->phy.type == e1000_phy_82577) &&
2624 !(er32(STATUS) & E1000_STATUS_LU)) {
2625 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
2626 if (ret_val)
2627 goto out;
2628
2629 in_slow_mode = true;
2630 }
2631
2632 /* Page 800 works differently than the rest so it has its own func */ 2794 /* Page 800 works differently than the rest so it has its own func */
2633 if (page == BM_WUC_PAGE) { 2795 if (page == BM_WUC_PAGE) {
2634 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, 2796 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
@@ -2665,12 +2827,8 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2665 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 2827 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2666 data); 2828 data);
2667out: 2829out:
2668 /* Revert to MDIO fast mode, if applicable */
2669 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
2670 ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
2671
2672 if (!locked) 2830 if (!locked)
2673 hw->phy.ops.release_phy(hw); 2831 hw->phy.ops.release(hw);
2674 2832
2675 return ret_val; 2833 return ret_val;
2676} 2834}
@@ -2720,24 +2878,13 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2720 s32 ret_val; 2878 s32 ret_val;
2721 u16 page = BM_PHY_REG_PAGE(offset); 2879 u16 page = BM_PHY_REG_PAGE(offset);
2722 u16 reg = BM_PHY_REG_NUM(offset); 2880 u16 reg = BM_PHY_REG_NUM(offset);
2723 bool in_slow_mode = false;
2724 2881
2725 if (!locked) { 2882 if (!locked) {
2726 ret_val = hw->phy.ops.acquire_phy(hw); 2883 ret_val = hw->phy.ops.acquire(hw);
2727 if (ret_val) 2884 if (ret_val)
2728 return ret_val; 2885 return ret_val;
2729 } 2886 }
2730 2887
2731 /* Workaround failure in MDIO access while cable is disconnected */
2732 if ((hw->phy.type == e1000_phy_82577) &&
2733 !(er32(STATUS) & E1000_STATUS_LU)) {
2734 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
2735 if (ret_val)
2736 goto out;
2737
2738 in_slow_mode = true;
2739 }
2740
2741 /* Page 800 works differently than the rest so it has its own func */ 2888 /* Page 800 works differently than the rest so it has its own func */
2742 if (page == BM_WUC_PAGE) { 2889 if (page == BM_WUC_PAGE) {
2743 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, 2890 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
@@ -2791,12 +2938,8 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2791 data); 2938 data);
2792 2939
2793out: 2940out:
2794 /* Revert to MDIO fast mode, if applicable */
2795 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
2796 ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
2797
2798 if (!locked) 2941 if (!locked)
2799 hw->phy.ops.release_phy(hw); 2942 hw->phy.ops.release(hw);
2800 2943
2801 return ret_val; 2944 return ret_val;
2802} 2945}
@@ -2872,7 +3015,7 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
2872 /* masking with 0x3F to remove the page from offset */ 3015 /* masking with 0x3F to remove the page from offset */
2873 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3016 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
2874 if (ret_val) { 3017 if (ret_val) {
2875 hw_dbg(hw, "Could not write PHY the HV address register\n"); 3018 e_dbg("Could not write PHY the HV address register\n");
2876 goto out; 3019 goto out;
2877 } 3020 }
2878 3021
@@ -2883,7 +3026,7 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
2883 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); 3026 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
2884 3027
2885 if (ret_val) { 3028 if (ret_val) {
2886 hw_dbg(hw, "Could not read data value from HV data register\n"); 3029 e_dbg("Could not read data value from HV data register\n");
2887 goto out; 3030 goto out;
2888 } 3031 }
2889 3032
@@ -2911,12 +3054,12 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
2911 goto out; 3054 goto out;
2912 3055
2913 /* Do not apply workaround if in PHY loopback bit 14 set */ 3056 /* Do not apply workaround if in PHY loopback bit 14 set */
2914 hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &data); 3057 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
2915 if (data & PHY_CONTROL_LB) 3058 if (data & PHY_CONTROL_LB)
2916 goto out; 3059 goto out;
2917 3060
2918 /* check if link is up and at 1Gbps */ 3061 /* check if link is up and at 1Gbps */
2919 ret_val = hw->phy.ops.read_phy_reg(hw, BM_CS_STATUS, &data); 3062 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
2920 if (ret_val) 3063 if (ret_val)
2921 goto out; 3064 goto out;
2922 3065
@@ -2932,13 +3075,13 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
2932 mdelay(200); 3075 mdelay(200);
2933 3076
2934 /* flush the packets in the fifo buffer */ 3077 /* flush the packets in the fifo buffer */
2935 ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL, 3078 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
2936 HV_MUX_DATA_CTRL_GEN_TO_MAC | 3079 HV_MUX_DATA_CTRL_GEN_TO_MAC |
2937 HV_MUX_DATA_CTRL_FORCE_SPEED); 3080 HV_MUX_DATA_CTRL_FORCE_SPEED);
2938 if (ret_val) 3081 if (ret_val)
2939 goto out; 3082 goto out;
2940 3083
2941 ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL, 3084 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
2942 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3085 HV_MUX_DATA_CTRL_GEN_TO_MAC);
2943 3086
2944out: 3087out:
@@ -2959,7 +3102,7 @@ s32 e1000_check_polarity_82577(struct e1000_hw *hw)
2959 s32 ret_val; 3102 s32 ret_val;
2960 u16 data; 3103 u16 data;
2961 3104
2962 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data); 3105 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
2963 3106
2964 if (!ret_val) 3107 if (!ret_val)
2965 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3108 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
@@ -2984,13 +3127,13 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
2984 u16 phy_data; 3127 u16 phy_data;
2985 bool link; 3128 bool link;
2986 3129
2987 ret_val = phy->ops.read_phy_reg(hw, PHY_CONTROL, &phy_data); 3130 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2988 if (ret_val) 3131 if (ret_val)
2989 goto out; 3132 goto out;
2990 3133
2991 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 3134 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
2992 3135
2993 ret_val = phy->ops.write_phy_reg(hw, PHY_CONTROL, phy_data); 3136 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2994 if (ret_val) 3137 if (ret_val)
2995 goto out; 3138 goto out;
2996 3139
@@ -2998,23 +3141,23 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
2998 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI 3141 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
2999 * forced whenever speed and duplex are forced. 3142 * forced whenever speed and duplex are forced.
3000 */ 3143 */
3001 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_CTRL_2, &phy_data); 3144 ret_val = phy->ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
3002 if (ret_val) 3145 if (ret_val)
3003 goto out; 3146 goto out;
3004 3147
3005 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX; 3148 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX;
3006 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX; 3149 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX;
3007 3150
3008 ret_val = phy->ops.write_phy_reg(hw, I82577_PHY_CTRL_2, phy_data); 3151 ret_val = phy->ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
3009 if (ret_val) 3152 if (ret_val)
3010 goto out; 3153 goto out;
3011 3154
3012 hw_dbg(hw, "I82577_PHY_CTRL_2: %X\n", phy_data); 3155 e_dbg("I82577_PHY_CTRL_2: %X\n", phy_data);
3013 3156
3014 udelay(1); 3157 udelay(1);
3015 3158
3016 if (phy->autoneg_wait_to_complete) { 3159 if (phy->autoneg_wait_to_complete) {
3017 hw_dbg(hw, "Waiting for forced speed/duplex link on 82577 phy\n"); 3160 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3018 3161
3019 ret_val = e1000e_phy_has_link_generic(hw, 3162 ret_val = e1000e_phy_has_link_generic(hw,
3020 PHY_FORCE_LIMIT, 3163 PHY_FORCE_LIMIT,
@@ -3024,7 +3167,7 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3024 goto out; 3167 goto out;
3025 3168
3026 if (!link) 3169 if (!link)
3027 hw_dbg(hw, "Link taking longer than expected.\n"); 3170 e_dbg("Link taking longer than expected.\n");
3028 3171
3029 /* Try once more */ 3172 /* Try once more */
3030 ret_val = e1000e_phy_has_link_generic(hw, 3173 ret_val = e1000e_phy_has_link_generic(hw,
@@ -3060,7 +3203,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3060 goto out; 3203 goto out;
3061 3204
3062 if (!link) { 3205 if (!link) {
3063 hw_dbg(hw, "Phy info is only valid if link is up\n"); 3206 e_dbg("Phy info is only valid if link is up\n");
3064 ret_val = -E1000_ERR_CONFIG; 3207 ret_val = -E1000_ERR_CONFIG;
3065 goto out; 3208 goto out;
3066 } 3209 }
@@ -3071,7 +3214,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3071 if (ret_val) 3214 if (ret_val)
3072 goto out; 3215 goto out;
3073 3216
3074 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data); 3217 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3075 if (ret_val) 3218 if (ret_val)
3076 goto out; 3219 goto out;
3077 3220
@@ -3083,7 +3226,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3083 if (ret_val) 3226 if (ret_val)
3084 goto out; 3227 goto out;
3085 3228
3086 ret_val = phy->ops.read_phy_reg(hw, PHY_1000T_STATUS, &data); 3229 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3087 if (ret_val) 3230 if (ret_val)
3088 goto out; 3231 goto out;
3089 3232
@@ -3117,7 +3260,7 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3117 s32 ret_val; 3260 s32 ret_val;
3118 u16 phy_data, length; 3261 u16 phy_data, length;
3119 3262
3120 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3263 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3121 if (ret_val) 3264 if (ret_val)
3122 goto out; 3265 goto out;
3123 3266
@@ -3125,7 +3268,7 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3125 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 3268 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3126 3269
3127 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3270 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3128 ret_val = E1000_ERR_PHY; 3271 ret_val = -E1000_ERR_PHY;
3129 3272
3130 phy->cable_length = length; 3273 phy->cable_length = length;
3131 3274
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-02 08:08:37 -0400