e1000e: check return code from NVM accesses and fix bank detection

Check return code for all NVM accesses[1] and error out accordingly; log
a debug message for failed accesses.

For ICH8/9, the valid NVM bank detect function was not checking whether the
SEC1VAL (sector 1 valid) bit in the EECD register was itself valid (bits 8
and 9 also have to be set).  If invalid, it would have defaulted to the
possibly invalid bank 0.  Instead, try to use the valid bank detection
method used by ICH10 which has been cleaned up a bit.

[1] - reads and updates only; not writes because those are only writing to
the Shadow RAM, the update following the write is the only thing actually
writing the modified Shadow RAM contents to the NVM.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index b1b534d267ed..ca5d3f58329d 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -4723,14 +4723,14 @@ static void e1000_eeprom_checks(struct e1000_adapter *adapter)
                 return;
 
         ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
-        if (!(le16_to_cpu(buf) & (1 << 0))) {
+        if (!ret_val && (!(le16_to_cpu(buf) & (1 << 0)))) {
                 /* Deep Smart Power Down (DSPD) */
                 dev_warn(&adapter->pdev->dev,
                          "Warning: detected DSPD enabled in EEPROM\n");
         }
 
         ret_val = e1000_read_nvm(hw, NVM_INIT_3GIO_3, 1, &buf);
-        if (le16_to_cpu(buf) & (3 << 2)) {
+        if (!ret_val && (le16_to_cpu(buf) & (3 << 2))) {
                 /* ASPM enable */
                 dev_warn(&adapter->pdev->dev,
                          "Warning: detected ASPM enabled in EEPROM\n");