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authorBruce Allan <bruce.w.allan@intel.com>2009-06-02 07:28:39 -0400
committerDavid S. Miller <davem@davemloft.net>2009-06-03 05:46:33 -0400
commit3ec2a2b80f3eb53851fe4cef9e65b5d33376ef89 (patch)
treeaa95f81379ccc614232fdf127e9706b5d61cc7a8 /drivers/net/e1000e/netdev.c
parent918d7197aa18a562eb7dc37b80a87e9ff1d7f7d9 (diff)
e1000e: correct flow control thresholds
The flow control thresholds, i.e. high and low watermarks of the Rx FIFO for when the hardware should transmit PAUSE frames (XON and XOFF, respectively), need to be tuned for more efficient use of the FIFO. The logic to set the thresholds for parts that support early-receive (ERT) was also wrong in that it should check whether jumbo frames are in use. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/e1000e/netdev.c')
-rw-r--r--drivers/net/e1000e/netdev.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index 7e412d1168ed..b7a46c513783 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -2751,23 +2751,25 @@ void e1000e_reset(struct e1000_adapter *adapter)
2751 /* 2751 /*
2752 * flow control settings 2752 * flow control settings
2753 * 2753 *
2754 * The high water mark must be low enough to fit one full frame 2754 * The high water mark must be low enough to fit two full frame
2755 * (or the size used for early receive) above it in the Rx FIFO. 2755 * (or the size used for early receive) above it in the Rx FIFO.
2756 * Set it to the lower of: 2756 * Set it to the lower of:
2757 * - 90% of the Rx FIFO size, and 2757 * - 90% of the Rx FIFO size, and
2758 * - the full Rx FIFO size minus the early receive size (for parts 2758 * - the full Rx FIFO size minus the early receive size (for parts
2759 * with ERT support assuming ERT set to E1000_ERT_2048), or 2759 * with ERT support assuming ERT set to E1000_ERT_2048), or
2760 * - the full Rx FIFO size minus one full frame 2760 * - the full Rx FIFO size minus two full frames
2761 */ 2761 */
2762 if (adapter->flags & FLAG_HAS_ERT) 2762 if ((adapter->flags & FLAG_HAS_ERT) &&
2763 (adapter->netdev->mtu > ETH_DATA_LEN))
2763 hwm = min(((pba << 10) * 9 / 10), 2764 hwm = min(((pba << 10) * 9 / 10),
2764 ((pba << 10) - (E1000_ERT_2048 << 3))); 2765 ((pba << 10) - (E1000_ERT_2048 << 3)));
2765 else 2766 else
2766 hwm = min(((pba << 10) * 9 / 10), 2767 hwm = min(((pba << 10) * 9 / 10),
2767 ((pba << 10) - adapter->max_frame_size)); 2768 ((pba << 10) - (2 * adapter->max_frame_size)));
2768 2769
2769 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ 2770 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
2770 fc->low_water = fc->high_water - 8; 2771 fc->low_water = (fc->high_water - (2 * adapter->max_frame_size));
2772 fc->low_water &= E1000_FCRTL_RTL; /* 8-byte granularity */
2771 2773
2772 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 2774 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
2773 fc->pause_time = 0xFFFF; 2775 fc->pause_time = 0xFFFF;