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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2008-04-02 16:48:13 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-04-16 20:41:36 -0400
commite9ec2c0f4bfbe0632b22a2c0b74d5e1e96aeab66 (patch)
treee65a632498dad6f7eaf77f1d2b00aa0c237d60a5 /drivers/net/e1000e/82571.c
parent8d7c294cae6fd1474d88267810d1965f60a903af (diff)
e1000e: Make arrays out of these Rx/Tx registers
With multiple queues coming into the code these base control registers need to be made into arrays. Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/e1000e/82571.c')
-rw-r--r--drivers/net/e1000e/82571.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c
index 9b46a00bb5f1..85e476426b76 100644
--- a/drivers/net/e1000e/82571.c
+++ b/drivers/net/e1000e/82571.c
@@ -836,19 +836,19 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw)
836 ret_val = e1000_setup_link_82571(hw); 836 ret_val = e1000_setup_link_82571(hw);
837 837
838 /* Set the transmit descriptor write-back policy */ 838 /* Set the transmit descriptor write-back policy */
839 reg_data = er32(TXDCTL); 839 reg_data = er32(TXDCTL(0));
840 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 840 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
841 E1000_TXDCTL_FULL_TX_DESC_WB | 841 E1000_TXDCTL_FULL_TX_DESC_WB |
842 E1000_TXDCTL_COUNT_DESC; 842 E1000_TXDCTL_COUNT_DESC;
843 ew32(TXDCTL, reg_data); 843 ew32(TXDCTL(0), reg_data);
844 844
845 /* ...for both queues. */ 845 /* ...for both queues. */
846 if (mac->type != e1000_82573) { 846 if (mac->type != e1000_82573) {
847 reg_data = er32(TXDCTL1); 847 reg_data = er32(TXDCTL(1));
848 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 848 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
849 E1000_TXDCTL_FULL_TX_DESC_WB | 849 E1000_TXDCTL_FULL_TX_DESC_WB |
850 E1000_TXDCTL_COUNT_DESC; 850 E1000_TXDCTL_COUNT_DESC;
851 ew32(TXDCTL1, reg_data); 851 ew32(TXDCTL(1), reg_data);
852 } else { 852 } else {
853 e1000e_enable_tx_pkt_filtering(hw); 853 e1000e_enable_tx_pkt_filtering(hw);
854 reg_data = er32(GCR); 854 reg_data = er32(GCR);
@@ -878,17 +878,17 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
878 u32 reg; 878 u32 reg;
879 879
880 /* Transmit Descriptor Control 0 */ 880 /* Transmit Descriptor Control 0 */
881 reg = er32(TXDCTL); 881 reg = er32(TXDCTL(0));
882 reg |= (1 << 22); 882 reg |= (1 << 22);
883 ew32(TXDCTL, reg); 883 ew32(TXDCTL(0), reg);
884 884
885 /* Transmit Descriptor Control 1 */ 885 /* Transmit Descriptor Control 1 */
886 reg = er32(TXDCTL1); 886 reg = er32(TXDCTL(1));
887 reg |= (1 << 22); 887 reg |= (1 << 22);
888 ew32(TXDCTL1, reg); 888 ew32(TXDCTL(1), reg);
889 889
890 /* Transmit Arbitration Control 0 */ 890 /* Transmit Arbitration Control 0 */
891 reg = er32(TARC0); 891 reg = er32(TARC(0));
892 reg &= ~(0xF << 27); /* 30:27 */ 892 reg &= ~(0xF << 27); /* 30:27 */
893 switch (hw->mac.type) { 893 switch (hw->mac.type) {
894 case e1000_82571: 894 case e1000_82571:
@@ -898,10 +898,10 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
898 default: 898 default:
899 break; 899 break;
900 } 900 }
901 ew32(TARC0, reg); 901 ew32(TARC(0), reg);
902 902
903 /* Transmit Arbitration Control 1 */ 903 /* Transmit Arbitration Control 1 */
904 reg = er32(TARC1); 904 reg = er32(TARC(1));
905 switch (hw->mac.type) { 905 switch (hw->mac.type) {
906 case e1000_82571: 906 case e1000_82571:
907 case e1000_82572: 907 case e1000_82572:
@@ -911,7 +911,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
911 reg &= ~(1 << 28); 911 reg &= ~(1 << 28);
912 else 912 else
913 reg |= (1 << 28); 913 reg |= (1 << 28);
914 ew32(TARC1, reg); 914 ew32(TARC(1), reg);
915 break; 915 break;
916 default: 916 default:
917 break; 917 break;