diff options
author | Andrew Lunn <andrew@lunn.ch> | 2014-09-12 17:58:44 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2014-09-13 17:26:47 -0400 |
commit | 42f272539487e49c9ea830ad97db41eb9937d5dc (patch) | |
tree | 922b7db911471a526b0164f4233e219f92535f41 /drivers/net/dsa | |
parent | 0943629688c62c69d1355bf2abcd217029899da0 (diff) |
net: DSA: Marvell mv88e6171 switch driver
This is the Marvell driver with some cleanups by Claudio Leite
and myself.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Cc: Claudio Leite <leitec@staticky.com>
Signed-off-by: Claudio Leite <leitec@staticky.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa')
-rw-r--r-- | drivers/net/dsa/Kconfig | 9 | ||||
-rw-r--r-- | drivers/net/dsa/Makefile | 3 | ||||
-rw-r--r-- | drivers/net/dsa/mv88e6171.c | 407 | ||||
-rw-r--r-- | drivers/net/dsa/mv88e6xxx.c | 6 | ||||
-rw-r--r-- | drivers/net/dsa/mv88e6xxx.h | 1 |
5 files changed, 426 insertions, 0 deletions
diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig index c6ee07c6a1b5..ea0697eaeff5 100644 --- a/drivers/net/dsa/Kconfig +++ b/drivers/net/dsa/Kconfig | |||
@@ -36,6 +36,15 @@ config NET_DSA_MV88E6123_61_65 | |||
36 | This enables support for the Marvell 88E6123/6161/6165 | 36 | This enables support for the Marvell 88E6123/6161/6165 |
37 | ethernet switch chips. | 37 | ethernet switch chips. |
38 | 38 | ||
39 | config NET_DSA_MV88E6171 | ||
40 | tristate "Marvell 88E6171 ethernet switch chip support" | ||
41 | select NET_DSA | ||
42 | select NET_DSA_MV88E6XXX | ||
43 | select NET_DSA_TAG_EDSA | ||
44 | ---help--- | ||
45 | This enables support for the Marvell 88E6171 ethernet switch | ||
46 | chip. | ||
47 | |||
39 | config NET_DSA_BCM_SF2 | 48 | config NET_DSA_BCM_SF2 |
40 | tristate "Broadcom Starfighter 2 Ethernet switch support" | 49 | tristate "Broadcom Starfighter 2 Ethernet switch support" |
41 | select NET_DSA | 50 | select NET_DSA |
diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile index dd3cd3b8157f..23a90de9830e 100644 --- a/drivers/net/dsa/Makefile +++ b/drivers/net/dsa/Makefile | |||
@@ -7,4 +7,7 @@ endif | |||
7 | ifdef CONFIG_NET_DSA_MV88E6131 | 7 | ifdef CONFIG_NET_DSA_MV88E6131 |
8 | mv88e6xxx_drv-y += mv88e6131.o | 8 | mv88e6xxx_drv-y += mv88e6131.o |
9 | endif | 9 | endif |
10 | ifdef CONFIG_NET_DSA_MV88E6171 | ||
11 | mv88e6xxx_drv-y += mv88e6171.o | ||
12 | endif | ||
10 | obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm_sf2.o | 13 | obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm_sf2.o |
diff --git a/drivers/net/dsa/mv88e6171.c b/drivers/net/dsa/mv88e6171.c new file mode 100644 index 000000000000..03a70069a8c6 --- /dev/null +++ b/drivers/net/dsa/mv88e6171.c | |||
@@ -0,0 +1,407 @@ | |||
1 | /* net/dsa/mv88e6171.c - Marvell 88e6171 switch chip support | ||
2 | * Copyright (c) 2008-2009 Marvell Semiconductor | ||
3 | * Copyright (c) 2014 Claudio Leite <leitec@staticky.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation; either version 2 of the License, or | ||
8 | * (at your option) any later version. | ||
9 | */ | ||
10 | |||
11 | #include <linux/delay.h> | ||
12 | #include <linux/jiffies.h> | ||
13 | #include <linux/list.h> | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/netdevice.h> | ||
16 | #include <linux/phy.h> | ||
17 | #include <net/dsa.h> | ||
18 | #include "mv88e6xxx.h" | ||
19 | |||
20 | static char *mv88e6171_probe(struct mii_bus *bus, int sw_addr) | ||
21 | { | ||
22 | int ret; | ||
23 | |||
24 | ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03); | ||
25 | if (ret >= 0) { | ||
26 | if ((ret & 0xfff0) == 0x1710) | ||
27 | return "Marvell 88E6171"; | ||
28 | } | ||
29 | |||
30 | return NULL; | ||
31 | } | ||
32 | |||
33 | static int mv88e6171_switch_reset(struct dsa_switch *ds) | ||
34 | { | ||
35 | int i; | ||
36 | int ret; | ||
37 | unsigned long timeout; | ||
38 | |||
39 | /* Set all ports to the disabled state. */ | ||
40 | for (i = 0; i < 8; i++) { | ||
41 | ret = REG_READ(REG_PORT(i), 0x04); | ||
42 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); | ||
43 | } | ||
44 | |||
45 | /* Wait for transmit queues to drain. */ | ||
46 | usleep_range(2000, 4000); | ||
47 | |||
48 | /* Reset the switch. */ | ||
49 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); | ||
50 | |||
51 | /* Wait up to one second for reset to complete. */ | ||
52 | timeout = jiffies + 1 * HZ; | ||
53 | while (time_before(jiffies, timeout)) { | ||
54 | ret = REG_READ(REG_GLOBAL, 0x00); | ||
55 | if ((ret & 0xc800) == 0xc800) | ||
56 | break; | ||
57 | |||
58 | usleep_range(1000, 2000); | ||
59 | } | ||
60 | if (time_after(jiffies, timeout)) | ||
61 | return -ETIMEDOUT; | ||
62 | |||
63 | /* Enable ports not under DSA, e.g. WAN port */ | ||
64 | for (i = 0; i < 8; i++) { | ||
65 | if (dsa_is_cpu_port(ds, i) || ds->phys_port_mask & (1 << i)) | ||
66 | continue; | ||
67 | |||
68 | ret = REG_READ(REG_PORT(i), 0x04); | ||
69 | REG_WRITE(REG_PORT(i), 0x04, ret | 0x03); | ||
70 | } | ||
71 | |||
72 | return 0; | ||
73 | } | ||
74 | |||
75 | static int mv88e6171_setup_global(struct dsa_switch *ds) | ||
76 | { | ||
77 | int ret; | ||
78 | int i; | ||
79 | |||
80 | /* Disable the PHY polling unit (since there won't be any | ||
81 | * external PHYs to poll), don't discard packets with | ||
82 | * excessive collisions, and mask all interrupt sources. | ||
83 | */ | ||
84 | REG_WRITE(REG_GLOBAL, 0x04, 0x0000); | ||
85 | |||
86 | /* Set the default address aging time to 5 minutes, and | ||
87 | * enable address learn messages to be sent to all message | ||
88 | * ports. | ||
89 | */ | ||
90 | REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); | ||
91 | |||
92 | /* Configure the priority mapping registers. */ | ||
93 | ret = mv88e6xxx_config_prio(ds); | ||
94 | if (ret < 0) | ||
95 | return ret; | ||
96 | |||
97 | /* Configure the upstream port, and configure the upstream | ||
98 | * port as the port to which ingress and egress monitor frames | ||
99 | * are to be sent. | ||
100 | */ | ||
101 | if (REG_READ(REG_PORT(0), 0x03) == 0x1710) | ||
102 | REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1111)); | ||
103 | else | ||
104 | REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); | ||
105 | |||
106 | /* Disable remote management for now, and set the switch's | ||
107 | * DSA device number. | ||
108 | */ | ||
109 | REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); | ||
110 | |||
111 | /* Send all frames with destination addresses matching | ||
112 | * 01:80:c2:00:00:2x to the CPU port. | ||
113 | */ | ||
114 | REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); | ||
115 | |||
116 | /* Send all frames with destination addresses matching | ||
117 | * 01:80:c2:00:00:0x to the CPU port. | ||
118 | */ | ||
119 | REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); | ||
120 | |||
121 | /* Disable the loopback filter, disable flow control | ||
122 | * messages, disable flood broadcast override, disable | ||
123 | * removing of provider tags, disable ATU age violation | ||
124 | * interrupts, disable tag flow control, force flow | ||
125 | * control priority to the highest, and send all special | ||
126 | * multicast frames to the CPU at the highest priority. | ||
127 | */ | ||
128 | REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); | ||
129 | |||
130 | /* Program the DSA routing table. */ | ||
131 | for (i = 0; i < 32; i++) { | ||
132 | int nexthop; | ||
133 | |||
134 | nexthop = 0x1f; | ||
135 | if (i != ds->index && i < ds->dst->pd->nr_chips) | ||
136 | nexthop = ds->pd->rtable[i] & 0x1f; | ||
137 | |||
138 | REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); | ||
139 | } | ||
140 | |||
141 | /* Clear all trunk masks. */ | ||
142 | for (i = 0; i < 8; i++) | ||
143 | REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff); | ||
144 | |||
145 | /* Clear all trunk mappings. */ | ||
146 | for (i = 0; i < 16; i++) | ||
147 | REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); | ||
148 | |||
149 | /* Disable ingress rate limiting by resetting all ingress | ||
150 | * rate limit registers to their initial state. | ||
151 | */ | ||
152 | for (i = 0; i < 6; i++) | ||
153 | REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8)); | ||
154 | |||
155 | /* Initialise cross-chip port VLAN table to reset defaults. */ | ||
156 | REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000); | ||
157 | |||
158 | /* Clear the priority override table. */ | ||
159 | for (i = 0; i < 16; i++) | ||
160 | REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8)); | ||
161 | |||
162 | /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */ | ||
163 | |||
164 | return 0; | ||
165 | } | ||
166 | |||
167 | static int mv88e6171_setup_port(struct dsa_switch *ds, int p) | ||
168 | { | ||
169 | int addr = REG_PORT(p); | ||
170 | u16 val; | ||
171 | |||
172 | /* MAC Forcing register: don't force link, speed, duplex | ||
173 | * or flow control state to any particular values on physical | ||
174 | * ports, but force the CPU port and all DSA ports to 1000 Mb/s | ||
175 | * full duplex. | ||
176 | */ | ||
177 | val = REG_READ(addr, 0x01); | ||
178 | if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p)) | ||
179 | REG_WRITE(addr, 0x01, val | 0x003e); | ||
180 | else | ||
181 | REG_WRITE(addr, 0x01, val | 0x0003); | ||
182 | |||
183 | /* Do not limit the period of time that this port can be | ||
184 | * paused for by the remote end or the period of time that | ||
185 | * this port can pause the remote end. | ||
186 | */ | ||
187 | REG_WRITE(addr, 0x02, 0x0000); | ||
188 | |||
189 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | ||
190 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | ||
191 | * tunneling, determine priority by looking at 802.1p and IP | ||
192 | * priority fields (IP prio has precedence), and set STP state | ||
193 | * to Forwarding. | ||
194 | * | ||
195 | * If this is the CPU link, use DSA or EDSA tagging depending | ||
196 | * on which tagging mode was configured. | ||
197 | * | ||
198 | * If this is a link to another switch, use DSA tagging mode. | ||
199 | * | ||
200 | * If this is the upstream port for this switch, enable | ||
201 | * forwarding of unknown unicasts and multicasts. | ||
202 | */ | ||
203 | val = 0x0433; | ||
204 | if (dsa_is_cpu_port(ds, p)) { | ||
205 | if (ds->dst->tag_protocol == htons(ETH_P_EDSA)) | ||
206 | val |= 0x3300; | ||
207 | else | ||
208 | val |= 0x0100; | ||
209 | } | ||
210 | if (ds->dsa_port_mask & (1 << p)) | ||
211 | val |= 0x0100; | ||
212 | if (p == dsa_upstream_port(ds)) | ||
213 | val |= 0x000c; | ||
214 | REG_WRITE(addr, 0x04, val); | ||
215 | |||
216 | /* Port Control 1: disable trunking. Also, if this is the | ||
217 | * CPU port, enable learn messages to be sent to this port. | ||
218 | */ | ||
219 | REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000); | ||
220 | |||
221 | /* Port based VLAN map: give each port its own address | ||
222 | * database, allow the CPU port to talk to each of the 'real' | ||
223 | * ports, and allow each of the 'real' ports to only talk to | ||
224 | * the upstream port. | ||
225 | */ | ||
226 | val = (p & 0xf) << 12; | ||
227 | if (dsa_is_cpu_port(ds, p)) | ||
228 | val |= ds->phys_port_mask; | ||
229 | else | ||
230 | val |= 1 << dsa_upstream_port(ds); | ||
231 | REG_WRITE(addr, 0x06, val); | ||
232 | |||
233 | /* Default VLAN ID and priority: don't set a default VLAN | ||
234 | * ID, and set the default packet priority to zero. | ||
235 | */ | ||
236 | REG_WRITE(addr, 0x07, 0x0000); | ||
237 | |||
238 | /* Port Control 2: don't force a good FCS, set the maximum | ||
239 | * frame size to 10240 bytes, don't let the switch add or | ||
240 | * strip 802.1q tags, don't discard tagged or untagged frames | ||
241 | * on this port, do a destination address lookup on all | ||
242 | * received packets as usual, disable ARP mirroring and don't | ||
243 | * send a copy of all transmitted/received frames on this port | ||
244 | * to the CPU. | ||
245 | */ | ||
246 | REG_WRITE(addr, 0x08, 0x2080); | ||
247 | |||
248 | /* Egress rate control: disable egress rate control. */ | ||
249 | REG_WRITE(addr, 0x09, 0x0001); | ||
250 | |||
251 | /* Egress rate control 2: disable egress rate control. */ | ||
252 | REG_WRITE(addr, 0x0a, 0x0000); | ||
253 | |||
254 | /* Port Association Vector: when learning source addresses | ||
255 | * of packets, add the address to the address database using | ||
256 | * a port bitmap that has only the bit for this port set and | ||
257 | * the other bits clear. | ||
258 | */ | ||
259 | REG_WRITE(addr, 0x0b, 1 << p); | ||
260 | |||
261 | /* Port ATU control: disable limiting the number of address | ||
262 | * database entries that this port is allowed to use. | ||
263 | */ | ||
264 | REG_WRITE(addr, 0x0c, 0x0000); | ||
265 | |||
266 | /* Priority Override: disable DA, SA and VTU priority override. */ | ||
267 | REG_WRITE(addr, 0x0d, 0x0000); | ||
268 | |||
269 | /* Port Ethertype: use the Ethertype DSA Ethertype value. */ | ||
270 | REG_WRITE(addr, 0x0f, ETH_P_EDSA); | ||
271 | |||
272 | /* Tag Remap: use an identity 802.1p prio -> switch prio | ||
273 | * mapping. | ||
274 | */ | ||
275 | REG_WRITE(addr, 0x18, 0x3210); | ||
276 | |||
277 | /* Tag Remap 2: use an identity 802.1p prio -> switch prio | ||
278 | * mapping. | ||
279 | */ | ||
280 | REG_WRITE(addr, 0x19, 0x7654); | ||
281 | |||
282 | return 0; | ||
283 | } | ||
284 | |||
285 | static int mv88e6171_setup(struct dsa_switch *ds) | ||
286 | { | ||
287 | struct mv88e6xxx_priv_state *ps = (void *)(ds + 1); | ||
288 | int i; | ||
289 | int ret; | ||
290 | |||
291 | mutex_init(&ps->smi_mutex); | ||
292 | mutex_init(&ps->stats_mutex); | ||
293 | |||
294 | ret = mv88e6171_switch_reset(ds); | ||
295 | if (ret < 0) | ||
296 | return ret; | ||
297 | |||
298 | /* @@@ initialise vtu and atu */ | ||
299 | |||
300 | ret = mv88e6171_setup_global(ds); | ||
301 | if (ret < 0) | ||
302 | return ret; | ||
303 | |||
304 | for (i = 0; i < 8; i++) { | ||
305 | if (!(dsa_is_cpu_port(ds, i) || ds->phys_port_mask & (1 << i))) | ||
306 | continue; | ||
307 | |||
308 | ret = mv88e6171_setup_port(ds, i); | ||
309 | if (ret < 0) | ||
310 | return ret; | ||
311 | } | ||
312 | |||
313 | return 0; | ||
314 | } | ||
315 | |||
316 | static int mv88e6171_port_to_phy_addr(int port) | ||
317 | { | ||
318 | if (port >= 0 && port <= 4) | ||
319 | return port; | ||
320 | return -1; | ||
321 | } | ||
322 | |||
323 | static int | ||
324 | mv88e6171_phy_read(struct dsa_switch *ds, int port, int regnum) | ||
325 | { | ||
326 | int addr = mv88e6171_port_to_phy_addr(port); | ||
327 | |||
328 | return mv88e6xxx_phy_read(ds, addr, regnum); | ||
329 | } | ||
330 | |||
331 | static int | ||
332 | mv88e6171_phy_write(struct dsa_switch *ds, | ||
333 | int port, int regnum, u16 val) | ||
334 | { | ||
335 | int addr = mv88e6171_port_to_phy_addr(port); | ||
336 | |||
337 | return mv88e6xxx_phy_write(ds, addr, regnum, val); | ||
338 | } | ||
339 | |||
340 | static struct mv88e6xxx_hw_stat mv88e6171_hw_stats[] = { | ||
341 | { "in_good_octets", 8, 0x00, }, | ||
342 | { "in_bad_octets", 4, 0x02, }, | ||
343 | { "in_unicast", 4, 0x04, }, | ||
344 | { "in_broadcasts", 4, 0x06, }, | ||
345 | { "in_multicasts", 4, 0x07, }, | ||
346 | { "in_pause", 4, 0x16, }, | ||
347 | { "in_undersize", 4, 0x18, }, | ||
348 | { "in_fragments", 4, 0x19, }, | ||
349 | { "in_oversize", 4, 0x1a, }, | ||
350 | { "in_jabber", 4, 0x1b, }, | ||
351 | { "in_rx_error", 4, 0x1c, }, | ||
352 | { "in_fcs_error", 4, 0x1d, }, | ||
353 | { "out_octets", 8, 0x0e, }, | ||
354 | { "out_unicast", 4, 0x10, }, | ||
355 | { "out_broadcasts", 4, 0x13, }, | ||
356 | { "out_multicasts", 4, 0x12, }, | ||
357 | { "out_pause", 4, 0x15, }, | ||
358 | { "excessive", 4, 0x11, }, | ||
359 | { "collisions", 4, 0x1e, }, | ||
360 | { "deferred", 4, 0x05, }, | ||
361 | { "single", 4, 0x14, }, | ||
362 | { "multiple", 4, 0x17, }, | ||
363 | { "out_fcs_error", 4, 0x03, }, | ||
364 | { "late", 4, 0x1f, }, | ||
365 | { "hist_64bytes", 4, 0x08, }, | ||
366 | { "hist_65_127bytes", 4, 0x09, }, | ||
367 | { "hist_128_255bytes", 4, 0x0a, }, | ||
368 | { "hist_256_511bytes", 4, 0x0b, }, | ||
369 | { "hist_512_1023bytes", 4, 0x0c, }, | ||
370 | { "hist_1024_max_bytes", 4, 0x0d, }, | ||
371 | }; | ||
372 | |||
373 | static void | ||
374 | mv88e6171_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | ||
375 | { | ||
376 | mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6171_hw_stats), | ||
377 | mv88e6171_hw_stats, port, data); | ||
378 | } | ||
379 | |||
380 | static void | ||
381 | mv88e6171_get_ethtool_stats(struct dsa_switch *ds, | ||
382 | int port, uint64_t *data) | ||
383 | { | ||
384 | mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6171_hw_stats), | ||
385 | mv88e6171_hw_stats, port, data); | ||
386 | } | ||
387 | |||
388 | static int mv88e6171_get_sset_count(struct dsa_switch *ds) | ||
389 | { | ||
390 | return ARRAY_SIZE(mv88e6171_hw_stats); | ||
391 | } | ||
392 | |||
393 | struct dsa_switch_driver mv88e6171_switch_driver = { | ||
394 | .tag_protocol = DSA_TAG_PROTO_DSA, | ||
395 | .priv_size = sizeof(struct mv88e6xxx_priv_state), | ||
396 | .probe = mv88e6171_probe, | ||
397 | .setup = mv88e6171_setup, | ||
398 | .set_addr = mv88e6xxx_set_addr_indirect, | ||
399 | .phy_read = mv88e6171_phy_read, | ||
400 | .phy_write = mv88e6171_phy_write, | ||
401 | .poll_link = mv88e6xxx_poll_link, | ||
402 | .get_strings = mv88e6171_get_strings, | ||
403 | .get_ethtool_stats = mv88e6171_get_ethtool_stats, | ||
404 | .get_sset_count = mv88e6171_get_sset_count, | ||
405 | }; | ||
406 | |||
407 | MODULE_ALIAS("platform:mv88e6171"); | ||
diff --git a/drivers/net/dsa/mv88e6xxx.c b/drivers/net/dsa/mv88e6xxx.c index 9ce2146346b6..901d2a9704ef 100644 --- a/drivers/net/dsa/mv88e6xxx.c +++ b/drivers/net/dsa/mv88e6xxx.c | |||
@@ -501,12 +501,18 @@ static int __init mv88e6xxx_init(void) | |||
501 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) | 501 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) |
502 | register_switch_driver(&mv88e6123_61_65_switch_driver); | 502 | register_switch_driver(&mv88e6123_61_65_switch_driver); |
503 | #endif | 503 | #endif |
504 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) | ||
505 | register_switch_driver(&mv88e6171_switch_driver); | ||
506 | #endif | ||
504 | return 0; | 507 | return 0; |
505 | } | 508 | } |
506 | module_init(mv88e6xxx_init); | 509 | module_init(mv88e6xxx_init); |
507 | 510 | ||
508 | static void __exit mv88e6xxx_cleanup(void) | 511 | static void __exit mv88e6xxx_cleanup(void) |
509 | { | 512 | { |
513 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) | ||
514 | unregister_switch_driver(&mv88e6171_switch_driver); | ||
515 | #endif | ||
510 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) | 516 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) |
511 | unregister_switch_driver(&mv88e6123_61_65_switch_driver); | 517 | unregister_switch_driver(&mv88e6123_61_65_switch_driver); |
512 | #endif | 518 | #endif |
diff --git a/drivers/net/dsa/mv88e6xxx.h b/drivers/net/dsa/mv88e6xxx.h index 911ede58dd12..5e5145ad9525 100644 --- a/drivers/net/dsa/mv88e6xxx.h +++ b/drivers/net/dsa/mv88e6xxx.h | |||
@@ -70,6 +70,7 @@ void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, | |||
70 | 70 | ||
71 | extern struct dsa_switch_driver mv88e6131_switch_driver; | 71 | extern struct dsa_switch_driver mv88e6131_switch_driver; |
72 | extern struct dsa_switch_driver mv88e6123_61_65_switch_driver; | 72 | extern struct dsa_switch_driver mv88e6123_61_65_switch_driver; |
73 | extern struct dsa_switch_driver mv88e6171_switch_driver; | ||
73 | 74 | ||
74 | #define REG_READ(addr, reg) \ | 75 | #define REG_READ(addr, reg) \ |
75 | ({ \ | 76 | ({ \ |