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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /drivers/net/davinci_emac.c
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/net/davinci_emac.c')
-rw-r--r--drivers/net/davinci_emac.c157
1 files changed, 105 insertions, 52 deletions
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index e3478314c002..2b8edd2efbf6 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -29,10 +29,6 @@
29 * PHY layer usage 29 * PHY layer usage
30 */ 30 */
31 31
32/** Pending Items in this driver:
33 * 1. Use Linux cache infrastcture for DMA'ed memory (dma_xxx functions)
34 */
35
36#include <linux/module.h> 32#include <linux/module.h>
37#include <linux/kernel.h> 33#include <linux/kernel.h>
38#include <linux/sched.h> 34#include <linux/sched.h>
@@ -62,12 +58,11 @@
62#include <linux/bitops.h> 58#include <linux/bitops.h>
63#include <linux/io.h> 59#include <linux/io.h>
64#include <linux/uaccess.h> 60#include <linux/uaccess.h>
61#include <linux/davinci_emac.h>
65 62
66#include <asm/irq.h> 63#include <asm/irq.h>
67#include <asm/page.h> 64#include <asm/page.h>
68 65
69#include <mach/emac.h>
70
71static int debug_level; 66static int debug_level;
72module_param(debug_level, int, 0); 67module_param(debug_level, int, 0);
73MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)"); 68MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
@@ -465,6 +460,7 @@ struct emac_priv {
465 void __iomem *ctrl_base; 460 void __iomem *ctrl_base;
466 void __iomem *emac_ctrl_ram; 461 void __iomem *emac_ctrl_ram;
467 u32 ctrl_ram_size; 462 u32 ctrl_ram_size;
463 u32 hw_ram_addr;
468 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH]; 464 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
469 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH]; 465 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
470 u32 link; /* 1=link on, 0=link off */ 466 u32 link; /* 1=link on, 0=link off */
@@ -488,6 +484,9 @@ struct emac_priv {
488 struct mii_bus *mii_bus; 484 struct mii_bus *mii_bus;
489 struct phy_device *phydev; 485 struct phy_device *phydev;
490 spinlock_t lock; 486 spinlock_t lock;
487 /*platform specific members*/
488 void (*int_enable) (void);
489 void (*int_disable) (void);
491}; 490};
492 491
493/* clock frequency for EMAC */ 492/* clock frequency for EMAC */
@@ -495,20 +494,12 @@ static struct clk *emac_clk;
495static unsigned long emac_bus_frequency; 494static unsigned long emac_bus_frequency;
496static unsigned long mdio_max_freq; 495static unsigned long mdio_max_freq;
497 496
498/* EMAC internal utility function */ 497#define emac_virt_to_phys(addr, priv) \
499static inline u32 emac_virt_to_phys(void __iomem *addr) 498 (((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \
500{ 499 + priv->hw_ram_addr)
501 return (u32 __force) io_v2p(addr);
502}
503 500
504/* Cache macros - Packet buffers would be from skb pool which is cached */ 501/* Cache macros - Packet buffers would be from skb pool which is cached */
505#define EMAC_VIRT_NOCACHE(addr) (addr) 502#define EMAC_VIRT_NOCACHE(addr) (addr)
506#define EMAC_CACHE_INVALIDATE(addr, size) \
507 dma_cache_maint((void *)addr, size, DMA_FROM_DEVICE)
508#define EMAC_CACHE_WRITEBACK(addr, size) \
509 dma_cache_maint((void *)addr, size, DMA_TO_DEVICE)
510#define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
511 dma_cache_maint((void *)addr, size, DMA_BIDIRECTIONAL)
512 503
513/* DM644x does not have BD's in cached memory - so no cache functions */ 504/* DM644x does not have BD's in cached memory - so no cache functions */
514#define BD_CACHE_INVALIDATE(addr, size) 505#define BD_CACHE_INVALIDATE(addr, size)
@@ -956,19 +947,18 @@ static void emac_dev_mcast_set(struct net_device *ndev)
956 } else { 947 } else {
957 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC); 948 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
958 if ((ndev->flags & IFF_ALLMULTI) || 949 if ((ndev->flags & IFF_ALLMULTI) ||
959 (ndev->mc_count > EMAC_DEF_MAX_MULTICAST_ADDRESSES)) { 950 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
960 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 951 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
961 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL); 952 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
962 } 953 }
963 if (ndev->mc_count > 0) { 954 if (!netdev_mc_empty(ndev)) {
964 struct dev_mc_list *mc_ptr; 955 struct dev_mc_list *mc_ptr;
965 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 956 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
966 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); 957 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
967 /* program multicast address list into EMAC hardware */ 958 /* program multicast address list into EMAC hardware */
968 for (mc_ptr = ndev->mc_list; mc_ptr; 959 netdev_for_each_mc_addr(mc_ptr, ndev) {
969 mc_ptr = mc_ptr->next) {
970 emac_add_mcast(priv, EMAC_MULTICAST_ADD, 960 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
971 (u8 *)mc_ptr->dmi_addr); 961 (u8 *) mc_ptr->dmi_addr);
972 } 962 }
973 } else { 963 } else {
974 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST); 964 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
@@ -1002,6 +992,8 @@ static void emac_int_disable(struct emac_priv *priv)
1002 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); 992 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
1003 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); 993 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
1004 /* NOTE: Rx Threshold and Misc interrupts are not disabled */ 994 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
995 if (priv->int_disable)
996 priv->int_disable();
1005 997
1006 local_irq_restore(flags); 998 local_irq_restore(flags);
1007 999
@@ -1021,6 +1013,9 @@ static void emac_int_disable(struct emac_priv *priv)
1021static void emac_int_enable(struct emac_priv *priv) 1013static void emac_int_enable(struct emac_priv *priv)
1022{ 1014{
1023 if (priv->version == EMAC_VERSION_2) { 1015 if (priv->version == EMAC_VERSION_2) {
1016 if (priv->int_enable)
1017 priv->int_enable();
1018
1024 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); 1019 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
1025 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); 1020 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
1026 1021
@@ -1230,6 +1225,10 @@ static void emac_txch_teardown(struct emac_priv *priv, u32 ch)
1230 if (1 == txch->queue_active) { 1225 if (1 == txch->queue_active) {
1231 curr_bd = txch->active_queue_head; 1226 curr_bd = txch->active_queue_head;
1232 while (curr_bd != NULL) { 1227 while (curr_bd != NULL) {
1228 dma_unmap_single(emac_dev, curr_bd->buff_ptr,
1229 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
1230 DMA_TO_DEVICE);
1231
1233 emac_net_tx_complete(priv, (void __force *) 1232 emac_net_tx_complete(priv, (void __force *)
1234 &curr_bd->buf_token, 1, ch); 1233 &curr_bd->buf_token, 1, ch);
1235 if (curr_bd != txch->active_queue_tail) 1234 if (curr_bd != txch->active_queue_tail)
@@ -1302,7 +1301,7 @@ static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1302 curr_bd = txch->active_queue_head; 1301 curr_bd = txch->active_queue_head;
1303 if (NULL == curr_bd) { 1302 if (NULL == curr_bd) {
1304 emac_write(EMAC_TXCP(ch), 1303 emac_write(EMAC_TXCP(ch),
1305 emac_virt_to_phys(txch->last_hw_bdprocessed)); 1304 emac_virt_to_phys(txch->last_hw_bdprocessed, priv));
1306 txch->no_active_pkts++; 1305 txch->no_active_pkts++;
1307 spin_unlock_irqrestore(&priv->tx_lock, flags); 1306 spin_unlock_irqrestore(&priv->tx_lock, flags);
1308 return 0; 1307 return 0;
@@ -1312,7 +1311,7 @@ static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1312 while ((curr_bd) && 1311 while ((curr_bd) &&
1313 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && 1312 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1314 (pkts_processed < budget)) { 1313 (pkts_processed < budget)) {
1315 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd)); 1314 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd, priv));
1316 txch->active_queue_head = curr_bd->next; 1315 txch->active_queue_head = curr_bd->next;
1317 if (frame_status & EMAC_CPPI_EOQ_BIT) { 1316 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1318 if (curr_bd->next) { /* misqueued packet */ 1317 if (curr_bd->next) { /* misqueued packet */
@@ -1322,6 +1321,11 @@ static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1322 txch->queue_active = 0; /* end of queue */ 1321 txch->queue_active = 0; /* end of queue */
1323 } 1322 }
1324 } 1323 }
1324
1325 dma_unmap_single(emac_dev, curr_bd->buff_ptr,
1326 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
1327 DMA_TO_DEVICE);
1328
1325 *tx_complete_ptr = (u32) curr_bd->buf_token; 1329 *tx_complete_ptr = (u32) curr_bd->buf_token;
1326 ++tx_complete_ptr; 1330 ++tx_complete_ptr;
1327 ++tx_complete_cnt; 1331 ++tx_complete_cnt;
@@ -1382,8 +1386,8 @@ static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1382 1386
1383 txch->bd_pool_head = curr_bd->next; 1387 txch->bd_pool_head = curr_bd->next;
1384 curr_bd->buf_token = buf_list->buf_token; 1388 curr_bd->buf_token = buf_list->buf_token;
1385 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */ 1389 curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buf_list->data_ptr,
1386 curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr); 1390 buf_list->length, DMA_TO_DEVICE);
1387 curr_bd->off_b_len = buf_list->length; 1391 curr_bd->off_b_len = buf_list->length;
1388 curr_bd->h_next = 0; 1392 curr_bd->h_next = 0;
1389 curr_bd->next = NULL; 1393 curr_bd->next = NULL;
@@ -1399,7 +1403,7 @@ static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1399 txch->active_queue_tail = curr_bd; 1403 txch->active_queue_tail = curr_bd;
1400 if (1 != txch->queue_active) { 1404 if (1 != txch->queue_active) {
1401 emac_write(EMAC_TXHDP(ch), 1405 emac_write(EMAC_TXHDP(ch),
1402 emac_virt_to_phys(curr_bd)); 1406 emac_virt_to_phys(curr_bd, priv));
1403 txch->queue_active = 1; 1407 txch->queue_active = 1;
1404 } 1408 }
1405 ++txch->queue_reinit; 1409 ++txch->queue_reinit;
@@ -1411,10 +1415,11 @@ static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1411 tail_bd->next = curr_bd; 1415 tail_bd->next = curr_bd;
1412 txch->active_queue_tail = curr_bd; 1416 txch->active_queue_tail = curr_bd;
1413 tail_bd = EMAC_VIRT_NOCACHE(tail_bd); 1417 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1414 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd); 1418 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd, priv);
1415 frame_status = tail_bd->mode; 1419 frame_status = tail_bd->mode;
1416 if (frame_status & EMAC_CPPI_EOQ_BIT) { 1420 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1417 emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd)); 1421 emac_write(EMAC_TXHDP(ch),
1422 emac_virt_to_phys(curr_bd, priv));
1418 frame_status &= ~(EMAC_CPPI_EOQ_BIT); 1423 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1419 tail_bd->mode = frame_status; 1424 tail_bd->mode = frame_status;
1420 ++txch->end_of_queue_add; 1425 ++txch->end_of_queue_add;
@@ -1462,7 +1467,6 @@ static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1462 tx_buf.length = skb->len; 1467 tx_buf.length = skb->len;
1463 tx_buf.buf_token = (void *)skb; 1468 tx_buf.buf_token = (void *)skb;
1464 tx_buf.data_ptr = skb->data; 1469 tx_buf.data_ptr = skb->data;
1465 EMAC_CACHE_WRITEBACK((unsigned long)skb->data, skb->len);
1466 ndev->trans_start = jiffies; 1470 ndev->trans_start = jiffies;
1467 ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH); 1471 ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
1468 if (unlikely(ret_code != 0)) { 1472 if (unlikely(ret_code != 0)) {
@@ -1537,7 +1541,6 @@ static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
1537 p_skb->dev = ndev; 1541 p_skb->dev = ndev;
1538 skb_reserve(p_skb, NET_IP_ALIGN); 1542 skb_reserve(p_skb, NET_IP_ALIGN);
1539 *data_token = (void *) p_skb; 1543 *data_token = (void *) p_skb;
1540 EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p_skb->data, buf_size);
1541 return p_skb->data; 1544 return p_skb->data;
1542} 1545}
1543 1546
@@ -1604,9 +1607,10 @@ static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param)
1604 } 1607 }
1605 1608
1606 /* populate the hardware descriptor */ 1609 /* populate the hardware descriptor */
1607 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head); 1610 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head,
1608 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */ 1611 priv);
1609 curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr); 1612 curr_bd->buff_ptr = dma_map_single(emac_dev, curr_bd->data_ptr,
1613 rxch->buf_size, DMA_FROM_DEVICE);
1610 curr_bd->off_b_len = rxch->buf_size; 1614 curr_bd->off_b_len = rxch->buf_size;
1611 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; 1615 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1612 1616
@@ -1690,6 +1694,12 @@ static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch)
1690 curr_bd = rxch->active_queue_head; 1694 curr_bd = rxch->active_queue_head;
1691 while (curr_bd) { 1695 while (curr_bd) {
1692 if (curr_bd->buf_token) { 1696 if (curr_bd->buf_token) {
1697 dma_unmap_single(&priv->ndev->dev,
1698 curr_bd->buff_ptr,
1699 curr_bd->off_b_len
1700 & EMAC_RX_BD_BUF_SIZE,
1701 DMA_FROM_DEVICE);
1702
1693 dev_kfree_skb_any((struct sk_buff *)\ 1703 dev_kfree_skb_any((struct sk_buff *)\
1694 curr_bd->buf_token); 1704 curr_bd->buf_token);
1695 } 1705 }
@@ -1864,8 +1874,8 @@ static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1864 1874
1865 /* populate the hardware descriptor */ 1875 /* populate the hardware descriptor */
1866 curr_bd->h_next = 0; 1876 curr_bd->h_next = 0;
1867 /* FIXME buff_ptr = dma_map_single(... buffer ...) */ 1877 curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buffer,
1868 curr_bd->buff_ptr = virt_to_phys(buffer); 1878 rxch->buf_size, DMA_FROM_DEVICE);
1869 curr_bd->off_b_len = rxch->buf_size; 1879 curr_bd->off_b_len = rxch->buf_size;
1870 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; 1880 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1871 curr_bd->next = NULL; 1881 curr_bd->next = NULL;
@@ -1879,7 +1889,7 @@ static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1879 rxch->active_queue_tail = curr_bd; 1889 rxch->active_queue_tail = curr_bd;
1880 if (0 != rxch->queue_active) { 1890 if (0 != rxch->queue_active) {
1881 emac_write(EMAC_RXHDP(ch), 1891 emac_write(EMAC_RXHDP(ch),
1882 emac_virt_to_phys(rxch->active_queue_head)); 1892 emac_virt_to_phys(rxch->active_queue_head, priv));
1883 rxch->queue_active = 1; 1893 rxch->queue_active = 1;
1884 } 1894 }
1885 } else { 1895 } else {
@@ -1890,11 +1900,11 @@ static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1890 rxch->active_queue_tail = curr_bd; 1900 rxch->active_queue_tail = curr_bd;
1891 tail_bd->next = curr_bd; 1901 tail_bd->next = curr_bd;
1892 tail_bd = EMAC_VIRT_NOCACHE(tail_bd); 1902 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1893 tail_bd->h_next = emac_virt_to_phys(curr_bd); 1903 tail_bd->h_next = emac_virt_to_phys(curr_bd, priv);
1894 frame_status = tail_bd->mode; 1904 frame_status = tail_bd->mode;
1895 if (frame_status & EMAC_CPPI_EOQ_BIT) { 1905 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1896 emac_write(EMAC_RXHDP(ch), 1906 emac_write(EMAC_RXHDP(ch),
1897 emac_virt_to_phys(curr_bd)); 1907 emac_virt_to_phys(curr_bd, priv));
1898 frame_status &= ~(EMAC_CPPI_EOQ_BIT); 1908 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1899 tail_bd->mode = frame_status; 1909 tail_bd->mode = frame_status;
1900 ++rxch->end_of_queue_add; 1910 ++rxch->end_of_queue_add;
@@ -1920,7 +1930,6 @@ static int emac_net_rx_cb(struct emac_priv *priv,
1920 p_skb = (struct sk_buff *)net_pkt_list->pkt_token; 1930 p_skb = (struct sk_buff *)net_pkt_list->pkt_token;
1921 /* set length of packet */ 1931 /* set length of packet */
1922 skb_put(p_skb, net_pkt_list->pkt_length); 1932 skb_put(p_skb, net_pkt_list->pkt_length);
1923 EMAC_CACHE_INVALIDATE((unsigned long)p_skb->data, p_skb->len);
1924 p_skb->protocol = eth_type_trans(p_skb, priv->ndev); 1933 p_skb->protocol = eth_type_trans(p_skb, priv->ndev);
1925 netif_receive_skb(p_skb); 1934 netif_receive_skb(p_skb);
1926 priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length; 1935 priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length;
@@ -1983,11 +1992,16 @@ static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1983 rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr; 1992 rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
1984 rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE; 1993 rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
1985 rx_buf_obj->buf_token = curr_bd->buf_token; 1994 rx_buf_obj->buf_token = curr_bd->buf_token;
1995
1996 dma_unmap_single(&priv->ndev->dev, curr_bd->buff_ptr,
1997 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
1998 DMA_FROM_DEVICE);
1999
1986 curr_pkt->pkt_token = curr_pkt->buf_list->buf_token; 2000 curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
1987 curr_pkt->num_bufs = 1; 2001 curr_pkt->num_bufs = 1;
1988 curr_pkt->pkt_length = 2002 curr_pkt->pkt_length =
1989 (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK); 2003 (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
1990 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd)); 2004 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd, priv));
1991 ++rxch->processed_bd; 2005 ++rxch->processed_bd;
1992 last_bd = curr_bd; 2006 last_bd = curr_bd;
1993 curr_bd = last_bd->next; 2007 curr_bd = last_bd->next;
@@ -1998,7 +2012,7 @@ static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1998 if (curr_bd) { 2012 if (curr_bd) {
1999 ++rxch->mis_queued_packets; 2013 ++rxch->mis_queued_packets;
2000 emac_write(EMAC_RXHDP(ch), 2014 emac_write(EMAC_RXHDP(ch),
2001 emac_virt_to_phys(curr_bd)); 2015 emac_virt_to_phys(curr_bd, priv));
2002 } else { 2016 } else {
2003 ++rxch->end_of_queue; 2017 ++rxch->end_of_queue;
2004 rxch->queue_active = 0; 2018 rxch->queue_active = 0;
@@ -2099,7 +2113,7 @@ static int emac_hw_enable(struct emac_priv *priv)
2099 emac_write(EMAC_RXINTMASKSET, BIT(ch)); 2113 emac_write(EMAC_RXINTMASKSET, BIT(ch));
2100 rxch->queue_active = 1; 2114 rxch->queue_active = 1;
2101 emac_write(EMAC_RXHDP(ch), 2115 emac_write(EMAC_RXHDP(ch),
2102 emac_virt_to_phys(rxch->active_queue_head)); 2116 emac_virt_to_phys(rxch->active_queue_head, priv));
2103 } 2117 }
2104 2118
2105 /* Enable MII */ 2119 /* Enable MII */
@@ -2272,7 +2286,7 @@ static int emac_mii_reset(struct mii_bus *bus)
2272 unsigned int clk_div; 2286 unsigned int clk_div;
2273 int mdio_bus_freq = emac_bus_frequency; 2287 int mdio_bus_freq = emac_bus_frequency;
2274 2288
2275 if (mdio_max_freq & mdio_bus_freq) 2289 if (mdio_max_freq && mdio_bus_freq)
2276 clk_div = ((mdio_bus_freq / mdio_max_freq) - 1); 2290 clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
2277 else 2291 else
2278 clk_div = 0xFF; 2292 clk_div = 0xFF;
@@ -2378,7 +2392,7 @@ static int emac_dev_open(struct net_device *ndev)
2378 struct emac_priv *priv = netdev_priv(ndev); 2392 struct emac_priv *priv = netdev_priv(ndev);
2379 2393
2380 netif_carrier_off(ndev); 2394 netif_carrier_off(ndev);
2381 for (cnt = 0; cnt <= ETH_ALEN; cnt++) 2395 for (cnt = 0; cnt < ETH_ALEN; cnt++)
2382 ndev->dev_addr[cnt] = priv->mac_addr[cnt]; 2396 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
2383 2397
2384 /* Configuration items */ 2398 /* Configuration items */
@@ -2651,7 +2665,7 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2651 2665
2652 pdata = pdev->dev.platform_data; 2666 pdata = pdev->dev.platform_data;
2653 if (!pdata) { 2667 if (!pdata) {
2654 printk(KERN_ERR "DaVinci EMAC: No platfrom data\n"); 2668 printk(KERN_ERR "DaVinci EMAC: No platform data\n");
2655 return -ENODEV; 2669 return -ENODEV;
2656 } 2670 }
2657 2671
@@ -2660,6 +2674,9 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2660 priv->phy_mask = pdata->phy_mask; 2674 priv->phy_mask = pdata->phy_mask;
2661 priv->rmii_en = pdata->rmii_en; 2675 priv->rmii_en = pdata->rmii_en;
2662 priv->version = pdata->version; 2676 priv->version = pdata->version;
2677 priv->int_enable = pdata->interrupt_enable;
2678 priv->int_disable = pdata->interrupt_disable;
2679
2663 emac_dev = &ndev->dev; 2680 emac_dev = &ndev->dev;
2664 /* Get EMAC platform data */ 2681 /* Get EMAC platform data */
2665 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2682 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -2672,8 +2689,7 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2672 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset; 2689 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
2673 size = res->end - res->start + 1; 2690 size = res->end - res->start + 1;
2674 if (!request_mem_region(res->start, size, ndev->name)) { 2691 if (!request_mem_region(res->start, size, ndev->name)) {
2675 dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() \ 2692 dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() for regs\n");
2676 for regs\n");
2677 rc = -ENXIO; 2693 rc = -ENXIO;
2678 goto probe_quit; 2694 goto probe_quit;
2679 } 2695 }
@@ -2692,6 +2708,12 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2692 priv->ctrl_ram_size = pdata->ctrl_ram_size; 2708 priv->ctrl_ram_size = pdata->ctrl_ram_size;
2693 priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset; 2709 priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
2694 2710
2711 if (pdata->hw_ram_addr)
2712 priv->hw_ram_addr = pdata->hw_ram_addr;
2713 else
2714 priv->hw_ram_addr = (u32 __force)res->start +
2715 pdata->ctrl_ram_offset;
2716
2695 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 2717 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2696 if (!res) { 2718 if (!res) {
2697 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n"); 2719 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n");
@@ -2711,6 +2733,8 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2711 SET_ETHTOOL_OPS(ndev, &ethtool_ops); 2733 SET_ETHTOOL_OPS(ndev, &ethtool_ops);
2712 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT); 2734 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2713 2735
2736 clk_enable(emac_clk);
2737
2714 /* register the network device */ 2738 /* register the network device */
2715 SET_NETDEV_DEV(ndev, &pdev->dev); 2739 SET_NETDEV_DEV(ndev, &pdev->dev);
2716 rc = register_netdev(ndev); 2740 rc = register_netdev(ndev);
@@ -2720,7 +2744,6 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2720 goto netdev_reg_err; 2744 goto netdev_reg_err;
2721 } 2745 }
2722 2746
2723 clk_enable(emac_clk);
2724 2747
2725 /* MII/Phy intialisation, mdio bus registration */ 2748 /* MII/Phy intialisation, mdio bus registration */
2726 emac_mii = mdiobus_alloc(); 2749 emac_mii = mdiobus_alloc();
@@ -2760,6 +2783,7 @@ mdiobus_quit:
2760 2783
2761netdev_reg_err: 2784netdev_reg_err:
2762mdio_alloc_err: 2785mdio_alloc_err:
2786 clk_disable(emac_clk);
2763no_irq_res: 2787no_irq_res:
2764 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2788 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2765 release_mem_region(res->start, res->end - res->start + 1); 2789 release_mem_region(res->start, res->end - res->start + 1);
@@ -2803,16 +2827,45 @@ static int __devexit davinci_emac_remove(struct platform_device *pdev)
2803 return 0; 2827 return 0;
2804} 2828}
2805 2829
2830static int davinci_emac_suspend(struct device *dev)
2831{
2832 struct platform_device *pdev = to_platform_device(dev);
2833 struct net_device *ndev = platform_get_drvdata(pdev);
2834
2835 if (netif_running(ndev))
2836 emac_dev_stop(ndev);
2837
2838 clk_disable(emac_clk);
2839
2840 return 0;
2841}
2842
2843static int davinci_emac_resume(struct device *dev)
2844{
2845 struct platform_device *pdev = to_platform_device(dev);
2846 struct net_device *ndev = platform_get_drvdata(pdev);
2847
2848 clk_enable(emac_clk);
2849
2850 if (netif_running(ndev))
2851 emac_dev_open(ndev);
2852
2853 return 0;
2854}
2855
2856static const struct dev_pm_ops davinci_emac_pm_ops = {
2857 .suspend = davinci_emac_suspend,
2858 .resume = davinci_emac_resume,
2859};
2860
2806/** 2861/**
2807 * davinci_emac_driver: EMAC platform driver structure 2862 * davinci_emac_driver: EMAC platform driver structure
2808 *
2809 * We implement only probe and remove functions - suspend/resume and
2810 * others not supported by this module
2811 */ 2863 */
2812static struct platform_driver davinci_emac_driver = { 2864static struct platform_driver davinci_emac_driver = {
2813 .driver = { 2865 .driver = {
2814 .name = "davinci_emac", 2866 .name = "davinci_emac",
2815 .owner = THIS_MODULE, 2867 .owner = THIS_MODULE,
2868 .pm = &davinci_emac_pm_ops,
2816 }, 2869 },
2817 .probe = davinci_emac_probe, 2870 .probe = davinci_emac_probe,
2818 .remove = __devexit_p(davinci_emac_remove), 2871 .remove = __devexit_p(davinci_emac_remove),