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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /drivers/net/cxgb3/mc5.c
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'drivers/net/cxgb3/mc5.c')
-rw-r--r--drivers/net/cxgb3/mc5.c40
1 files changed, 1 insertions, 39 deletions
diff --git a/drivers/net/cxgb3/mc5.c b/drivers/net/cxgb3/mc5.c
index 3b5517b8fbde..e13b7fe9d082 100644
--- a/drivers/net/cxgb3/mc5.c
+++ b/drivers/net/cxgb3/mc5.c
@@ -318,7 +318,7 @@ static void mc5_dbgi_mode_disable(const struct mc5 *mc5)
318 318
319/* 319/*
320 * Initialization that requires the OS and protocol layers to already 320 * Initialization that requires the OS and protocol layers to already
321 * be intialized goes here. 321 * be initialized goes here.
322 */ 322 */
323int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 323int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
324 unsigned int nroutes) 324 unsigned int nroutes)
@@ -374,44 +374,6 @@ int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
374 return err; 374 return err;
375} 375}
376 376
377/*
378 * read_mc5_range - dump a part of the memory managed by MC5
379 * @mc5: the MC5 handle
380 * @start: the start address for the dump
381 * @n: number of 72-bit words to read
382 * @buf: result buffer
383 *
384 * Read n 72-bit words from MC5 memory from the given start location.
385 */
386int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start,
387 unsigned int n, u32 *buf)
388{
389 u32 read_cmd;
390 int err = 0;
391 struct adapter *adap = mc5->adapter;
392
393 if (mc5->part_type == IDT75P52100)
394 read_cmd = IDT_CMD_READ;
395 else if (mc5->part_type == IDT75N43102)
396 read_cmd = IDT4_CMD_READ;
397 else
398 return -EINVAL;
399
400 mc5_dbgi_mode_enable(mc5);
401
402 while (n--) {
403 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR0, start++);
404 if (mc5_cmd_write(adap, read_cmd)) {
405 err = -EIO;
406 break;
407 }
408 dbgi_rd_rsp3(adap, buf + 2, buf + 1, buf);
409 buf += 3;
410 }
411
412 mc5_dbgi_mode_disable(mc5);
413 return 0;
414}
415 377
416#define MC5_INT_FATAL (F_PARITYERR | F_REQQPARERR | F_DISPQPARERR) 378#define MC5_INT_FATAL (F_PARITYERR | F_REQQPARERR | F_DISPQPARERR)
417 379