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authorDivy Le Ray <divy@chelsio.com>2007-05-31 00:10:58 -0400
committerJeff Garzik <jeff@garzik.org>2007-07-08 22:16:39 -0400
commit480fe1a31c662ef4ff0598a7cacefa21f98335f1 (patch)
tree66da8f259d7093d7f9290054f4fbda1f68ff9e0a /drivers/net/cxgb3/common.h
parent8a9fab22cf6a3abde7731f4425d4ff87509bc15a (diff)
cxgb3 - TP SRAM update
The chip executes microcode present in internal RAM, whose content is loaded from EEPROM on power cycle. This patch allows an update of the microcode through PIO without forcing a power cycle. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/cxgb3/common.h')
-rw-r--r--drivers/net/cxgb3/common.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/net/cxgb3/common.h b/drivers/net/cxgb3/common.h
index 8d1379633698..16378004507a 100644
--- a/drivers/net/cxgb3/common.h
+++ b/drivers/net/cxgb3/common.h
@@ -101,6 +101,7 @@ enum {
101 TCB_SIZE = 128, /* TCB size */ 101 TCB_SIZE = 128, /* TCB size */
102 NMTUS = 16, /* size of MTU table */ 102 NMTUS = 16, /* size of MTU table */
103 NCCTRL_WIN = 32, /* # of congestion control windows */ 103 NCCTRL_WIN = 32, /* # of congestion control windows */
104 PROTO_SRAM_LINES = 128, /* size of TP sram */
104}; 105};
105 106
106#define MAX_RX_COALESCING_LEN 16224U 107#define MAX_RX_COALESCING_LEN 16224U
@@ -124,6 +125,30 @@ enum { /* adapter interrupt-maintained statistics */
124}; 125};
125 126
126enum { 127enum {
128 TP_VERSION_MAJOR = 1,
129 TP_VERSION_MINOR = 0,
130 TP_VERSION_MICRO = 44
131};
132
133#define S_TP_VERSION_MAJOR 16
134#define M_TP_VERSION_MAJOR 0xFF
135#define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR)
136#define G_TP_VERSION_MAJOR(x) \
137 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
138
139#define S_TP_VERSION_MINOR 8
140#define M_TP_VERSION_MINOR 0xFF
141#define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR)
142#define G_TP_VERSION_MINOR(x) \
143 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
144
145#define S_TP_VERSION_MICRO 0
146#define M_TP_VERSION_MICRO 0xFF
147#define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO)
148#define G_TP_VERSION_MICRO(x) \
149 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
150
151enum {
127 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 152 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
128 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 153 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
129 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 154 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
@@ -654,6 +679,9 @@ const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
654int t3_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 679int t3_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
655int t3_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 680int t3_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
656int t3_seeprom_wp(struct adapter *adapter, int enable); 681int t3_seeprom_wp(struct adapter *adapter, int enable);
682int t3_check_tpsram_version(struct adapter *adapter);
683int t3_check_tpsram(struct adapter *adapter, u8 *tp_ram, unsigned int size);
684int t3_set_proto_sram(struct adapter *adap, u8 *data);
657int t3_read_flash(struct adapter *adapter, unsigned int addr, 685int t3_read_flash(struct adapter *adapter, unsigned int addr,
658 unsigned int nwords, u32 *data, int byte_oriented); 686 unsigned int nwords, u32 *data, int byte_oriented);
659int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size); 687int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size);