diff options
author | Tomoya <tomoya-linux@dsn.okisemi.com> | 2010-11-29 13:19:52 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-12-02 16:13:46 -0500 |
commit | 2989042ca86b94bf4ffa9486921bb300ad44225f (patch) | |
tree | 3f7c6abad513d04528d754eab78b876dd6087695 /drivers/net/can | |
parent | d68f6837c4972b0433e41f8bee4b2b8205610f31 (diff) |
can: EG20T PCH: Delete unnecessary spin_lock
Delete unnecessary spin_lock for accessing Message Object.
Since all message objects are divided into tx/rx area completely,
spin_lock processing is unnecessary.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/can')
-rw-r--r-- | drivers/net/can/pch_can.c | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c index 2d4ab0fc9184..a9b6a6525a65 100644 --- a/drivers/net/can/pch_can.c +++ b/drivers/net/can/pch_can.c | |||
@@ -71,7 +71,6 @@ | |||
71 | #define PCH_REC 0x00007f00 | 71 | #define PCH_REC 0x00007f00 |
72 | #define PCH_TEC 0x000000ff | 72 | #define PCH_TEC 0x000000ff |
73 | 73 | ||
74 | |||
75 | #define PCH_TX_OK BIT(3) | 74 | #define PCH_TX_OK BIT(3) |
76 | #define PCH_RX_OK BIT(4) | 75 | #define PCH_RX_OK BIT(4) |
77 | #define PCH_EPASSIV BIT(5) | 76 | #define PCH_EPASSIV BIT(5) |
@@ -178,7 +177,6 @@ struct pch_can_priv { | |||
178 | unsigned int int_enables; | 177 | unsigned int int_enables; |
179 | unsigned int int_stat; | 178 | unsigned int int_stat; |
180 | struct net_device *ndev; | 179 | struct net_device *ndev; |
181 | spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/ | ||
182 | unsigned int msg_obj[PCH_TX_OBJ_END]; | 180 | unsigned int msg_obj[PCH_TX_OBJ_END]; |
183 | struct pch_can_regs __iomem *regs; | 181 | struct pch_can_regs __iomem *regs; |
184 | struct napi_struct napi; | 182 | struct napi_struct napi; |
@@ -309,7 +307,6 @@ static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num) | |||
309 | static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, | 307 | static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, |
310 | u32 set, enum pch_ifreg dir) | 308 | u32 set, enum pch_ifreg dir) |
311 | { | 309 | { |
312 | unsigned long flags; | ||
313 | u32 ie; | 310 | u32 ie; |
314 | 311 | ||
315 | if (dir) | 312 | if (dir) |
@@ -317,7 +314,6 @@ static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, | |||
317 | else | 314 | else |
318 | ie = PCH_IF_MCONT_RXIE; | 315 | ie = PCH_IF_MCONT_RXIE; |
319 | 316 | ||
320 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | ||
321 | /* Reading the receive buffer data from RAM to Interface1 registers */ | 317 | /* Reading the receive buffer data from RAM to Interface1 registers */ |
322 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); | 318 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); |
323 | pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); | 319 | pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); |
@@ -338,10 +334,8 @@ static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, | |||
338 | } | 334 | } |
339 | 335 | ||
340 | pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); | 336 | pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); |
341 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | ||
342 | } | 337 | } |
343 | 338 | ||
344 | |||
345 | static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set) | 339 | static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set) |
346 | { | 340 | { |
347 | int i; | 341 | int i; |
@@ -363,7 +357,6 @@ static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set) | |||
363 | static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, | 357 | static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, |
364 | enum pch_ifreg dir) | 358 | enum pch_ifreg dir) |
365 | { | 359 | { |
366 | unsigned long flags; | ||
367 | u32 ie, enable; | 360 | u32 ie, enable; |
368 | 361 | ||
369 | if (dir) | 362 | if (dir) |
@@ -371,7 +364,6 @@ static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, | |||
371 | else | 364 | else |
372 | ie = PCH_IF_MCONT_TXIE; | 365 | ie = PCH_IF_MCONT_TXIE; |
373 | 366 | ||
374 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | ||
375 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); | 367 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); |
376 | pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); | 368 | pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); |
377 | 369 | ||
@@ -381,7 +373,6 @@ static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, | |||
381 | } else { | 373 | } else { |
382 | enable = 0; | 374 | enable = 0; |
383 | } | 375 | } |
384 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | ||
385 | return enable; | 376 | return enable; |
386 | } | 377 | } |
387 | 378 | ||
@@ -393,9 +384,6 @@ static int pch_can_int_pending(struct pch_can_priv *priv) | |||
393 | static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, | 384 | static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, |
394 | u32 buffer_num, u32 set) | 385 | u32 buffer_num, u32 set) |
395 | { | 386 | { |
396 | unsigned long flags; | ||
397 | |||
398 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | ||
399 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); | 387 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); |
400 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); | 388 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); |
401 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, | 389 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, |
@@ -407,15 +395,11 @@ static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, | |||
407 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); | 395 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); |
408 | 396 | ||
409 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); | 397 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); |
410 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | ||
411 | } | 398 | } |
412 | 399 | ||
413 | static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv, | 400 | static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv, |
414 | u32 buffer_num, u32 *link) | 401 | u32 buffer_num, u32 *link) |
415 | { | 402 | { |
416 | unsigned long flags; | ||
417 | |||
418 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | ||
419 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); | 403 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); |
420 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); | 404 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); |
421 | 405 | ||
@@ -423,7 +407,6 @@ static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv, | |||
423 | *link = PCH_DISABLE; | 407 | *link = PCH_DISABLE; |
424 | else | 408 | else |
425 | *link = PCH_ENABLE; | 409 | *link = PCH_ENABLE; |
426 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | ||
427 | } | 410 | } |
428 | 411 | ||
429 | static void pch_can_clear_buffers(struct pch_can_priv *priv) | 412 | static void pch_can_clear_buffers(struct pch_can_priv *priv) |
@@ -468,9 +451,6 @@ static void pch_can_clear_buffers(struct pch_can_priv *priv) | |||
468 | static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) | 451 | static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) |
469 | { | 452 | { |
470 | int i; | 453 | int i; |
471 | unsigned long flags; | ||
472 | |||
473 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | ||
474 | 454 | ||
475 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { | 455 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
476 | iowrite32(PCH_CMASK_RX_TX_GET, | 456 | iowrite32(PCH_CMASK_RX_TX_GET, |
@@ -529,7 +509,6 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) | |||
529 | 509 | ||
530 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); | 510 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); |
531 | } | 511 | } |
532 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | ||
533 | } | 512 | } |
534 | 513 | ||
535 | static void pch_can_init(struct pch_can_priv *priv) | 514 | static void pch_can_init(struct pch_can_priv *priv) |
@@ -845,7 +824,6 @@ static int pch_can_rx_poll(struct napi_struct *napi, int quota) | |||
845 | u32 int_stat; | 824 | u32 int_stat; |
846 | int rcv_pkts = 0; | 825 | int rcv_pkts = 0; |
847 | u32 reg_stat; | 826 | u32 reg_stat; |
848 | unsigned long flags; | ||
849 | 827 | ||
850 | int_stat = pch_can_int_pending(priv); | 828 | int_stat = pch_can_int_pending(priv); |
851 | if (!int_stat) | 829 | if (!int_stat) |
@@ -860,12 +838,10 @@ INT_STAT: | |||
860 | } | 838 | } |
861 | 839 | ||
862 | if (reg_stat & PCH_TX_OK) { | 840 | if (reg_stat & PCH_TX_OK) { |
863 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | ||
864 | iowrite32(PCH_CMASK_RX_TX_GET, | 841 | iowrite32(PCH_CMASK_RX_TX_GET, |
865 | &priv->regs->ifregs[1].cmask); | 842 | &priv->regs->ifregs[1].cmask); |
866 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, | 843 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, |
867 | ioread32(&priv->regs->intr)); | 844 | ioread32(&priv->regs->intr)); |
868 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | ||
869 | pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK); | 845 | pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK); |
870 | } | 846 | } |
871 | 847 | ||
@@ -879,22 +855,18 @@ INT_STAT: | |||
879 | 855 | ||
880 | MSG_OBJ: | 856 | MSG_OBJ: |
881 | if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) { | 857 | if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) { |
882 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | ||
883 | rcv_pkts = pch_can_rx_normal(ndev, int_stat); | 858 | rcv_pkts = pch_can_rx_normal(ndev, int_stat); |
884 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | ||
885 | if (rcv_pkts < 0) | 859 | if (rcv_pkts < 0) |
886 | return 0; | 860 | return 0; |
887 | } else if ((int_stat >= PCH_TX_OBJ_START) && | 861 | } else if ((int_stat >= PCH_TX_OBJ_START) && |
888 | (int_stat <= PCH_TX_OBJ_END)) { | 862 | (int_stat <= PCH_TX_OBJ_END)) { |
889 | /* Handle transmission interrupt */ | 863 | /* Handle transmission interrupt */ |
890 | can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1); | 864 | can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1); |
891 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | ||
892 | iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND, | 865 | iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND, |
893 | &priv->regs->ifregs[1].cmask); | 866 | &priv->regs->ifregs[1].cmask); |
894 | dlc = ioread32(&priv->regs->ifregs[1].mcont) & | 867 | dlc = ioread32(&priv->regs->ifregs[1].mcont) & |
895 | PCH_IF_MCONT_DLC; | 868 | PCH_IF_MCONT_DLC; |
896 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat); | 869 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat); |
897 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | ||
898 | if (dlc > 8) | 870 | if (dlc > 8) |
899 | dlc = 8; | 871 | dlc = 8; |
900 | stats->tx_bytes += dlc; | 872 | stats->tx_bytes += dlc; |
@@ -1052,7 +1024,6 @@ static int pch_get_msg_obj_sts(struct net_device *ndev, u32 obj_id) | |||
1052 | static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) | 1024 | static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) |
1053 | { | 1025 | { |
1054 | int i, j; | 1026 | int i, j; |
1055 | unsigned long flags; | ||
1056 | struct pch_can_priv *priv = netdev_priv(ndev); | 1027 | struct pch_can_priv *priv = netdev_priv(ndev); |
1057 | struct can_frame *cf = (struct can_frame *)skb->data; | 1028 | struct can_frame *cf = (struct can_frame *)skb->data; |
1058 | int tx_buffer_avail = 0; | 1029 | int tx_buffer_avail = 0; |
@@ -1072,9 +1043,6 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) | |||
1072 | } | 1043 | } |
1073 | priv->tx_obj++; | 1044 | priv->tx_obj++; |
1074 | 1045 | ||
1075 | /* Attaining the lock. */ | ||
1076 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | ||
1077 | |||
1078 | /* Reading the Msg Obj from the Msg RAM to the Interface register. */ | 1046 | /* Reading the Msg Obj from the Msg RAM to the Interface register. */ |
1079 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); | 1047 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); |
1080 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); | 1048 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); |
@@ -1126,8 +1094,6 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) | |||
1126 | 1094 | ||
1127 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); | 1095 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); |
1128 | 1096 | ||
1129 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | ||
1130 | |||
1131 | return NETDEV_TX_OK; | 1097 | return NETDEV_TX_OK; |
1132 | } | 1098 | } |
1133 | 1099 | ||