diff options
author | Yaniv Rosner <yanivr@broadcom.com> | 2009-11-05 12:18:12 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-11-05 23:00:35 -0500 |
commit | 15ddd2d0ef4849410a2251587b3652fe6a689fda (patch) | |
tree | 4964565c9e2f4bf350cc2774f29424c17028eac6 /drivers/net/bnx2x_reg.h | |
parent | d5cb9e997708bd48d2ed3dd926dad7a6fc83bf56 (diff) |
bnx2x: Enable FC when parallel-detect is used
When parallel detect is used, flow-control is set to the
req_fc_auto_adv instead of none.
Motive: when 577xx is FC configuration is set to AUTO, while LP speed
is set to FORCE mode and FC to force RX/TX, link would come up using
parallel detect, and the FC will be set to NONE since FC capabilities
were not negotiated, although the LP is setting FC to force RX/TX.
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_reg.h')
-rw-r--r-- | drivers/net/bnx2x_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h index b80fde44c85d..4be9bab42f5c 100644 --- a/drivers/net/bnx2x_reg.h +++ b/drivers/net/bnx2x_reg.h | |||
@@ -4920,6 +4920,8 @@ | |||
4920 | 4920 | ||
4921 | 4921 | ||
4922 | #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 | 4922 | #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 |
4923 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 | ||
4924 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000 | ||
4923 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 | 4925 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 |
4924 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 | 4926 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 |
4925 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 | 4927 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 |
@@ -4944,6 +4946,8 @@ | |||
4944 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 | 4946 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 |
4945 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 | 4947 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 |
4946 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 | 4948 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 |
4949 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15 | ||
4950 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002 | ||
4947 | #define MDIO_SERDES_DIGITAL_MISC1 0x18 | 4951 | #define MDIO_SERDES_DIGITAL_MISC1 0x18 |
4948 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 | 4952 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 |
4949 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 | 4953 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 |