diff options
author | Eilon Greenstein <eilong@broadcom.com> | 2009-08-12 04:23:53 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-08-13 02:02:54 -0400 |
commit | 57937203aa077520a7e1665bfb7071b3cbb3f5a9 (patch) | |
tree | 373911f3591808e5b7641cb57ffc2a516af7f053 /drivers/net/bnx2x_link.c | |
parent | 6f65497b567ef9a518d930ef30fe6b8f27051688 (diff) |
bnx2x: Remove SGMII configuration when not required
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_link.c')
-rw-r--r-- | drivers/net/bnx2x_link.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c index b81a05737d48..c163c42bc1fe 100644 --- a/drivers/net/bnx2x_link.c +++ b/drivers/net/bnx2x_link.c | |||
@@ -1276,14 +1276,14 @@ static void bnx2x_program_serdes(struct link_params *params, | |||
1276 | struct bnx2x *bp = params->bp; | 1276 | struct bnx2x *bp = params->bp; |
1277 | u16 reg_val; | 1277 | u16 reg_val; |
1278 | 1278 | ||
1279 | /* program duplex, disable autoneg */ | 1279 | /* program duplex, disable autoneg and sgmii*/ |
1280 | |||
1281 | CL45_RD_OVER_CL22(bp, params->port, | 1280 | CL45_RD_OVER_CL22(bp, params->port, |
1282 | params->phy_addr, | 1281 | params->phy_addr, |
1283 | MDIO_REG_BANK_COMBO_IEEE0, | 1282 | MDIO_REG_BANK_COMBO_IEEE0, |
1284 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | 1283 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); |
1285 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | | 1284 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | |
1286 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN); | 1285 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
1286 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); | ||
1287 | if (params->req_duplex == DUPLEX_FULL) | 1287 | if (params->req_duplex == DUPLEX_FULL) |
1288 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; | 1288 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; |
1289 | CL45_WR_OVER_CL22(bp, params->port, | 1289 | CL45_WR_OVER_CL22(bp, params->port, |
@@ -5271,6 +5271,13 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, | |||
5271 | ext_phy_link_up = 0; | 5271 | ext_phy_link_up = 0; |
5272 | break; | 5272 | break; |
5273 | } | 5273 | } |
5274 | /* Set SGMII mode for external phy */ | ||
5275 | if (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { | ||
5276 | if (vars->line_speed < SPEED_1000) | ||
5277 | vars->phy_flags |= PHY_SGMII_FLAG; | ||
5278 | else | ||
5279 | vars->phy_flags &= ~PHY_SGMII_FLAG; | ||
5280 | } | ||
5274 | 5281 | ||
5275 | } else { /* SerDes */ | 5282 | } else { /* SerDes */ |
5276 | ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config); | 5283 | ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config); |