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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /drivers/net/bnx2x_link.c
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/net/bnx2x_link.c')
-rw-r--r--drivers/net/bnx2x_link.c342
1 files changed, 212 insertions, 130 deletions
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index e32d3370862e..32e79c359e89 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -14,6 +14,8 @@
14 * 14 *
15 */ 15 */
16 16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
17#include <linux/kernel.h> 19#include <linux/kernel.h>
18#include <linux/errno.h> 20#include <linux/errno.h>
19#include <linux/pci.h> 21#include <linux/pci.h>
@@ -1107,18 +1109,21 @@ static void bnx2x_set_parallel_detection(struct link_params *params,
1107 MDIO_REG_BANK_SERDES_DIGITAL, 1109 MDIO_REG_BANK_SERDES_DIGITAL,
1108 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 1110 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1109 &control2); 1111 &control2);
1110 1112 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1111 1113 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1112 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 1114 else
1113 1115 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1114 1116 DP(NETIF_MSG_LINK, "params->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1117 params->speed_cap_mask, control2);
1115 CL45_WR_OVER_CL22(bp, params->port, 1118 CL45_WR_OVER_CL22(bp, params->port,
1116 params->phy_addr, 1119 params->phy_addr,
1117 MDIO_REG_BANK_SERDES_DIGITAL, 1120 MDIO_REG_BANK_SERDES_DIGITAL,
1118 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 1121 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1119 control2); 1122 control2);
1120 1123
1121 if (phy_flags & PHY_XGXS_FLAG) { 1124 if ((phy_flags & PHY_XGXS_FLAG) &&
1125 (params->speed_cap_mask &
1126 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
1122 DP(NETIF_MSG_LINK, "XGXS\n"); 1127 DP(NETIF_MSG_LINK, "XGXS\n");
1123 1128
1124 CL45_WR_OVER_CL22(bp, params->port, 1129 CL45_WR_OVER_CL22(bp, params->port,
@@ -1225,7 +1230,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
1225 params->phy_addr, 1230 params->phy_addr,
1226 MDIO_REG_BANK_CL73_USERB0, 1231 MDIO_REG_BANK_CL73_USERB0,
1227 MDIO_CL73_USERB0_CL73_UCTRL, 1232 MDIO_CL73_USERB0_CL73_UCTRL,
1228 MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL); 1233 0xe);
1229 1234
1230 /* Enable BAM Station Manager*/ 1235 /* Enable BAM Station Manager*/
1231 CL45_WR_OVER_CL22(bp, params->port, 1236 CL45_WR_OVER_CL22(bp, params->port,
@@ -1236,29 +1241,25 @@ static void bnx2x_set_autoneg(struct link_params *params,
1236 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 1241 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1237 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 1242 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1238 1243
1239 /* Merge CL73 and CL37 aneg resolution */ 1244 /* Advertise CL73 link speeds */
1240 CL45_RD_OVER_CL22(bp, params->port,
1241 params->phy_addr,
1242 MDIO_REG_BANK_CL73_USERB0,
1243 MDIO_CL73_USERB0_CL73_BAM_CTRL3,
1244 &reg_val);
1245
1246 if (params->speed_cap_mask &
1247 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
1248 /* Set the CL73 AN speed */
1249 CL45_RD_OVER_CL22(bp, params->port, 1245 CL45_RD_OVER_CL22(bp, params->port,
1250 params->phy_addr, 1246 params->phy_addr,
1251 MDIO_REG_BANK_CL73_IEEEB1, 1247 MDIO_REG_BANK_CL73_IEEEB1,
1252 MDIO_CL73_IEEEB1_AN_ADV2, 1248 MDIO_CL73_IEEEB1_AN_ADV2,
1253 &reg_val); 1249 &reg_val);
1250 if (params->speed_cap_mask &
1251 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1252 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
1253 if (params->speed_cap_mask &
1254 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1255 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
1254 1256
1255 CL45_WR_OVER_CL22(bp, params->port, 1257 CL45_WR_OVER_CL22(bp, params->port,
1256 params->phy_addr, 1258 params->phy_addr,
1257 MDIO_REG_BANK_CL73_IEEEB1, 1259 MDIO_REG_BANK_CL73_IEEEB1,
1258 MDIO_CL73_IEEEB1_AN_ADV2, 1260 MDIO_CL73_IEEEB1_AN_ADV2,
1259 reg_val | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4); 1261 reg_val);
1260 1262
1261 }
1262 /* CL73 Autoneg Enabled */ 1263 /* CL73 Autoneg Enabled */
1263 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 1264 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
1264 1265
@@ -1351,6 +1352,7 @@ static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
1351 1352
1352static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u16 *ieee_fc) 1353static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u16 *ieee_fc)
1353{ 1354{
1355 struct bnx2x *bp = params->bp;
1354 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 1356 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1355 /* resolve pause mode and advertisement 1357 /* resolve pause mode and advertisement
1356 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */ 1358 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
@@ -1380,18 +1382,30 @@ static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u16 *ieee_fc)
1380 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 1382 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
1381 break; 1383 break;
1382 } 1384 }
1385 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
1383} 1386}
1384 1387
1385static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params, 1388static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
1386 u16 ieee_fc) 1389 u16 ieee_fc)
1387{ 1390{
1388 struct bnx2x *bp = params->bp; 1391 struct bnx2x *bp = params->bp;
1392 u16 val;
1389 /* for AN, we are always publishing full duplex */ 1393 /* for AN, we are always publishing full duplex */
1390 1394
1391 CL45_WR_OVER_CL22(bp, params->port, 1395 CL45_WR_OVER_CL22(bp, params->port,
1392 params->phy_addr, 1396 params->phy_addr,
1393 MDIO_REG_BANK_COMBO_IEEE0, 1397 MDIO_REG_BANK_COMBO_IEEE0,
1394 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 1398 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
1399 CL45_RD_OVER_CL22(bp, params->port,
1400 params->phy_addr,
1401 MDIO_REG_BANK_CL73_IEEEB1,
1402 MDIO_CL73_IEEEB1_AN_ADV1, &val);
1403 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
1404 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
1405 CL45_WR_OVER_CL22(bp, params->port,
1406 params->phy_addr,
1407 MDIO_REG_BANK_CL73_IEEEB1,
1408 MDIO_CL73_IEEEB1_AN_ADV1, val);
1395} 1409}
1396 1410
1397static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73) 1411static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73)
@@ -1609,6 +1623,39 @@ static u8 bnx2x_ext_phy_resolve_fc(struct link_params *params,
1609 return ret; 1623 return ret;
1610} 1624}
1611 1625
1626static u8 bnx2x_direct_parallel_detect_used(struct link_params *params)
1627{
1628 struct bnx2x *bp = params->bp;
1629 u16 pd_10g, status2_1000x;
1630 CL45_RD_OVER_CL22(bp, params->port,
1631 params->phy_addr,
1632 MDIO_REG_BANK_SERDES_DIGITAL,
1633 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1634 &status2_1000x);
1635 CL45_RD_OVER_CL22(bp, params->port,
1636 params->phy_addr,
1637 MDIO_REG_BANK_SERDES_DIGITAL,
1638 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1639 &status2_1000x);
1640 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
1641 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
1642 params->port);
1643 return 1;
1644 }
1645
1646 CL45_RD_OVER_CL22(bp, params->port,
1647 params->phy_addr,
1648 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1649 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
1650 &pd_10g);
1651
1652 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
1653 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
1654 params->port);
1655 return 1;
1656 }
1657 return 0;
1658}
1612 1659
1613static void bnx2x_flow_ctrl_resolve(struct link_params *params, 1660static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1614 struct link_vars *vars, 1661 struct link_vars *vars,
@@ -1627,21 +1674,53 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1627 (!(vars->phy_flags & PHY_SGMII_FLAG)) && 1674 (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
1628 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1675 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1629 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) { 1676 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1630 CL45_RD_OVER_CL22(bp, params->port, 1677 if (bnx2x_direct_parallel_detect_used(params)) {
1631 params->phy_addr, 1678 vars->flow_ctrl = params->req_fc_auto_adv;
1632 MDIO_REG_BANK_COMBO_IEEE0, 1679 return;
1633 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 1680 }
1634 &ld_pause); 1681 if ((gp_status &
1635 CL45_RD_OVER_CL22(bp, params->port, 1682 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1636 params->phy_addr, 1683 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
1637 MDIO_REG_BANK_COMBO_IEEE0, 1684 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1638 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 1685 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
1639 &lp_pause); 1686
1640 pause_result = (ld_pause & 1687 CL45_RD_OVER_CL22(bp, params->port,
1688 params->phy_addr,
1689 MDIO_REG_BANK_CL73_IEEEB1,
1690 MDIO_CL73_IEEEB1_AN_ADV1,
1691 &ld_pause);
1692 CL45_RD_OVER_CL22(bp, params->port,
1693 params->phy_addr,
1694 MDIO_REG_BANK_CL73_IEEEB1,
1695 MDIO_CL73_IEEEB1_AN_LP_ADV1,
1696 &lp_pause);
1697 pause_result = (ld_pause &
1698 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
1699 >> 8;
1700 pause_result |= (lp_pause &
1701 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
1702 >> 10;
1703 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
1704 pause_result);
1705 } else {
1706
1707 CL45_RD_OVER_CL22(bp, params->port,
1708 params->phy_addr,
1709 MDIO_REG_BANK_COMBO_IEEE0,
1710 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1711 &ld_pause);
1712 CL45_RD_OVER_CL22(bp, params->port,
1713 params->phy_addr,
1714 MDIO_REG_BANK_COMBO_IEEE0,
1715 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1716 &lp_pause);
1717 pause_result = (ld_pause &
1641 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 1718 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1642 pause_result |= (lp_pause & 1719 pause_result |= (lp_pause &
1643 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 1720 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1644 DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result); 1721 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
1722 pause_result);
1723 }
1645 bnx2x_pause_resolve(vars, pause_result); 1724 bnx2x_pause_resolve(vars, pause_result);
1646 } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) && 1725 } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
1647 (bnx2x_ext_phy_resolve_fc(params, vars))) { 1726 (bnx2x_ext_phy_resolve_fc(params, vars))) {
@@ -1853,6 +1932,8 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1853 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1932 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1854 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) || 1933 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
1855 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1934 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1935 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) ||
1936 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1856 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) { 1937 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) {
1857 vars->autoneg = AUTO_NEG_ENABLED; 1938 vars->autoneg = AUTO_NEG_ENABLED;
1858 1939
@@ -1987,8 +2068,7 @@ static u8 bnx2x_emac_program(struct link_params *params,
1987 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 2068 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
1988 mode); 2069 mode);
1989 2070
1990 bnx2x_set_led(bp, params->port, LED_MODE_OPER, 2071 bnx2x_set_led(params, LED_MODE_OPER, line_speed);
1991 line_speed, params->hw_led_mode, params->chip_id);
1992 return 0; 2072 return 0;
1993} 2073}
1994 2074
@@ -2122,6 +2202,8 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
2122 MDIO_PMA_REG_CTRL, 2202 MDIO_PMA_REG_CTRL,
2123 1<<15); 2203 1<<15);
2124 break; 2204 break;
2205 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
2206 break;
2125 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 2207 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
2126 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n"); 2208 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
2127 break; 2209 break;
@@ -2512,16 +2594,11 @@ static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
2512 /* Need to wait 100ms after reset */ 2594 /* Need to wait 100ms after reset */
2513 msleep(100); 2595 msleep(100);
2514 2596
2515 /* Set serial boot control for external load */
2516 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2517 MDIO_PMA_DEVAD,
2518 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2519
2520 /* Micro controller re-boot */ 2597 /* Micro controller re-boot */
2521 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2598 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2522 MDIO_PMA_DEVAD, 2599 MDIO_PMA_DEVAD,
2523 MDIO_PMA_REG_GEN_CTRL, 2600 MDIO_PMA_REG_GEN_CTRL,
2524 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 2601 0x018B);
2525 2602
2526 /* Set soft reset */ 2603 /* Set soft reset */
2527 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2604 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
@@ -2529,14 +2606,10 @@ static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
2529 MDIO_PMA_REG_GEN_CTRL, 2606 MDIO_PMA_REG_GEN_CTRL,
2530 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 2607 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2531 2608
2532 /* Set PLL register value to be same like in P13 ver */
2533 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2609 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2534 MDIO_PMA_DEVAD, 2610 MDIO_PMA_DEVAD,
2535 MDIO_PMA_REG_PLL_CTRL, 2611 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2536 0x73A0);
2537 2612
2538 /* Clear soft reset.
2539 Will automatically reset micro-controller re-boot */
2540 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2613 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2541 MDIO_PMA_DEVAD, 2614 MDIO_PMA_DEVAD,
2542 MDIO_PMA_REG_GEN_CTRL, 2615 MDIO_PMA_REG_GEN_CTRL,
@@ -2916,11 +2989,8 @@ static u8 bnx2x_verify_sfp_module(struct link_params *params)
2916 else 2989 else
2917 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; 2990 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
2918 2991
2919 printk(KERN_INFO PFX "Warning: " 2992 netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected, Port %d from %s part number %s\n",
2920 "Unqualified SFP+ module " 2993 params->port, vendor_name, vendor_pn);
2921 "detected on %s, Port %d from %s part number %s\n"
2922 , bp->dev->name, params->port,
2923 vendor_name, vendor_pn);
2924 return -EINVAL; 2994 return -EINVAL;
2925} 2995}
2926 2996
@@ -3462,8 +3532,8 @@ static void bnx2x_8481_set_10G_led_mode(struct link_params *params,
3462 MDIO_PMA_REG_8481_LINK_SIGNAL, 3532 MDIO_PMA_REG_8481_LINK_SIGNAL,
3463 &val1); 3533 &val1);
3464 /* Set bit 2 to 0, and bits [1:0] to 10 */ 3534 /* Set bit 2 to 0, and bits [1:0] to 10 */
3465 val1 &= ~((1<<0) | (1<<2)); /* Clear bits 0,2*/ 3535 val1 &= ~((1<<0) | (1<<2) | (1<<7)); /* Clear bits 0,2,7*/
3466 val1 |= (1<<1); /* Set bit 1 */ 3536 val1 |= ((1<<1) | (1<<6)); /* Set bit 1, 6 */
3467 3537
3468 bnx2x_cl45_write(bp, params->port, 3538 bnx2x_cl45_write(bp, params->port,
3469 ext_phy_type, 3539 ext_phy_type,
@@ -3497,36 +3567,19 @@ static void bnx2x_8481_set_10G_led_mode(struct link_params *params,
3497 MDIO_PMA_REG_8481_LED2_MASK, 3567 MDIO_PMA_REG_8481_LED2_MASK,
3498 0); 3568 0);
3499 3569
3500 /* LED3 (10G/1G/100/10G Activity) */ 3570 /* Unmask LED3 for 10G link */
3501 bnx2x_cl45_read(bp, params->port,
3502 ext_phy_type,
3503 ext_phy_addr,
3504 MDIO_PMA_DEVAD,
3505 MDIO_PMA_REG_8481_LINK_SIGNAL,
3506 &val1);
3507 /* Enable blink based on source 4(Activity) */
3508 val1 &= ~((1<<7) | (1<<8)); /* Clear bits 7,8 */
3509 val1 |= (1<<6); /* Set only bit 6 */
3510 bnx2x_cl45_write(bp, params->port, 3571 bnx2x_cl45_write(bp, params->port,
3511 ext_phy_type, 3572 ext_phy_type,
3512 ext_phy_addr, 3573 ext_phy_addr,
3513 MDIO_PMA_DEVAD, 3574 MDIO_PMA_DEVAD,
3514 MDIO_PMA_REG_8481_LINK_SIGNAL,
3515 val1);
3516
3517 bnx2x_cl45_read(bp, params->port,
3518 ext_phy_type,
3519 ext_phy_addr,
3520 MDIO_PMA_DEVAD,
3521 MDIO_PMA_REG_8481_LED3_MASK, 3575 MDIO_PMA_REG_8481_LED3_MASK,
3522 &val1); 3576 0x6);
3523 val1 |= (1<<4); /* Unmask LED3 for 10G link */
3524 bnx2x_cl45_write(bp, params->port, 3577 bnx2x_cl45_write(bp, params->port,
3525 ext_phy_type, 3578 ext_phy_type,
3526 ext_phy_addr, 3579 ext_phy_addr,
3527 MDIO_PMA_DEVAD, 3580 MDIO_PMA_DEVAD,
3528 MDIO_PMA_REG_8481_LED3_MASK, 3581 MDIO_PMA_REG_8481_LED3_BLINK,
3529 val1); 3582 0);
3530} 3583}
3531 3584
3532 3585
@@ -3544,7 +3597,10 @@ static void bnx2x_init_internal_phy(struct link_params *params,
3544 bnx2x_set_preemphasis(params); 3597 bnx2x_set_preemphasis(params);
3545 3598
3546 /* forced speed requested? */ 3599 /* forced speed requested? */
3547 if (vars->line_speed != SPEED_AUTO_NEG) { 3600 if (vars->line_speed != SPEED_AUTO_NEG ||
3601 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
3602 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3603 params->loopback_mode == LOOPBACK_EXT)) {
3548 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); 3604 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3549 3605
3550 /* disable autoneg */ 3606 /* disable autoneg */
@@ -3693,19 +3749,6 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3693 } 3749 }
3694 } 3750 }
3695 /* Force speed */ 3751 /* Force speed */
3696 /* First enable LASI */
3697 bnx2x_cl45_write(bp, params->port,
3698 ext_phy_type,
3699 ext_phy_addr,
3700 MDIO_PMA_DEVAD,
3701 MDIO_PMA_REG_RX_ALARM_CTRL,
3702 0x0400);
3703 bnx2x_cl45_write(bp, params->port,
3704 ext_phy_type,
3705 ext_phy_addr,
3706 MDIO_PMA_DEVAD,
3707 MDIO_PMA_REG_LASI_CTRL, 0x0004);
3708
3709 if (params->req_line_speed == SPEED_10000) { 3752 if (params->req_line_speed == SPEED_10000) {
3710 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); 3753 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
3711 3754
@@ -3715,6 +3758,9 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3715 MDIO_PMA_DEVAD, 3758 MDIO_PMA_DEVAD,
3716 MDIO_PMA_REG_DIGITAL_CTRL, 3759 MDIO_PMA_REG_DIGITAL_CTRL,
3717 0x400); 3760 0x400);
3761 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3762 ext_phy_addr, MDIO_PMA_DEVAD,
3763 MDIO_PMA_REG_LASI_CTRL, 1);
3718 } else { 3764 } else {
3719 /* Force 1Gbps using autoneg with 1G 3765 /* Force 1Gbps using autoneg with 1G
3720 advertisment */ 3766 advertisment */
@@ -3756,6 +3802,17 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3756 MDIO_AN_DEVAD, 3802 MDIO_AN_DEVAD,
3757 MDIO_AN_REG_CTRL, 3803 MDIO_AN_REG_CTRL,
3758 0x1200); 3804 0x1200);
3805 bnx2x_cl45_write(bp, params->port,
3806 ext_phy_type,
3807 ext_phy_addr,
3808 MDIO_PMA_DEVAD,
3809 MDIO_PMA_REG_RX_ALARM_CTRL,
3810 0x0400);
3811 bnx2x_cl45_write(bp, params->port,
3812 ext_phy_type,
3813 ext_phy_addr,
3814 MDIO_PMA_DEVAD,
3815 MDIO_PMA_REG_LASI_CTRL, 0x0004);
3759 3816
3760 } 3817 }
3761 bnx2x_save_bcm_spirom_ver(bp, params->port, 3818 bnx2x_save_bcm_spirom_ver(bp, params->port,
@@ -4291,6 +4348,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4291 break; 4348 break;
4292 } 4349 }
4293 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 4350 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
4351 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
4294 /* This phy uses the NIG latch mechanism since link 4352 /* This phy uses the NIG latch mechanism since link
4295 indication arrives through its LED4 and not via 4353 indication arrives through its LED4 and not via
4296 its LASI signal, so we get steady signal 4354 its LASI signal, so we get steady signal
@@ -4298,6 +4356,12 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4298 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 4356 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
4299 1 << NIG_LATCH_BC_ENABLE_MI_INT); 4357 1 << NIG_LATCH_BC_ENABLE_MI_INT);
4300 4358
4359 bnx2x_cl45_write(bp, params->port,
4360 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
4361 ext_phy_addr,
4362 MDIO_PMA_DEVAD,
4363 MDIO_PMA_REG_CTRL, 0x0000);
4364
4301 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr); 4365 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr);
4302 if (params->req_line_speed == SPEED_AUTO_NEG) { 4366 if (params->req_line_speed == SPEED_AUTO_NEG) {
4303 4367
@@ -4394,17 +4458,12 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4394 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) { 4458 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
4395 DP(NETIF_MSG_LINK, "Advertising 10G\n"); 4459 DP(NETIF_MSG_LINK, "Advertising 10G\n");
4396 /* Restart autoneg for 10G*/ 4460 /* Restart autoneg for 10G*/
4397 bnx2x_cl45_read(bp, params->port, 4461
4398 ext_phy_type,
4399 ext_phy_addr,
4400 MDIO_AN_DEVAD,
4401 MDIO_AN_REG_CTRL, &val);
4402 val |= 0x200;
4403 bnx2x_cl45_write(bp, params->port, 4462 bnx2x_cl45_write(bp, params->port,
4404 ext_phy_type, 4463 ext_phy_type,
4405 ext_phy_addr, 4464 ext_phy_addr,
4406 MDIO_AN_DEVAD, 4465 MDIO_AN_DEVAD,
4407 MDIO_AN_REG_CTRL, val); 4466 MDIO_AN_REG_CTRL, 0x3200);
4408 } 4467 }
4409 } else { 4468 } else {
4410 /* Force speed */ 4469 /* Force speed */
@@ -4657,8 +4716,8 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4657 0xc809, &val1); 4716 0xc809, &val1);
4658 4717
4659 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); 4718 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4660 ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) 4719 ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) &&
4661 && ((val1 & (1<<8)) == 0)); 4720 ((val1 & (1<<8)) == 0));
4662 if (ext_phy_link_up) 4721 if (ext_phy_link_up)
4663 vars->line_speed = SPEED_10000; 4722 vars->line_speed = SPEED_10000;
4664 break; 4723 break;
@@ -4786,16 +4845,8 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4786 " has been detected on " 4845 " has been detected on "
4787 "port %d\n", 4846 "port %d\n",
4788 params->port); 4847 params->port);
4789 printk(KERN_ERR PFX "Error: Power" 4848 netdev_err(bp->dev, "Error: Power fault on Port %d has been detected and the power to that SFP+ module has been removed to prevent failure of the card. Please remove the SFP+ module and restart the system to clear this error.\n",
4790 " fault on %s Port %d has" 4849 params->port);
4791 " been detected and the"
4792 " power to that SFP+ module"
4793 " has been removed to prevent"
4794 " failure of the card. Please"
4795 " remove the SFP+ module and"
4796 " restart the system to clear"
4797 " this error.\n"
4798 , bp->dev->name, params->port);
4799 /* 4850 /*
4800 * Disable all RX_ALARMs except for 4851 * Disable all RX_ALARMs except for
4801 * mod_abs 4852 * mod_abs
@@ -5148,6 +5199,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
5148 } 5199 }
5149 break; 5200 break;
5150 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 5201 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
5202 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
5151 /* Check 10G-BaseT link status */ 5203 /* Check 10G-BaseT link status */
5152 /* Check PMD signal ok */ 5204 /* Check PMD signal ok */
5153 bnx2x_cl45_read(bp, params->port, ext_phy_type, 5205 bnx2x_cl45_read(bp, params->port, ext_phy_type,
@@ -5363,8 +5415,10 @@ static void bnx2x_link_int_ack(struct link_params *params,
5363 (NIG_STATUS_XGXS0_LINK10G | 5415 (NIG_STATUS_XGXS0_LINK10G |
5364 NIG_STATUS_XGXS0_LINK_STATUS | 5416 NIG_STATUS_XGXS0_LINK_STATUS |
5365 NIG_STATUS_SERDES0_LINK_STATUS)); 5417 NIG_STATUS_SERDES0_LINK_STATUS));
5366 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) 5418 if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config)
5367 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) { 5419 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) ||
5420 (XGXS_EXT_PHY_TYPE(params->ext_phy_config)
5421 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823)) {
5368 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int); 5422 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int);
5369 } 5423 }
5370 if (vars->phy_link_up) { 5424 if (vars->phy_link_up) {
@@ -5477,6 +5531,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5477 status = bnx2x_format_ver(spirom_ver, version, len); 5531 status = bnx2x_format_ver(spirom_ver, version, len);
5478 break; 5532 break;
5479 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 5533 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
5534 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
5480 spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 | 5535 spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 |
5481 (spirom_ver & 0x7F); 5536 (spirom_ver & 0x7F);
5482 status = bnx2x_format_ver(spirom_ver, version, len); 5537 status = bnx2x_format_ver(spirom_ver, version, len);
@@ -5728,13 +5783,15 @@ u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
5728} 5783}
5729 5784
5730 5785
5731u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed, 5786u8 bnx2x_set_led(struct link_params *params, u8 mode, u32 speed)
5732 u16 hw_led_mode, u32 chip_id)
5733{ 5787{
5788 u8 port = params->port;
5789 u16 hw_led_mode = params->hw_led_mode;
5734 u8 rc = 0; 5790 u8 rc = 0;
5735 u32 tmp; 5791 u32 tmp;
5736 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 5792 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5737 5793 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5794 struct bnx2x *bp = params->bp;
5738 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 5795 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5739 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 5796 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5740 speed, hw_led_mode); 5797 speed, hw_led_mode);
@@ -5749,7 +5806,14 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
5749 break; 5806 break;
5750 5807
5751 case LED_MODE_OPER: 5808 case LED_MODE_OPER:
5752 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode); 5809 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5810 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5811 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5812 } else {
5813 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5814 hw_led_mode);
5815 }
5816
5753 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + 5817 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
5754 port*4, 0); 5818 port*4, 0);
5755 /* Set blinking rate to ~15.9Hz */ 5819 /* Set blinking rate to ~15.9Hz */
@@ -5761,7 +5825,7 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
5761 EMAC_WR(bp, EMAC_REG_EMAC_LED, 5825 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5762 (tmp & (~EMAC_LED_OVERRIDE))); 5826 (tmp & (~EMAC_LED_OVERRIDE)));
5763 5827
5764 if (!CHIP_IS_E1H(bp) && 5828 if (CHIP_IS_E1(bp) &&
5765 ((speed == SPEED_2500) || 5829 ((speed == SPEED_2500) ||
5766 (speed == SPEED_1000) || 5830 (speed == SPEED_1000) ||
5767 (speed == SPEED_100) || 5831 (speed == SPEED_100) ||
@@ -5864,6 +5928,7 @@ static u8 bnx2x_link_initialize(struct link_params *params,
5864 5928
5865 if (non_ext_phy || 5929 if (non_ext_phy ||
5866 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) || 5930 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
5931 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) ||
5867 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) || 5932 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
5868 (params->loopback_mode == LOOPBACK_EXT_PHY)) { 5933 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
5869 if (params->req_line_speed == SPEED_AUTO_NEG) 5934 if (params->req_line_speed == SPEED_AUTO_NEG)
@@ -6030,10 +6095,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
6030 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + 6095 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6031 params->port*4, 0); 6096 params->port*4, 0);
6032 6097
6033 bnx2x_set_led(bp, params->port, LED_MODE_OPER, 6098 bnx2x_set_led(params, LED_MODE_OPER, vars->line_speed);
6034 vars->line_speed, params->hw_led_mode,
6035 params->chip_id);
6036
6037 } else 6099 } else
6038 /* No loopback */ 6100 /* No loopback */
6039 { 6101 {
@@ -6091,15 +6153,13 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6091{ 6153{
6092 struct bnx2x *bp = params->bp; 6154 struct bnx2x *bp = params->bp;
6093 u32 ext_phy_config = params->ext_phy_config; 6155 u32 ext_phy_config = params->ext_phy_config;
6094 u16 hw_led_mode = params->hw_led_mode;
6095 u32 chip_id = params->chip_id;
6096 u8 port = params->port; 6156 u8 port = params->port;
6097 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 6157 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
6098 u32 val = REG_RD(bp, params->shmem_base + 6158 u32 val = REG_RD(bp, params->shmem_base +
6099 offsetof(struct shmem_region, dev_info. 6159 offsetof(struct shmem_region, dev_info.
6100 port_feature_config[params->port]. 6160 port_feature_config[params->port].
6101 config)); 6161 config));
6102 6162 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
6103 /* disable attentions */ 6163 /* disable attentions */
6104 vars->link_status = 0; 6164 vars->link_status = 0;
6105 bnx2x_update_mng(params, vars->link_status); 6165 bnx2x_update_mng(params, vars->link_status);
@@ -6127,7 +6187,7 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6127 * Hold it as vars low 6187 * Hold it as vars low
6128 */ 6188 */
6129 /* clear link led */ 6189 /* clear link led */
6130 bnx2x_set_led(bp, port, LED_MODE_OFF, 0, hw_led_mode, chip_id); 6190 bnx2x_set_led(params, LED_MODE_OFF, 0);
6131 if (reset_ext_phy) { 6191 if (reset_ext_phy) {
6132 switch (ext_phy_type) { 6192 switch (ext_phy_type) {
6133 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 6193 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
@@ -6163,6 +6223,22 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6163 bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr); 6223 bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr);
6164 break; 6224 break;
6165 } 6225 }
6226 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
6227 {
6228 u8 ext_phy_addr =
6229 XGXS_EXT_PHY_ADDR(params->ext_phy_config);
6230 bnx2x_cl45_write(bp, port,
6231 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
6232 ext_phy_addr,
6233 MDIO_AN_DEVAD,
6234 MDIO_AN_REG_CTRL, 0x0000);
6235 bnx2x_cl45_write(bp, port,
6236 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
6237 ext_phy_addr,
6238 MDIO_PMA_DEVAD,
6239 MDIO_PMA_REG_CTRL, 1);
6240 break;
6241 }
6166 default: 6242 default:
6167 /* HW reset */ 6243 /* HW reset */
6168 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6244 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
@@ -6198,9 +6274,7 @@ static u8 bnx2x_update_link_down(struct link_params *params,
6198 u8 port = params->port; 6274 u8 port = params->port;
6199 6275
6200 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); 6276 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6201 bnx2x_set_led(bp, port, LED_MODE_OFF, 6277 bnx2x_set_led(params, LED_MODE_OFF, 0);
6202 0, params->hw_led_mode,
6203 params->chip_id);
6204 6278
6205 /* indicate no mac active */ 6279 /* indicate no mac active */
6206 vars->mac_type = MAC_TYPE_NONE; 6280 vars->mac_type = MAC_TYPE_NONE;
@@ -6237,15 +6311,13 @@ static u8 bnx2x_update_link_up(struct link_params *params,
6237 vars->link_status |= LINK_STATUS_LINK_UP; 6311 vars->link_status |= LINK_STATUS_LINK_UP;
6238 if (link_10g) { 6312 if (link_10g) {
6239 bnx2x_bmac_enable(params, vars, 0); 6313 bnx2x_bmac_enable(params, vars, 0);
6240 bnx2x_set_led(bp, port, LED_MODE_OPER, 6314 bnx2x_set_led(params, LED_MODE_OPER, SPEED_10000);
6241 SPEED_10000, params->hw_led_mode,
6242 params->chip_id);
6243
6244 } else { 6315 } else {
6245 bnx2x_emac_enable(params, vars, 0);
6246 rc = bnx2x_emac_program(params, vars->line_speed, 6316 rc = bnx2x_emac_program(params, vars->line_speed,
6247 vars->duplex); 6317 vars->duplex);
6248 6318
6319 bnx2x_emac_enable(params, vars, 0);
6320
6249 /* AN complete? */ 6321 /* AN complete? */
6250 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) { 6322 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
6251 if (!(vars->phy_flags & 6323 if (!(vars->phy_flags &
@@ -6343,6 +6415,7 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6343 6415
6344 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) && 6416 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
6345 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) && 6417 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
6418 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) &&
6346 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) && 6419 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
6347 (ext_phy_link_up && !vars->phy_link_up)) 6420 (ext_phy_link_up && !vars->phy_link_up))
6348 bnx2x_init_internal_phy(params, vars, 0); 6421 bnx2x_init_internal_phy(params, vars, 0);
@@ -6578,6 +6651,13 @@ static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6578 return 0; 6651 return 0;
6579} 6652}
6580 6653
6654
6655static u8 bnx2x_84823_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6656{
6657 /* HW reset */
6658 bnx2x_ext_phy_hw_reset(bp, 1);
6659 return 0;
6660}
6581u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base) 6661u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6582{ 6662{
6583 u8 rc = 0; 6663 u8 rc = 0;
@@ -6607,7 +6687,9 @@ u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6607 /* GPIO1 affects both ports, so there's need to pull 6687 /* GPIO1 affects both ports, so there's need to pull
6608 it for single port alone */ 6688 it for single port alone */
6609 rc = bnx2x_8726_common_init_phy(bp, shmem_base); 6689 rc = bnx2x_8726_common_init_phy(bp, shmem_base);
6610 6690 break;
6691 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
6692 rc = bnx2x_84823_common_init_phy(bp, shmem_base);
6611 break; 6693 break;
6612 default: 6694 default:
6613 DP(NETIF_MSG_LINK, 6695 DP(NETIF_MSG_LINK,
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-28 19:22:38 -0400