bnx2x: Re-factor the initialization code

Moving the code to a more logical place and beautifying it. No real change in behavior. Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
author: Eilon Greenstein <eilong@broadcom.com> 2009-08-12 04:24:14 -0400
committer: David S. Miller <davem@davemloft.net> 2009-08-13 02:02:59 -0400
commit: 573f203574581faaf80ca4fc079d33452327fc3b (patch)
tree: 1bd1cce6b130dc6a30fced46665d3a112a168bfb /drivers/net/bnx2x_init.h
parent: e4ed7113372a04df9b7aa985ce3860207dbb1141 (diff)
1 files changed, 58 insertions, 262 deletions
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index 3ba4d888068f..65b26cbfe3e7 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -15,24 +15,11 @@
 #ifndef BNX2X_INIT_H
 #define BNX2X_INIT_H
-#define COMMON                          0x1
-#define PORT0                           0x2
-#define PORT1                           0x4
-#define INIT_EMULATION                  0x1
-#define INIT_FPGA                       0x2
-#define INIT_ASIC                       0x4
-#define INIT_HARDWARE                   0x7
-#define TSTORM_INTMEM_ADDR              TSEM_REG_FAST_MEMORY
-#define CSTORM_INTMEM_ADDR              CSEM_REG_FAST_MEMORY
-#define XSTORM_INTMEM_ADDR              XSEM_REG_FAST_MEMORY
-#define USTORM_INTMEM_ADDR              USEM_REG_FAST_MEMORY
 /* RAM0 size in bytes */
 #define STORM_INTMEM_SIZE_E1            0x5800
 #define STORM_INTMEM_SIZE_E1H           0x10000
-#define STORM_INTMEM_SIZE(bp)   ((CHIP_IS_E1H(bp) ? STORM_INTMEM_SIZE_E1H : \
+#define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1(bp) ? STORM_INTMEM_SIZE_E1 : \
-                                                    STORM_INTMEM_SIZE_E1) / 4)
+                                                    STORM_INTMEM_SIZE_E1H) / 4)
 /* Init operation types and structures */
@@ -53,65 +40,68 @@
 #define OP_WR_ASIC              0xc /* write single register on ASIC */
 /* Init stages */
-#define COMMON_STAGE            0
+/* Never reorder stages !!! */
-#define PORT0_STAGE             1
+#define COMMON_STAGE            0
-#define PORT1_STAGE             2
+#define PORT0_STAGE             1
-/* Never reorder FUNCx stages !!! */
+#define PORT1_STAGE             2
-#define FUNC0_STAGE             3
+#define FUNC0_STAGE             3
-#define FUNC1_STAGE             4
+#define FUNC1_STAGE             4
-#define FUNC2_STAGE             5
+#define FUNC2_STAGE             5
-#define FUNC3_STAGE             6
+#define FUNC3_STAGE             6
-#define FUNC4_STAGE             7
+#define FUNC4_STAGE             7
-#define FUNC5_STAGE             8
+#define FUNC5_STAGE             8
-#define FUNC6_STAGE             9
+#define FUNC6_STAGE             9
-#define FUNC7_STAGE             10
+#define FUNC7_STAGE             10
-#define STAGE_IDX_MAX           11
+#define STAGE_IDX_MAX           11
-#define STAGE_START             0
+#define STAGE_START             0
-#define STAGE_END               1
+#define STAGE_END               1
 /* Indices of blocks */
-#define PRS_BLOCK               0
+#define PRS_BLOCK               0
-#define SRCH_BLOCK              1
+#define SRCH_BLOCK              1
-#define TSDM_BLOCK              2
+#define TSDM_BLOCK              2
-#define TCM_BLOCK               3
+#define TCM_BLOCK               3
-#define BRB1_BLOCK              4
+#define BRB1_BLOCK              4
-#define TSEM_BLOCK              5
+#define TSEM_BLOCK              5
-#define PXPCS_BLOCK             6
+#define PXPCS_BLOCK             6
-#define EMAC0_BLOCK             7
+#define EMAC0_BLOCK             7
-#define EMAC1_BLOCK             8
+#define EMAC1_BLOCK             8
-#define DBU_BLOCK               9
+#define DBU_BLOCK               9
-#define MISC_BLOCK              10
+#define MISC_BLOCK              10
-#define DBG_BLOCK               11
+#define DBG_BLOCK               11
-#define NIG_BLOCK               12
+#define NIG_BLOCK               12
-#define MCP_BLOCK               13
+#define MCP_BLOCK               13
-#define UPB_BLOCK               14
+#define UPB_BLOCK               14
-#define CSDM_BLOCK              15
+#define CSDM_BLOCK              15
-#define USDM_BLOCK              16
+#define USDM_BLOCK              16
-#define CCM_BLOCK               17
+#define CCM_BLOCK               17
-#define UCM_BLOCK               18
+#define UCM_BLOCK               18
-#define USEM_BLOCK              19
+#define USEM_BLOCK              19
-#define CSEM_BLOCK              20
+#define CSEM_BLOCK              20
-#define XPB_BLOCK               21
+#define XPB_BLOCK               21
-#define DQ_BLOCK                22
+#define DQ_BLOCK                22
-#define TIMERS_BLOCK            23
+#define TIMERS_BLOCK            23
-#define XSDM_BLOCK              24
+#define XSDM_BLOCK              24
-#define QM_BLOCK                25
+#define QM_BLOCK                25
-#define PBF_BLOCK               26
+#define PBF_BLOCK               26
-#define XCM_BLOCK               27
+#define XCM_BLOCK               27
-#define XSEM_BLOCK              28
+#define XSEM_BLOCK              28
-#define CDU_BLOCK               29
+#define CDU_BLOCK               29
-#define DMAE_BLOCK              30
+#define DMAE_BLOCK              30
-#define PXP_BLOCK               31
+#define PXP_BLOCK               31
-#define CFC_BLOCK               32
+#define CFC_BLOCK               32
-#define HC_BLOCK                33
+#define HC_BLOCK                33
-#define PXP2_BLOCK              34
+#define PXP2_BLOCK              34
-#define MISC_AEU_BLOCK          35
+#define MISC_AEU_BLOCK          35
+#define PGLUE_B_BLOCK           36
+#define IGU_BLOCK               37
 /* Returns the index of start or end of a specific block stage in ops array*/
 #define BLOCK_OPS_IDX(block, stage, end) \
-       (2*(((block)*STAGE_IDX_MAX) + (stage)) + (end))
+                        (2*(((block)*STAGE_IDX_MAX) + (stage)) + (end))
 struct raw_op {
@@ -158,199 +148,5 @@ union init_op {
        struct raw_op           raw;
 };
-/****************************************************************************
-* PXP
-****************************************************************************/
-/*
- * This code configures the PCI read/write arbiter
- * which implements a weighted round robin
- * between the virtual queues in the chip.
- *
- * The values were derived for each PCI max payload and max request size.
- * since max payload and max request size are only known at run time,
- * this is done as a separate init stage.
- */
-#define NUM_WR_Q                        13
-#define NUM_RD_Q                        29
-#define MAX_RD_ORD                      3
-#define MAX_WR_ORD                      2
-/* configuration for one arbiter queue */
-struct arb_line {
-        int l;
-        int add;
-        int ubound;
-};
-/* derived configuration for each read queue for each max request size */
-static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
-/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
-        { {4, 8,  4},  {4,  8,  4},  {4,  8,  4},  {4,  8,  4}  },
-        { {4, 3,  3},  {4,  3,  3},  {4,  3,  3},  {4,  3,  3}  },
-        { {8, 3,  6},  {16, 3,  11}, {16, 3,  11}, {16, 3,  11} },
-        { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
-/* 10 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-/* 20 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
-};
-/* derived configuration for each write queue for each max request size */
-static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
-/* 1 */ { {4, 6,  3},  {4,  6,  3},  {4,  6,  3} },
-        { {4, 2,  3},  {4,  2,  3},  {4,  2,  3} },
-        { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
-        { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
-        { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
-        { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
-        { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
-        { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
-        { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
-/* 10 */{ {8, 9,  6},  {16, 9,  11}, {32, 9,  21} },
-        { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
-        { {8, 9,  6},  {16, 9,  11}, {16, 9,  11} },
-        { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
-};
-/* register addresses for read queues */
-static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
-/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
-                PXP2_REG_RQ_BW_RD_UBOUND0},
-        {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
-                PXP2_REG_PSWRQ_BW_UB1},
-        {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
-                PXP2_REG_PSWRQ_BW_UB2},
-        {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
-                PXP2_REG_PSWRQ_BW_UB3},
-        {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
-                PXP2_REG_RQ_BW_RD_UBOUND4},
-        {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
-                PXP2_REG_RQ_BW_RD_UBOUND5},
-        {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
-                PXP2_REG_PSWRQ_BW_UB6},
-        {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
-                PXP2_REG_PSWRQ_BW_UB7},
-        {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
-                PXP2_REG_PSWRQ_BW_UB8},
-/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
-                PXP2_REG_PSWRQ_BW_UB9},
-        {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
-                PXP2_REG_PSWRQ_BW_UB10},
-        {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
-                PXP2_REG_PSWRQ_BW_UB11},
-        {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
-                PXP2_REG_RQ_BW_RD_UBOUND12},
-        {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
-                PXP2_REG_RQ_BW_RD_UBOUND13},
-        {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
-                PXP2_REG_RQ_BW_RD_UBOUND14},
-        {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
-                PXP2_REG_RQ_BW_RD_UBOUND15},
-        {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
-                PXP2_REG_RQ_BW_RD_UBOUND16},
-        {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
-                PXP2_REG_RQ_BW_RD_UBOUND17},
-        {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
-                PXP2_REG_RQ_BW_RD_UBOUND18},
-/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
-                PXP2_REG_RQ_BW_RD_UBOUND19},
-        {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
-                PXP2_REG_RQ_BW_RD_UBOUND20},
-        {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
-                PXP2_REG_RQ_BW_RD_UBOUND22},
-        {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
-                PXP2_REG_RQ_BW_RD_UBOUND23},
-        {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
-                PXP2_REG_RQ_BW_RD_UBOUND24},
-        {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
-                PXP2_REG_RQ_BW_RD_UBOUND25},
-        {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
-                PXP2_REG_RQ_BW_RD_UBOUND26},
-        {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
-                PXP2_REG_RQ_BW_RD_UBOUND27},
-        {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
-                PXP2_REG_PSWRQ_BW_UB28}
-};
-/* register addresses for write queues */
-static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
-/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
-                PXP2_REG_PSWRQ_BW_UB1},
-        {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
-                PXP2_REG_PSWRQ_BW_UB2},
-        {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
-                PXP2_REG_PSWRQ_BW_UB3},
-        {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
-                PXP2_REG_PSWRQ_BW_UB6},
-        {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
-                PXP2_REG_PSWRQ_BW_UB7},
-        {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
-                PXP2_REG_PSWRQ_BW_UB8},
-        {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
-                PXP2_REG_PSWRQ_BW_UB9},
-        {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
-                PXP2_REG_PSWRQ_BW_UB10},
-        {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
-                PXP2_REG_PSWRQ_BW_UB11},
-/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
-                PXP2_REG_PSWRQ_BW_UB28},
-        {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
-                PXP2_REG_RQ_BW_WR_UBOUND29},
-        {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
-                PXP2_REG_RQ_BW_WR_UBOUND30}
-};
-/****************************************************************************
-* CDU
-****************************************************************************/
-#define CDU_REGION_NUMBER_XCM_AG        2
-#define CDU_REGION_NUMBER_UCM_AG        4
-/**
- * String-to-compress [31:8] = CID (all 24 bits)
- * String-to-compress [7:4] = Region
- * String-to-compress [3:0] = Type
- */
-#define CDU_VALID_DATA(_cid, _region, _type) \
-                (((_cid) << 8) | (((_region) & 0xf) << 4) | (((_type) & 0xf)))
-#define CDU_CRC8(_cid, _region, _type) \
-                        calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)
-#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
-                        (0x80 | (CDU_CRC8(_cid, _region, _type) & 0x7f))
-#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \
-        (0x80 | ((_type) & 0xf << 3) | (CDU_CRC8(_cid, _region, _type) & 0x7))
-#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val)        ((_val) & ~0x80)
-/* registers addresses are not in order
-   so these arrays help simplify the code */
-static const int cm_blocks[9] = {
-        MISC_BLOCK, TCM_BLOCK,  UCM_BLOCK,  CCM_BLOCK, XCM_BLOCK,
-        TSEM_BLOCK, USEM_BLOCK, CSEM_BLOCK, XSEM_BLOCK
-};
 #endif /* BNX2X_INIT_H */
author	Eilon Greenstein <eilong@broadcom.com>	2009-08-12 04:24:14 -0400
committer	David S. Miller <davem@davemloft.net>	2009-08-13 02:02:59 -0400
commit	573f203574581faaf80ca4fc079d33452327fc3b (patch)
tree	1bd1cce6b130dc6a30fced46665d3a112a168bfb /drivers/net/bnx2x_init.h
parent	e4ed7113372a04df9b7aa985ce3860207dbb1141 (diff)

diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h index 3ba4d888068f..65b26cbfe3e7 100644 --- a/drivers/net/bnx2x_init.h +++ b/drivers/net/bnx2x_init.h
@@ -15,24 +15,11 @@
15	#ifndef BNX2X_INIT_H	15	#ifndef BNX2X_INIT_H
16	#define BNX2X_INIT_H	16	#define BNX2X_INIT_H
17		17
18	#define COMMON 0x1
19	#define PORT0 0x2
20	#define PORT1 0x4
21
22	#define INIT_EMULATION 0x1
23	#define INIT_FPGA 0x2
24	#define INIT_ASIC 0x4
25	#define INIT_HARDWARE 0x7
26
27	#define TSTORM_INTMEM_ADDR TSEM_REG_FAST_MEMORY
28	#define CSTORM_INTMEM_ADDR CSEM_REG_FAST_MEMORY
29	#define XSTORM_INTMEM_ADDR XSEM_REG_FAST_MEMORY
30	#define USTORM_INTMEM_ADDR USEM_REG_FAST_MEMORY
31	/* RAM0 size in bytes */	18	/* RAM0 size in bytes */
32	#define STORM_INTMEM_SIZE_E1 0x5800	19	#define STORM_INTMEM_SIZE_E1 0x5800
33	#define STORM_INTMEM_SIZE_E1H 0x10000	20	#define STORM_INTMEM_SIZE_E1H 0x10000
34	#define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1H(bp) ? STORM_INTMEM_SIZE_E1H : \	21	#define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1(bp) ? STORM_INTMEM_SIZE_E1 : \
35	STORM_INTMEM_SIZE_E1) / 4)	22	STORM_INTMEM_SIZE_E1H) / 4)
36		23
37		24
38	/* Init operation types and structures */	25	/* Init operation types and structures */
@@ -53,65 +40,68 @@
53	#define OP_WR_ASIC 0xc /* write single register on ASIC */	40	#define OP_WR_ASIC 0xc /* write single register on ASIC */
54		41
55	/* Init stages */	42	/* Init stages */
56	#define COMMON_STAGE 0	43	/* Never reorder stages !!! */
57	#define PORT0_STAGE 1	44	#define COMMON_STAGE 0
58	#define PORT1_STAGE 2	45	#define PORT0_STAGE 1
59	/* Never reorder FUNCx stages !!! */	46	#define PORT1_STAGE 2
60	#define FUNC0_STAGE 3	47	#define FUNC0_STAGE 3
61	#define FUNC1_STAGE 4	48	#define FUNC1_STAGE 4
62	#define FUNC2_STAGE 5	49	#define FUNC2_STAGE 5
63	#define FUNC3_STAGE 6	50	#define FUNC3_STAGE 6
64	#define FUNC4_STAGE 7	51	#define FUNC4_STAGE 7
65	#define FUNC5_STAGE 8	52	#define FUNC5_STAGE 8
66	#define FUNC6_STAGE 9	53	#define FUNC6_STAGE 9
67	#define FUNC7_STAGE 10	54	#define FUNC7_STAGE 10
68	#define STAGE_IDX_MAX 11	55	#define STAGE_IDX_MAX 11
69		56
70	#define STAGE_START 0	57	#define STAGE_START 0
71	#define STAGE_END 1	58	#define STAGE_END 1
72		59
73		60
74	/* Indices of blocks */	61	/* Indices of blocks */
75	#define PRS_BLOCK 0	62	#define PRS_BLOCK 0
76	#define SRCH_BLOCK 1	63	#define SRCH_BLOCK 1
77	#define TSDM_BLOCK 2	64	#define TSDM_BLOCK 2
78	#define TCM_BLOCK 3	65	#define TCM_BLOCK 3
79	#define BRB1_BLOCK 4	66	#define BRB1_BLOCK 4
80	#define TSEM_BLOCK 5	67	#define TSEM_BLOCK 5
81	#define PXPCS_BLOCK 6	68	#define PXPCS_BLOCK 6
82	#define EMAC0_BLOCK 7	69	#define EMAC0_BLOCK 7
83	#define EMAC1_BLOCK 8	70	#define EMAC1_BLOCK 8
84	#define DBU_BLOCK 9	71	#define DBU_BLOCK 9
85	#define MISC_BLOCK 10	72	#define MISC_BLOCK 10
86	#define DBG_BLOCK 11	73	#define DBG_BLOCK 11
87	#define NIG_BLOCK 12	74	#define NIG_BLOCK 12
88	#define MCP_BLOCK 13	75	#define MCP_BLOCK 13
89	#define UPB_BLOCK 14	76	#define UPB_BLOCK 14
90	#define CSDM_BLOCK 15	77	#define CSDM_BLOCK 15
91	#define USDM_BLOCK 16	78	#define USDM_BLOCK 16
92	#define CCM_BLOCK 17	79	#define CCM_BLOCK 17
93	#define UCM_BLOCK 18	80	#define UCM_BLOCK 18
94	#define USEM_BLOCK 19	81	#define USEM_BLOCK 19
95	#define CSEM_BLOCK 20	82	#define CSEM_BLOCK 20
96	#define XPB_BLOCK 21	83	#define XPB_BLOCK 21
97	#define DQ_BLOCK 22	84	#define DQ_BLOCK 22
98	#define TIMERS_BLOCK 23	85	#define TIMERS_BLOCK 23
99	#define XSDM_BLOCK 24	86	#define XSDM_BLOCK 24
100	#define QM_BLOCK 25	87	#define QM_BLOCK 25
101	#define PBF_BLOCK 26	88	#define PBF_BLOCK 26
102	#define XCM_BLOCK 27	89	#define XCM_BLOCK 27
103	#define XSEM_BLOCK 28	90	#define XSEM_BLOCK 28
104	#define CDU_BLOCK 29	91	#define CDU_BLOCK 29
105	#define DMAE_BLOCK 30	92	#define DMAE_BLOCK 30
106	#define PXP_BLOCK 31	93	#define PXP_BLOCK 31
107	#define CFC_BLOCK 32	94	#define CFC_BLOCK 32
108	#define HC_BLOCK 33	95	#define HC_BLOCK 33
109	#define PXP2_BLOCK 34	96	#define PXP2_BLOCK 34
110	#define MISC_AEU_BLOCK 35	97	#define MISC_AEU_BLOCK 35
		98	#define PGLUE_B_BLOCK 36
		99	#define IGU_BLOCK 37
		100
111		101
112	/* Returns the index of start or end of a specific block stage in ops array*/	102	/* Returns the index of start or end of a specific block stage in ops array*/
113	#define BLOCK_OPS_IDX(block, stage, end) \	103	#define BLOCK_OPS_IDX(block, stage, end) \
114	(2(((block)STAGE_IDX_MAX) + (stage)) + (end))	104	(2(((block)STAGE_IDX_MAX) + (stage)) + (end))
115		105
116		106
117	struct raw_op {	107	struct raw_op {
@@ -158,199 +148,5 @@ union init_op {
158	struct raw_op raw;	148	struct raw_op raw;
159	};	149	};
160		150
161	/****************************************************************************
162	* PXP
163	****************************************************************************/
164	/*
165	* This code configures the PCI read/write arbiter
166	* which implements a weighted round robin
167	* between the virtual queues in the chip.
168	*
169	* The values were derived for each PCI max payload and max request size.
170	* since max payload and max request size are only known at run time,
171	* this is done as a separate init stage.
172	*/
173
174	#define NUM_WR_Q 13
175	#define NUM_RD_Q 29
176	#define MAX_RD_ORD 3
177	#define MAX_WR_ORD 2
178
179	/* configuration for one arbiter queue */
180	struct arb_line {
181	int l;
182	int add;
183	int ubound;
184	};
185
186	/* derived configuration for each read queue for each max request size */
187	static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
188	/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
189	{ {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
190	{ {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
191	{ {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
192	{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
193	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
194	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
195	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
196	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
197	/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
198	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
199	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
200	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
201	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
202	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
203	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
204	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
205	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
206	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
207	/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
208	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
209	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
210	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
211	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
212	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
213	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
214	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
215	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
216	{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
217	};
218
219	/* derived configuration for each write queue for each max request size */
220	static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
221	/* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
222	{ {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
223	{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
224	{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
225	{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
226	{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
227	{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
228	{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
229	{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
230	/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
231	{ {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
232	{ {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
233	{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
234	};
235
236	/* register addresses for read queues */
237	static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
238	/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
239	PXP2_REG_RQ_BW_RD_UBOUND0},
240	{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
241	PXP2_REG_PSWRQ_BW_UB1},
242	{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
243	PXP2_REG_PSWRQ_BW_UB2},
244	{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
245	PXP2_REG_PSWRQ_BW_UB3},
246	{PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
247	PXP2_REG_RQ_BW_RD_UBOUND4},
248	{PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
249	PXP2_REG_RQ_BW_RD_UBOUND5},
250	{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
251	PXP2_REG_PSWRQ_BW_UB6},
252	{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
253	PXP2_REG_PSWRQ_BW_UB7},
254	{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
255	PXP2_REG_PSWRQ_BW_UB8},
256	/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
257	PXP2_REG_PSWRQ_BW_UB9},
258	{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
259	PXP2_REG_PSWRQ_BW_UB10},
260	{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
261	PXP2_REG_PSWRQ_BW_UB11},
262	{PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
263	PXP2_REG_RQ_BW_RD_UBOUND12},
264	{PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
265	PXP2_REG_RQ_BW_RD_UBOUND13},
266	{PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
267	PXP2_REG_RQ_BW_RD_UBOUND14},
268	{PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
269	PXP2_REG_RQ_BW_RD_UBOUND15},
270	{PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
271	PXP2_REG_RQ_BW_RD_UBOUND16},
272	{PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
273	PXP2_REG_RQ_BW_RD_UBOUND17},
274	{PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
275	PXP2_REG_RQ_BW_RD_UBOUND18},
276	/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
277	PXP2_REG_RQ_BW_RD_UBOUND19},
278	{PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
279	PXP2_REG_RQ_BW_RD_UBOUND20},
280	{PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
281	PXP2_REG_RQ_BW_RD_UBOUND22},
282	{PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
283	PXP2_REG_RQ_BW_RD_UBOUND23},
284	{PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
285	PXP2_REG_RQ_BW_RD_UBOUND24},
286	{PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
287	PXP2_REG_RQ_BW_RD_UBOUND25},
288	{PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
289	PXP2_REG_RQ_BW_RD_UBOUND26},
290	{PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
291	PXP2_REG_RQ_BW_RD_UBOUND27},
292	{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
293	PXP2_REG_PSWRQ_BW_UB28}
294	};
295
296	/* register addresses for write queues */
297	static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
298	/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
299	PXP2_REG_PSWRQ_BW_UB1},
300	{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
301	PXP2_REG_PSWRQ_BW_UB2},
302	{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
303	PXP2_REG_PSWRQ_BW_UB3},
304	{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
305	PXP2_REG_PSWRQ_BW_UB6},
306	{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
307	PXP2_REG_PSWRQ_BW_UB7},
308	{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
309	PXP2_REG_PSWRQ_BW_UB8},
310	{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
311	PXP2_REG_PSWRQ_BW_UB9},
312	{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
313	PXP2_REG_PSWRQ_BW_UB10},
314	{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
315	PXP2_REG_PSWRQ_BW_UB11},
316	/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
317	PXP2_REG_PSWRQ_BW_UB28},
318	{PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
319	PXP2_REG_RQ_BW_WR_UBOUND29},
320	{PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
321	PXP2_REG_RQ_BW_WR_UBOUND30}
322	};
323
324
325	/****************************************************************************
326	* CDU
327	****************************************************************************/
328
329	#define CDU_REGION_NUMBER_XCM_AG 2
330	#define CDU_REGION_NUMBER_UCM_AG 4
331
332	/**
333	* String-to-compress [31:8] = CID (all 24 bits)
334	* String-to-compress [7:4] = Region
335	* String-to-compress [3:0] = Type
336	*/
337	#define CDU_VALID_DATA(_cid, _region, _type) \
338	(((_cid) << 8) \| (((_region) & 0xf) << 4) \| (((_type) & 0xf)))
339	#define CDU_CRC8(_cid, _region, _type) \
340	calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)
341	#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
342	(0x80 \| (CDU_CRC8(_cid, _region, _type) & 0x7f))
343	#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \
344	(0x80 \| ((_type) & 0xf << 3) \| (CDU_CRC8(_cid, _region, _type) & 0x7))
345	#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
346
347
348	/* registers addresses are not in order
349	so these arrays help simplify the code */
350	static const int cm_blocks[9] = {
351	MISC_BLOCK, TCM_BLOCK, UCM_BLOCK, CCM_BLOCK, XCM_BLOCK,
352	TSEM_BLOCK, USEM_BLOCK, CSEM_BLOCK, XSEM_BLOCK
353	};
354
355	#endif /* BNX2X_INIT_H */	151	#endif /* BNX2X_INIT_H */
356		152