diff options
author | Dmitry Kravkov <dmitry@broadcom.com> | 2010-10-05 23:26:40 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-10-06 17:10:36 -0400 |
commit | fb3bff178e722fe88b5ab02319c9636da0980e25 (patch) | |
tree | 137b9073e0fb18d26c4aafce714631b25494c95a /drivers/net/bnx2x/bnx2x_main.c | |
parent | 6f7aeeec7e142caf30e3b420c2411ad85f23b9f5 (diff) |
bnx2x: rename MF related fields
MF (multi-function) mode supported not only by 57711E (E1H) devices,
but also by coming 57712E, then we use more generic names.
Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_main.c')
-rw-r--r-- | drivers/net/bnx2x/bnx2x_main.c | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c index 119ca871f016..238e38f051fb 100644 --- a/drivers/net/bnx2x/bnx2x_main.c +++ b/drivers/net/bnx2x/bnx2x_main.c | |||
@@ -1013,7 +1013,7 @@ void bnx2x_int_enable(struct bnx2x *bp) | |||
1013 | 1013 | ||
1014 | if (CHIP_IS_E1H(bp)) { | 1014 | if (CHIP_IS_E1H(bp)) { |
1015 | /* init leading/trailing edge */ | 1015 | /* init leading/trailing edge */ |
1016 | if (IS_E1HMF(bp)) { | 1016 | if (IS_MF(bp)) { |
1017 | val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); | 1017 | val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); |
1018 | if (bp->port.pmf) | 1018 | if (bp->port.pmf) |
1019 | /* enable nig and gpio3 attention */ | 1019 | /* enable nig and gpio3 attention */ |
@@ -1792,7 +1792,7 @@ static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) | |||
1792 | { | 1792 | { |
1793 | if (CHIP_REV_IS_SLOW(bp)) | 1793 | if (CHIP_REV_IS_SLOW(bp)) |
1794 | return CMNG_FNS_NONE; | 1794 | return CMNG_FNS_NONE; |
1795 | if (IS_E1HMF(bp)) | 1795 | if (IS_MF(bp)) |
1796 | return CMNG_FNS_MINMAX; | 1796 | return CMNG_FNS_MINMAX; |
1797 | 1797 | ||
1798 | return CMNG_FNS_NONE; | 1798 | return CMNG_FNS_NONE; |
@@ -1906,7 +1906,7 @@ static void bnx2x_link_attn(struct bnx2x *bp) | |||
1906 | if (prev_link_status != bp->link_vars.link_status) | 1906 | if (prev_link_status != bp->link_vars.link_status) |
1907 | bnx2x_link_report(bp); | 1907 | bnx2x_link_report(bp); |
1908 | 1908 | ||
1909 | if (IS_E1HMF(bp)) { | 1909 | if (IS_MF(bp)) { |
1910 | int port = BP_PORT(bp); | 1910 | int port = BP_PORT(bp); |
1911 | int func; | 1911 | int func; |
1912 | int vn; | 1912 | int vn; |
@@ -2160,7 +2160,7 @@ static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp, | |||
2160 | /* calculate queue flags */ | 2160 | /* calculate queue flags */ |
2161 | flags |= QUEUE_FLG_CACHE_ALIGN; | 2161 | flags |= QUEUE_FLG_CACHE_ALIGN; |
2162 | flags |= QUEUE_FLG_HC; | 2162 | flags |= QUEUE_FLG_HC; |
2163 | flags |= IS_E1HMF(bp) ? QUEUE_FLG_OV : 0; | 2163 | flags |= IS_MF(bp) ? QUEUE_FLG_OV : 0; |
2164 | 2164 | ||
2165 | #ifdef BCM_VLAN | 2165 | #ifdef BCM_VLAN |
2166 | flags |= QUEUE_FLG_VLAN; | 2166 | flags |= QUEUE_FLG_VLAN; |
@@ -2262,7 +2262,7 @@ void bnx2x_pf_init(struct bnx2x *bp) | |||
2262 | 2262 | ||
2263 | /* pf specific setups */ | 2263 | /* pf specific setups */ |
2264 | if (!CHIP_IS_E1(bp)) | 2264 | if (!CHIP_IS_E1(bp)) |
2265 | storm_memset_ov(bp, bp->e1hov, BP_FUNC(bp)); | 2265 | storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp)); |
2266 | 2266 | ||
2267 | /* function setup flags */ | 2267 | /* function setup flags */ |
2268 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); | 2268 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); |
@@ -3855,13 +3855,13 @@ static void bnx2x_init_internal_common(struct bnx2x *bp) | |||
3855 | /* xstorm needs to know whether to add ovlan to packets or not, | 3855 | /* xstorm needs to know whether to add ovlan to packets or not, |
3856 | * in switch-independent we'll write 0 to here... */ | 3856 | * in switch-independent we'll write 0 to here... */ |
3857 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET, | 3857 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET, |
3858 | bp->e1hmf); | 3858 | bp->mf_mode); |
3859 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET, | 3859 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET, |
3860 | bp->e1hmf); | 3860 | bp->mf_mode); |
3861 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET, | 3861 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET, |
3862 | bp->e1hmf); | 3862 | bp->mf_mode); |
3863 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET, | 3863 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET, |
3864 | bp->e1hmf); | 3864 | bp->mf_mode); |
3865 | } | 3865 | } |
3866 | 3866 | ||
3867 | /* Zero this manually as its initialization is | 3867 | /* Zero this manually as its initialization is |
@@ -4418,7 +4418,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code) | |||
4418 | 4418 | ||
4419 | bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE); | 4419 | bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE); |
4420 | if (CHIP_IS_E1H(bp)) | 4420 | if (CHIP_IS_E1H(bp)) |
4421 | REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp)); | 4421 | REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp)); |
4422 | 4422 | ||
4423 | REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100); | 4423 | REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100); |
4424 | msleep(30); | 4424 | msleep(30); |
@@ -4518,7 +4518,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code) | |||
4518 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | 4518 | REG_WR(bp, PRS_REG_NIC_MODE, 1); |
4519 | #endif | 4519 | #endif |
4520 | if (CHIP_IS_E1H(bp)) | 4520 | if (CHIP_IS_E1H(bp)) |
4521 | REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp)); | 4521 | REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF(bp)); |
4522 | 4522 | ||
4523 | bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE); | 4523 | bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE); |
4524 | bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE); | 4524 | bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE); |
@@ -4596,8 +4596,8 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code) | |||
4596 | 4596 | ||
4597 | bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE); | 4597 | bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE); |
4598 | if (CHIP_IS_E1H(bp)) { | 4598 | if (CHIP_IS_E1H(bp)) { |
4599 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp)); | 4599 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); |
4600 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp)); | 4600 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF(bp)); |
4601 | } | 4601 | } |
4602 | 4602 | ||
4603 | if (CHIP_REV_IS_SLOW(bp)) | 4603 | if (CHIP_REV_IS_SLOW(bp)) |
@@ -4692,7 +4692,7 @@ static int bnx2x_init_hw_port(struct bnx2x *bp) | |||
4692 | low = 0; | 4692 | low = 0; |
4693 | high = 513; | 4693 | high = 513; |
4694 | } else { | 4694 | } else { |
4695 | if (IS_E1HMF(bp)) | 4695 | if (IS_MF(bp)) |
4696 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | 4696 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); |
4697 | else if (bp->dev->mtu > 4096) { | 4697 | else if (bp->dev->mtu > 4096) { |
4698 | if (bp->flags & ONE_PORT_FLAG) | 4698 | if (bp->flags & ONE_PORT_FLAG) |
@@ -4758,7 +4758,7 @@ static int bnx2x_init_hw_port(struct bnx2x *bp) | |||
4758 | * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF | 4758 | * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF |
4759 | * bits 4-7 are used for "per vn group attention" */ | 4759 | * bits 4-7 are used for "per vn group attention" */ |
4760 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, | 4760 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, |
4761 | (IS_E1HMF(bp) ? 0xF7 : 0x7)); | 4761 | (IS_MF(bp) ? 0xF7 : 0x7)); |
4762 | 4762 | ||
4763 | bnx2x_init_block(bp, PXPCS_BLOCK, init_stage); | 4763 | bnx2x_init_block(bp, PXPCS_BLOCK, init_stage); |
4764 | bnx2x_init_block(bp, EMAC0_BLOCK, init_stage); | 4764 | bnx2x_init_block(bp, EMAC0_BLOCK, init_stage); |
@@ -4771,9 +4771,9 @@ static int bnx2x_init_hw_port(struct bnx2x *bp) | |||
4771 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | 4771 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); |
4772 | 4772 | ||
4773 | if (CHIP_IS_E1H(bp)) { | 4773 | if (CHIP_IS_E1H(bp)) { |
4774 | /* 0x2 disable e1hov, 0x1 enable */ | 4774 | /* 0x2 disable mf_ov, 0x1 enable */ |
4775 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, | 4775 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
4776 | (IS_E1HMF(bp) ? 0x1 : 0x2)); | 4776 | (IS_MF(bp) ? 0x1 : 0x2)); |
4777 | 4777 | ||
4778 | { | 4778 | { |
4779 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | 4779 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); |
@@ -4883,9 +4883,9 @@ static int bnx2x_init_hw_func(struct bnx2x *bp) | |||
4883 | 4883 | ||
4884 | bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func); | 4884 | bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func); |
4885 | 4885 | ||
4886 | if (IS_E1HMF(bp)) { | 4886 | if (IS_MF(bp)) { |
4887 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); | 4887 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
4888 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov); | 4888 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); |
4889 | } | 4889 | } |
4890 | 4890 | ||
4891 | bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func); | 4891 | bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func); |
@@ -7189,8 +7189,8 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |||
7189 | bp->igu_base_sb = 0; | 7189 | bp->igu_base_sb = 0; |
7190 | bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x, bp->l2_cid_count); | 7190 | bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x, bp->l2_cid_count); |
7191 | 7191 | ||
7192 | bp->e1hov = 0; | 7192 | bp->mf_ov = 0; |
7193 | bp->e1hmf = 0; | 7193 | bp->mf_mode = 0; |
7194 | if (CHIP_IS_E1H(bp) && !BP_NOMCP(bp)) { | 7194 | if (CHIP_IS_E1H(bp) && !BP_NOMCP(bp)) { |
7195 | 7195 | ||
7196 | bp->common.mf_cfg_base = bp->common.shmem_base + | 7196 | bp->common.mf_cfg_base = bp->common.shmem_base + |
@@ -7202,19 +7202,19 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |||
7202 | val = (MF_CFG_RD(bp, func_mf_config[FUNC_0].e1hov_tag) & | 7202 | val = (MF_CFG_RD(bp, func_mf_config[FUNC_0].e1hov_tag) & |
7203 | FUNC_MF_CFG_E1HOV_TAG_MASK); | 7203 | FUNC_MF_CFG_E1HOV_TAG_MASK); |
7204 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | 7204 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) |
7205 | bp->e1hmf = 1; | 7205 | bp->mf_mode = 1; |
7206 | BNX2X_DEV_INFO("%s function mode\n", | 7206 | BNX2X_DEV_INFO("%s function mode\n", |
7207 | IS_E1HMF(bp) ? "multi" : "single"); | 7207 | IS_MF(bp) ? "multi" : "single"); |
7208 | 7208 | ||
7209 | if (IS_E1HMF(bp)) { | 7209 | if (IS_MF(bp)) { |
7210 | val = (MF_CFG_RD(bp, func_mf_config[func]. | 7210 | val = (MF_CFG_RD(bp, func_mf_config[func]. |
7211 | e1hov_tag) & | 7211 | e1hov_tag) & |
7212 | FUNC_MF_CFG_E1HOV_TAG_MASK); | 7212 | FUNC_MF_CFG_E1HOV_TAG_MASK); |
7213 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | 7213 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
7214 | bp->e1hov = val; | 7214 | bp->mf_ov = val; |
7215 | BNX2X_DEV_INFO("E1HOV for func %d is %d " | 7215 | BNX2X_DEV_INFO("E1HOV for func %d is %d " |
7216 | "(0x%04x)\n", | 7216 | "(0x%04x)\n", |
7217 | func, bp->e1hov, bp->e1hov); | 7217 | func, bp->mf_ov, bp->mf_ov); |
7218 | } else { | 7218 | } else { |
7219 | BNX2X_ERROR("No valid E1HOV for func %d," | 7219 | BNX2X_ERROR("No valid E1HOV for func %d," |
7220 | " aborting\n", func); | 7220 | " aborting\n", func); |
@@ -7230,7 +7230,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |||
7230 | } | 7230 | } |
7231 | 7231 | ||
7232 | /* adjust igu_sb_cnt to MF */ | 7232 | /* adjust igu_sb_cnt to MF */ |
7233 | if (IS_E1HMF(bp)) | 7233 | if (IS_MF(bp)) |
7234 | bp->igu_sb_cnt /= E1HVN_MAX; | 7234 | bp->igu_sb_cnt /= E1HVN_MAX; |
7235 | 7235 | ||
7236 | if (!BP_NOMCP(bp)) { | 7236 | if (!BP_NOMCP(bp)) { |
@@ -7241,7 +7241,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |||
7241 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | 7241 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); |
7242 | } | 7242 | } |
7243 | 7243 | ||
7244 | if (IS_E1HMF(bp)) { | 7244 | if (IS_MF(bp)) { |
7245 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | 7245 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); |
7246 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | 7246 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); |
7247 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | 7247 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && |