bnx2x: Adjust BCM84833 to BCM578xx

Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@conan.davemloft.net>

1 files changed, 47 insertions, 0 deletions

diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index 0dddba9532c1..29c67029c756 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -1955,6 +1955,53 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
         return 0;
 }
 
+int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
+{
+        u32 gpio_reg = 0;
+        int rc = 0;
+
+        /* Any port swapping should be handled by caller. */
+
+        bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
+        /* read GPIO and mask except the float bits */
+        gpio_reg = REG_RD(bp, MISC_REG_GPIO);
+        gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
+        gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
+        gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
+
+        switch (mode) {
+        case MISC_REGISTERS_GPIO_OUTPUT_LOW:
+                DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
+                /* set CLR */
+                gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
+                break;
+
+        case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
+                DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
+                /* set SET */
+                gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
+                break;
+
+        case MISC_REGISTERS_GPIO_INPUT_HI_Z:
+                DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
+                /* set FLOAT */
+                gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
+                break;
+
+        default:
+                BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
+                rc = -EINVAL;
+                break;
+        }
+
+        if (rc == 0)
+                REG_WR(bp, MISC_REG_GPIO, gpio_reg);
+
+        bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
+
+        return rc;
+}
+
 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
 {
         /* The GPIO should be swapped if swap register is set and active */