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authorYaniv Rosner <yanivr@broadcom.com>2011-07-04 21:06:59 -0400
committerDavid S. Miller <davem@davemloft.net>2011-07-05 07:21:40 -0400
commit0520e63acb387a265c2a6abbf51c44c67149cf37 (patch)
tree071b86eed9b2e641a6c189e95742bd092fbf1c95 /drivers/net/bnx2x/bnx2x_link.c
parent85242eea68f5039458afad0e4030828496bb4034 (diff)
bnx2x: Fix BCM84833 initialization
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_link.c')
-rw-r--r--drivers/net/bnx2x/bnx2x_link.c45
1 files changed, 33 insertions, 12 deletions
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index 144cfae39661..d6684b38a26d 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -9182,11 +9182,14 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9182 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9182 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9183 an_1000_val); 9183 an_1000_val);
9184 9184
9185 /* set 10 speed advertisement */ 9185 /* set 100 speed advertisement */
9186 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9186 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9187 (phy->speed_cap_mask & 9187 (phy->speed_cap_mask &
9188 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | 9188 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9189 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) { 9189 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
9190 (phy->supported &
9191 (SUPPORTED_100baseT_Half |
9192 SUPPORTED_100baseT_Full)))) {
9190 an_10_100_val |= (1<<7); 9193 an_10_100_val |= (1<<7);
9191 /* Enable autoneg and restart autoneg for legacy speeds */ 9194 /* Enable autoneg and restart autoneg for legacy speeds */
9192 autoneg_val |= (1<<9 | 1<<12); 9195 autoneg_val |= (1<<9 | 1<<12);
@@ -9197,9 +9200,12 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9197 } 9200 }
9198 /* set 10 speed advertisement */ 9201 /* set 10 speed advertisement */
9199 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9202 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9200 (phy->speed_cap_mask & 9203 (phy->speed_cap_mask &
9201 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | 9204 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9202 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) { 9205 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9206 (phy->supported &
9207 (SUPPORTED_10baseT_Half |
9208 SUPPORTED_10baseT_Full)))) {
9203 an_10_100_val |= (1<<5); 9209 an_10_100_val |= (1<<5);
9204 autoneg_val |= (1<<9 | 1<<12); 9210 autoneg_val |= (1<<9 | 1<<12);
9205 if (phy->req_duplex == DUPLEX_FULL) 9211 if (phy->req_duplex == DUPLEX_FULL)
@@ -9208,7 +9214,10 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9208 } 9214 }
9209 9215
9210 /* Only 10/100 are allowed to work in FORCE mode */ 9216 /* Only 10/100 are allowed to work in FORCE mode */
9211 if (phy->req_line_speed == SPEED_100) { 9217 if ((phy->req_line_speed == SPEED_100) &&
9218 (phy->supported &
9219 (SUPPORTED_100baseT_Half |
9220 SUPPORTED_100baseT_Full))) {
9212 autoneg_val |= (1<<13); 9221 autoneg_val |= (1<<13);
9213 /* Enabled AUTO-MDIX when autoneg is disabled */ 9222 /* Enabled AUTO-MDIX when autoneg is disabled */
9214 bnx2x_cl45_write(bp, phy, 9223 bnx2x_cl45_write(bp, phy,
@@ -9216,7 +9225,10 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9216 (1<<15 | 1<<9 | 7<<0)); 9225 (1<<15 | 1<<9 | 7<<0));
9217 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 9226 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9218 } 9227 }
9219 if (phy->req_line_speed == SPEED_10) { 9228 if ((phy->req_line_speed == SPEED_10) &&
9229 (phy->supported &
9230 (SUPPORTED_10baseT_Half |
9231 SUPPORTED_10baseT_Full))) {
9220 /* Enabled AUTO-MDIX when autoneg is disabled */ 9232 /* Enabled AUTO-MDIX when autoneg is disabled */
9221 bnx2x_cl45_write(bp, phy, 9233 bnx2x_cl45_write(bp, phy,
9222 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9234 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
@@ -9284,11 +9296,22 @@ static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9284 struct link_vars *vars) 9296 struct link_vars *vars)
9285{ 9297{
9286 u32 idx; 9298 u32 idx;
9299 u32 pair_swap;
9287 u16 val; 9300 u16 val;
9288 u16 data = 0x01b1; 9301 u16 data;
9289 struct bnx2x *bp = params->bp; 9302 struct bnx2x *bp = params->bp;
9290 /* Do pair swap */ 9303 /* Do pair swap */
9291 9304
9305 /* Check for configuration. */
9306 pair_swap = REG_RD(bp, params->shmem_base +
9307 offsetof(struct shmem_region,
9308 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9309 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9310
9311 if (pair_swap == 0)
9312 return 0;
9313
9314 data = (u16)pair_swap;
9292 9315
9293 /* Write CMD_OPEN_OVERRIDE to STATUS reg */ 9316 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9294 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9317 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
@@ -10787,9 +10810,7 @@ static struct bnx2x_phy phy_84833 = {
10787 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 10810 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10788 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 10811 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10789 .mdio_ctrl = 0, 10812 .mdio_ctrl = 0,
10790 .supported = (SUPPORTED_10baseT_Half | 10813 .supported = (SUPPORTED_100baseT_Half |
10791 SUPPORTED_10baseT_Full |
10792 SUPPORTED_100baseT_Half |
10793 SUPPORTED_100baseT_Full | 10814 SUPPORTED_100baseT_Full |
10794 SUPPORTED_1000baseT_Full | 10815 SUPPORTED_1000baseT_Full |
10795 SUPPORTED_10000baseT_Full | 10816 SUPPORTED_10000baseT_Full |