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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-05-20 09:55:16 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-11 19:29:59 -0400
commit2b133ad6e9e96798007e64eb912c42fa00adef0a (patch)
tree34d1760a9257b150289893cda05b4adfa1990306 /drivers/net/atl1c
parent3401299a1b9e747cbf7de2cc0c8f6376c3cbe565 (diff)
atl*: Move the Atheros drivers
Move the Atheros drivers into drivers/net/ethernet/atheros/ and make the necessary Kconfig and Makefile changes. CC: Jay Cliburn <jcliburn@gmail.com> CC: Chris Snook <chris.snook@gmail.com> CC: Jie Yang <jie.yang@atheros.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/atl1c')
-rw-r--r--drivers/net/atl1c/Makefile2
-rw-r--r--drivers/net/atl1c/atl1c.h636
-rw-r--r--drivers/net/atl1c/atl1c_ethtool.c311
-rw-r--r--drivers/net/atl1c/atl1c_hw.c662
-rw-r--r--drivers/net/atl1c/atl1c_hw.h868
-rw-r--r--drivers/net/atl1c/atl1c_main.c2934
6 files changed, 0 insertions, 5413 deletions
diff --git a/drivers/net/atl1c/Makefile b/drivers/net/atl1c/Makefile
deleted file mode 100644
index c37d966952ee..000000000000
--- a/drivers/net/atl1c/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
1obj-$(CONFIG_ATL1C) += atl1c.o
2atl1c-objs := atl1c_main.o atl1c_hw.o atl1c_ethtool.o
diff --git a/drivers/net/atl1c/atl1c.h b/drivers/net/atl1c/atl1c.h
deleted file mode 100644
index ca70e16b6e2c..000000000000
--- a/drivers/net/atl1c/atl1c.h
+++ /dev/null
@@ -1,636 +0,0 @@
1/*
2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef _ATL1C_H_
23#define _ATL1C_H_
24
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/types.h>
28#include <linux/errno.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/ioport.h>
35#include <linux/slab.h>
36#include <linux/list.h>
37#include <linux/delay.h>
38#include <linux/sched.h>
39#include <linux/in.h>
40#include <linux/ip.h>
41#include <linux/ipv6.h>
42#include <linux/udp.h>
43#include <linux/mii.h>
44#include <linux/io.h>
45#include <linux/vmalloc.h>
46#include <linux/pagemap.h>
47#include <linux/tcp.h>
48#include <linux/ethtool.h>
49#include <linux/if_vlan.h>
50#include <linux/workqueue.h>
51#include <net/checksum.h>
52#include <net/ip6_checksum.h>
53
54#include "atl1c_hw.h"
55
56/* Wake Up Filter Control */
57#define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
58#define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
59#define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
60#define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
61#define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
62
63#define AT_VLAN_TO_TAG(_vlan, _tag) \
64 _tag = ((((_vlan) >> 8) & 0xFF) |\
65 (((_vlan) & 0xFF) << 8))
66
67#define AT_TAG_TO_VLAN(_tag, _vlan) \
68 _vlan = ((((_tag) >> 8) & 0xFF) |\
69 (((_tag) & 0xFF) << 8))
70
71#define SPEED_0 0xffff
72#define HALF_DUPLEX 1
73#define FULL_DUPLEX 2
74
75#define AT_RX_BUF_SIZE (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)
76#define MAX_JUMBO_FRAME_SIZE (6*1024)
77#define MAX_TSO_FRAME_SIZE (7*1024)
78#define MAX_TX_OFFLOAD_THRESH (9*1024)
79
80#define AT_MAX_RECEIVE_QUEUE 4
81#define AT_DEF_RECEIVE_QUEUE 1
82#define AT_MAX_TRANSMIT_QUEUE 2
83
84#define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL
85#define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL
86
87#define AT_TX_WATCHDOG (5 * HZ)
88#define AT_MAX_INT_WORK 5
89#define AT_TWSI_EEPROM_TIMEOUT 100
90#define AT_HW_MAX_IDLE_DELAY 10
91#define AT_SUSPEND_LINK_TIMEOUT 100
92
93#define AT_ASPM_L0S_TIMER 6
94#define AT_ASPM_L1_TIMER 12
95#define AT_LCKDET_TIMER 12
96
97#define ATL1C_PCIE_L0S_L1_DISABLE 0x01
98#define ATL1C_PCIE_PHY_RESET 0x02
99
100#define ATL1C_ASPM_L0s_ENABLE 0x0001
101#define ATL1C_ASPM_L1_ENABLE 0x0002
102
103#define AT_REGS_LEN (75 * sizeof(u32))
104#define AT_EEPROM_LEN 512
105
106#define ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
107#define ATL1C_RFD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc)
108#define ATL1C_TPD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc)
109#define ATL1C_RRD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status)
110
111/* tpd word 1 bit 0:7 General Checksum task offload */
112#define TPD_L4HDR_OFFSET_MASK 0x00FF
113#define TPD_L4HDR_OFFSET_SHIFT 0
114
115/* tpd word 1 bit 0:7 Large Send task offload (IPv4/IPV6) */
116#define TPD_TCPHDR_OFFSET_MASK 0x00FF
117#define TPD_TCPHDR_OFFSET_SHIFT 0
118
119/* tpd word 1 bit 0:7 Custom Checksum task offload */
120#define TPD_PLOADOFFSET_MASK 0x00FF
121#define TPD_PLOADOFFSET_SHIFT 0
122
123/* tpd word 1 bit 8:17 */
124#define TPD_CCSUM_EN_MASK 0x0001
125#define TPD_CCSUM_EN_SHIFT 8
126#define TPD_IP_CSUM_MASK 0x0001
127#define TPD_IP_CSUM_SHIFT 9
128#define TPD_TCP_CSUM_MASK 0x0001
129#define TPD_TCP_CSUM_SHIFT 10
130#define TPD_UDP_CSUM_MASK 0x0001
131#define TPD_UDP_CSUM_SHIFT 11
132#define TPD_LSO_EN_MASK 0x0001 /* TCP Large Send Offload */
133#define TPD_LSO_EN_SHIFT 12
134#define TPD_LSO_VER_MASK 0x0001
135#define TPD_LSO_VER_SHIFT 13 /* 0 : ipv4; 1 : ipv4/ipv6 */
136#define TPD_CON_VTAG_MASK 0x0001
137#define TPD_CON_VTAG_SHIFT 14
138#define TPD_INS_VTAG_MASK 0x0001
139#define TPD_INS_VTAG_SHIFT 15
140#define TPD_IPV4_PACKET_MASK 0x0001 /* valid when LSO VER is 1 */
141#define TPD_IPV4_PACKET_SHIFT 16
142#define TPD_ETH_TYPE_MASK 0x0001
143#define TPD_ETH_TYPE_SHIFT 17 /* 0 : 802.3 frame; 1 : Ethernet */
144
145/* tpd word 18:25 Custom Checksum task offload */
146#define TPD_CCSUM_OFFSET_MASK 0x00FF
147#define TPD_CCSUM_OFFSET_SHIFT 18
148#define TPD_CCSUM_EPAD_MASK 0x0001
149#define TPD_CCSUM_EPAD_SHIFT 30
150
151/* tpd word 18:30 Large Send task offload (IPv4/IPV6) */
152#define TPD_MSS_MASK 0x1FFF
153#define TPD_MSS_SHIFT 18
154
155#define TPD_EOP_MASK 0x0001
156#define TPD_EOP_SHIFT 31
157
158struct atl1c_tpd_desc {
159 __le16 buffer_len; /* include 4-byte CRC */
160 __le16 vlan_tag;
161 __le32 word1;
162 __le64 buffer_addr;
163};
164
165struct atl1c_tpd_ext_desc {
166 u32 reservd_0;
167 __le32 word1;
168 __le32 pkt_len;
169 u32 reservd_1;
170};
171/* rrs word 0 bit 0:31 */
172#define RRS_RX_CSUM_MASK 0xFFFF
173#define RRS_RX_CSUM_SHIFT 0
174#define RRS_RX_RFD_CNT_MASK 0x000F
175#define RRS_RX_RFD_CNT_SHIFT 16
176#define RRS_RX_RFD_INDEX_MASK 0x0FFF
177#define RRS_RX_RFD_INDEX_SHIFT 20
178
179/* rrs flag bit 0:16 */
180#define RRS_HEAD_LEN_MASK 0x00FF
181#define RRS_HEAD_LEN_SHIFT 0
182#define RRS_HDS_TYPE_MASK 0x0003
183#define RRS_HDS_TYPE_SHIFT 8
184#define RRS_CPU_NUM_MASK 0x0003
185#define RRS_CPU_NUM_SHIFT 10
186#define RRS_HASH_FLG_MASK 0x000F
187#define RRS_HASH_FLG_SHIFT 12
188
189#define RRS_HDS_TYPE_HEAD 1
190#define RRS_HDS_TYPE_DATA 2
191
192#define RRS_IS_NO_HDS_TYPE(flag) \
193 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == 0)
194
195#define RRS_IS_HDS_HEAD(flag) \
196 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \
197 RRS_HDS_TYPE_HEAD)
198
199#define RRS_IS_HDS_DATA(flag) \
200 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \
201 RRS_HDS_TYPE_DATA)
202
203/* rrs word 3 bit 0:31 */
204#define RRS_PKT_SIZE_MASK 0x3FFF
205#define RRS_PKT_SIZE_SHIFT 0
206#define RRS_ERR_L4_CSUM_MASK 0x0001
207#define RRS_ERR_L4_CSUM_SHIFT 14
208#define RRS_ERR_IP_CSUM_MASK 0x0001
209#define RRS_ERR_IP_CSUM_SHIFT 15
210#define RRS_VLAN_INS_MASK 0x0001
211#define RRS_VLAN_INS_SHIFT 16
212#define RRS_PROT_ID_MASK 0x0007
213#define RRS_PROT_ID_SHIFT 17
214#define RRS_RX_ERR_SUM_MASK 0x0001
215#define RRS_RX_ERR_SUM_SHIFT 20
216#define RRS_RX_ERR_CRC_MASK 0x0001
217#define RRS_RX_ERR_CRC_SHIFT 21
218#define RRS_RX_ERR_FAE_MASK 0x0001
219#define RRS_RX_ERR_FAE_SHIFT 22
220#define RRS_RX_ERR_TRUNC_MASK 0x0001
221#define RRS_RX_ERR_TRUNC_SHIFT 23
222#define RRS_RX_ERR_RUNC_MASK 0x0001
223#define RRS_RX_ERR_RUNC_SHIFT 24
224#define RRS_RX_ERR_ICMP_MASK 0x0001
225#define RRS_RX_ERR_ICMP_SHIFT 25
226#define RRS_PACKET_BCAST_MASK 0x0001
227#define RRS_PACKET_BCAST_SHIFT 26
228#define RRS_PACKET_MCAST_MASK 0x0001
229#define RRS_PACKET_MCAST_SHIFT 27
230#define RRS_PACKET_TYPE_MASK 0x0001
231#define RRS_PACKET_TYPE_SHIFT 28
232#define RRS_FIFO_FULL_MASK 0x0001
233#define RRS_FIFO_FULL_SHIFT 29
234#define RRS_802_3_LEN_ERR_MASK 0x0001
235#define RRS_802_3_LEN_ERR_SHIFT 30
236#define RRS_RXD_UPDATED_MASK 0x0001
237#define RRS_RXD_UPDATED_SHIFT 31
238
239#define RRS_ERR_L4_CSUM 0x00004000
240#define RRS_ERR_IP_CSUM 0x00008000
241#define RRS_VLAN_INS 0x00010000
242#define RRS_RX_ERR_SUM 0x00100000
243#define RRS_RX_ERR_CRC 0x00200000
244#define RRS_802_3_LEN_ERR 0x40000000
245#define RRS_RXD_UPDATED 0x80000000
246
247#define RRS_PACKET_TYPE_802_3 1
248#define RRS_PACKET_TYPE_ETH 0
249#define RRS_PACKET_IS_ETH(word) \
250 ((((word) >> RRS_PACKET_TYPE_SHIFT) & RRS_PACKET_TYPE_MASK) == \
251 RRS_PACKET_TYPE_ETH)
252#define RRS_RXD_IS_VALID(word) \
253 ((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1)
254
255#define RRS_PACKET_PROT_IS_IPV4_ONLY(word) \
256 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1)
257#define RRS_PACKET_PROT_IS_IPV6_ONLY(word) \
258 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6)
259
260struct atl1c_recv_ret_status {
261 __le32 word0;
262 __le32 rss_hash;
263 __le16 vlan_tag;
264 __le16 flag;
265 __le32 word3;
266};
267
268/* RFD descriptor */
269struct atl1c_rx_free_desc {
270 __le64 buffer_addr;
271};
272
273/* DMA Order Settings */
274enum atl1c_dma_order {
275 atl1c_dma_ord_in = 1,
276 atl1c_dma_ord_enh = 2,
277 atl1c_dma_ord_out = 4
278};
279
280enum atl1c_dma_rcb {
281 atl1c_rcb_64 = 0,
282 atl1c_rcb_128 = 1
283};
284
285enum atl1c_mac_speed {
286 atl1c_mac_speed_0 = 0,
287 atl1c_mac_speed_10_100 = 1,
288 atl1c_mac_speed_1000 = 2
289};
290
291enum atl1c_dma_req_block {
292 atl1c_dma_req_128 = 0,
293 atl1c_dma_req_256 = 1,
294 atl1c_dma_req_512 = 2,
295 atl1c_dma_req_1024 = 3,
296 atl1c_dma_req_2048 = 4,
297 atl1c_dma_req_4096 = 5
298};
299
300enum atl1c_rss_mode {
301 atl1c_rss_mode_disable = 0,
302 atl1c_rss_sig_que = 1,
303 atl1c_rss_mul_que_sig_int = 2,
304 atl1c_rss_mul_que_mul_int = 4,
305};
306
307enum atl1c_rss_type {
308 atl1c_rss_disable = 0,
309 atl1c_rss_ipv4 = 1,
310 atl1c_rss_ipv4_tcp = 2,
311 atl1c_rss_ipv6 = 4,
312 atl1c_rss_ipv6_tcp = 8
313};
314
315enum atl1c_nic_type {
316 athr_l1c = 0,
317 athr_l2c = 1,
318 athr_l2c_b,
319 athr_l2c_b2,
320 athr_l1d,
321 athr_l1d_2,
322};
323
324enum atl1c_trans_queue {
325 atl1c_trans_normal = 0,
326 atl1c_trans_high = 1
327};
328
329struct atl1c_hw_stats {
330 /* rx */
331 unsigned long rx_ok; /* The number of good packet received. */
332 unsigned long rx_bcast; /* The number of good broadcast packet received. */
333 unsigned long rx_mcast; /* The number of good multicast packet received. */
334 unsigned long rx_pause; /* The number of Pause packet received. */
335 unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */
336 unsigned long rx_fcs_err; /* The number of packets with bad FCS. */
337 unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */
338 unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
339 unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
340 unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
341 unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
342 unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
343 unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
344 unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
345 unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
346 unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
347 unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
348 unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
349 unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
350 unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
351 unsigned long rx_align_err; /* Alignment Error */
352 unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
353 unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
354 unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */
355
356 /* tx */
357 unsigned long tx_ok; /* The number of good packet transmitted. */
358 unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */
359 unsigned long tx_mcast; /* The number of good multicast packet transmitted. */
360 unsigned long tx_pause; /* The number of Pause packet transmitted. */
361 unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
362 unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
363 unsigned long tx_defer; /* The number of packets transmitted that is deferred. */
364 unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
365 unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
366 unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
367 unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
368 unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
369 unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
370 unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
371 unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
372 unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
373 unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
374 unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */
375 unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
376 unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
377 unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
378 unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
379 unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
380 unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
381 unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
382};
383
384struct atl1c_hw {
385 u8 __iomem *hw_addr; /* inner register address */
386 struct atl1c_adapter *adapter;
387 enum atl1c_nic_type nic_type;
388 enum atl1c_dma_order dma_order;
389 enum atl1c_dma_rcb rcb_value;
390 enum atl1c_dma_req_block dmar_block;
391 enum atl1c_dma_req_block dmaw_block;
392
393 u16 device_id;
394 u16 vendor_id;
395 u16 subsystem_id;
396 u16 subsystem_vendor_id;
397 u8 revision_id;
398 u16 phy_id1;
399 u16 phy_id2;
400
401 u32 intr_mask;
402 u8 dmaw_dly_cnt;
403 u8 dmar_dly_cnt;
404
405 u8 preamble_len;
406 u16 max_frame_size;
407 u16 min_frame_size;
408
409 enum atl1c_mac_speed mac_speed;
410 bool mac_duplex;
411 bool hibernate;
412 u16 media_type;
413#define MEDIA_TYPE_AUTO_SENSOR 0
414#define MEDIA_TYPE_100M_FULL 1
415#define MEDIA_TYPE_100M_HALF 2
416#define MEDIA_TYPE_10M_FULL 3
417#define MEDIA_TYPE_10M_HALF 4
418
419 u16 autoneg_advertised;
420 u16 mii_autoneg_adv_reg;
421 u16 mii_1000t_ctrl_reg;
422
423 u16 tx_imt; /* TX Interrupt Moderator timer ( 2us resolution) */
424 u16 rx_imt; /* RX Interrupt Moderator timer ( 2us resolution) */
425 u16 ict; /* Interrupt Clear timer (2us resolution) */
426 u16 ctrl_flags;
427#define ATL1C_INTR_CLEAR_ON_READ 0x0001
428#define ATL1C_INTR_MODRT_ENABLE 0x0002
429#define ATL1C_CMB_ENABLE 0x0004
430#define ATL1C_SMB_ENABLE 0x0010
431#define ATL1C_TXQ_MODE_ENHANCE 0x0020
432#define ATL1C_RX_IPV6_CHKSUM 0x0040
433#define ATL1C_ASPM_L0S_SUPPORT 0x0080
434#define ATL1C_ASPM_L1_SUPPORT 0x0100
435#define ATL1C_ASPM_CTRL_MON 0x0200
436#define ATL1C_HIB_DISABLE 0x0400
437#define ATL1C_APS_MODE_ENABLE 0x0800
438#define ATL1C_LINK_EXT_SYNC 0x1000
439#define ATL1C_CLK_GATING_EN 0x2000
440#define ATL1C_FPGA_VERSION 0x8000
441 u16 link_cap_flags;
442#define ATL1C_LINK_CAP_1000M 0x0001
443 u16 cmb_tpd;
444 u16 cmb_rrd;
445 u16 cmb_rx_timer; /* 2us resolution */
446 u16 cmb_tx_timer;
447 u32 smb_timer;
448
449 u16 rrd_thresh; /* Threshold of number of RRD produced to trigger
450 interrupt request */
451 u16 tpd_thresh;
452 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */
453 u8 rfd_burst;
454 enum atl1c_rss_type rss_type;
455 enum atl1c_rss_mode rss_mode;
456 u8 rss_hash_bits;
457 u32 base_cpu;
458 u32 indirect_tab;
459 u8 mac_addr[ETH_ALEN];
460 u8 perm_mac_addr[ETH_ALEN];
461
462 bool phy_configured;
463 bool re_autoneg;
464 bool emi_ca;
465};
466
467/*
468 * atl1c_ring_header represents a single, contiguous block of DMA space
469 * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
470 * message blocks (cmb, smb) described below
471 */
472struct atl1c_ring_header {
473 void *desc; /* virtual address */
474 dma_addr_t dma; /* physical address*/
475 unsigned int size; /* length in bytes */
476};
477
478/*
479 * atl1c_buffer is wrapper around a pointer to a socket buffer
480 * so a DMA handle can be stored along with the skb
481 */
482struct atl1c_buffer {
483 struct sk_buff *skb; /* socket buffer */
484 u16 length; /* rx buffer length */
485 u16 flags; /* information of buffer */
486#define ATL1C_BUFFER_FREE 0x0001
487#define ATL1C_BUFFER_BUSY 0x0002
488#define ATL1C_BUFFER_STATE_MASK 0x0003
489
490#define ATL1C_PCIMAP_SINGLE 0x0004
491#define ATL1C_PCIMAP_PAGE 0x0008
492#define ATL1C_PCIMAP_TYPE_MASK 0x000C
493
494#define ATL1C_PCIMAP_TODEVICE 0x0010
495#define ATL1C_PCIMAP_FROMDEVICE 0x0020
496#define ATL1C_PCIMAP_DIRECTION_MASK 0x0030
497 dma_addr_t dma;
498};
499
500#define ATL1C_SET_BUFFER_STATE(buff, state) do { \
501 ((buff)->flags) &= ~ATL1C_BUFFER_STATE_MASK; \
502 ((buff)->flags) |= (state); \
503 } while (0)
504
505#define ATL1C_SET_PCIMAP_TYPE(buff, type, direction) do { \
506 ((buff)->flags) &= ~ATL1C_PCIMAP_TYPE_MASK; \
507 ((buff)->flags) |= (type); \
508 ((buff)->flags) &= ~ATL1C_PCIMAP_DIRECTION_MASK; \
509 ((buff)->flags) |= (direction); \
510 } while (0)
511
512/* transimit packet descriptor (tpd) ring */
513struct atl1c_tpd_ring {
514 void *desc; /* descriptor ring virtual address */
515 dma_addr_t dma; /* descriptor ring physical address */
516 u16 size; /* descriptor ring length in bytes */
517 u16 count; /* number of descriptors in the ring */
518 u16 next_to_use; /* this is protectd by adapter->tx_lock */
519 atomic_t next_to_clean;
520 struct atl1c_buffer *buffer_info;
521};
522
523/* receive free descriptor (rfd) ring */
524struct atl1c_rfd_ring {
525 void *desc; /* descriptor ring virtual address */
526 dma_addr_t dma; /* descriptor ring physical address */
527 u16 size; /* descriptor ring length in bytes */
528 u16 count; /* number of descriptors in the ring */
529 u16 next_to_use;
530 u16 next_to_clean;
531 struct atl1c_buffer *buffer_info;
532};
533
534/* receive return descriptor (rrd) ring */
535struct atl1c_rrd_ring {
536 void *desc; /* descriptor ring virtual address */
537 dma_addr_t dma; /* descriptor ring physical address */
538 u16 size; /* descriptor ring length in bytes */
539 u16 count; /* number of descriptors in the ring */
540 u16 next_to_use;
541 u16 next_to_clean;
542};
543
544struct atl1c_cmb {
545 void *cmb;
546 dma_addr_t dma;
547};
548
549struct atl1c_smb {
550 void *smb;
551 dma_addr_t dma;
552};
553
554/* board specific private data structure */
555struct atl1c_adapter {
556 struct net_device *netdev;
557 struct pci_dev *pdev;
558 struct napi_struct napi;
559 struct atl1c_hw hw;
560 struct atl1c_hw_stats hw_stats;
561 struct mii_if_info mii; /* MII interface info */
562 u16 rx_buffer_len;
563
564 unsigned long flags;
565#define __AT_TESTING 0x0001
566#define __AT_RESETTING 0x0002
567#define __AT_DOWN 0x0003
568 unsigned long work_event;
569#define ATL1C_WORK_EVENT_RESET 0
570#define ATL1C_WORK_EVENT_LINK_CHANGE 1
571 u32 msg_enable;
572
573 bool have_msi;
574 u32 wol;
575 u16 link_speed;
576 u16 link_duplex;
577
578 spinlock_t mdio_lock;
579 spinlock_t tx_lock;
580 atomic_t irq_sem;
581
582 struct work_struct common_task;
583 struct timer_list watchdog_timer;
584 struct timer_list phy_config_timer;
585
586 /* All Descriptor memory */
587 struct atl1c_ring_header ring_header;
588 struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE];
589 struct atl1c_rfd_ring rfd_ring[AT_MAX_RECEIVE_QUEUE];
590 struct atl1c_rrd_ring rrd_ring[AT_MAX_RECEIVE_QUEUE];
591 struct atl1c_cmb cmb;
592 struct atl1c_smb smb;
593 int num_rx_queues;
594 u32 bd_number; /* board number;*/
595};
596
597#define AT_WRITE_REG(a, reg, value) ( \
598 writel((value), ((a)->hw_addr + reg)))
599
600#define AT_WRITE_FLUSH(a) (\
601 readl((a)->hw_addr))
602
603#define AT_READ_REG(a, reg, pdata) do { \
604 if (unlikely((a)->hibernate)) { \
605 readl((a)->hw_addr + reg); \
606 *(u32 *)pdata = readl((a)->hw_addr + reg); \
607 } else { \
608 *(u32 *)pdata = readl((a)->hw_addr + reg); \
609 } \
610 } while (0)
611
612#define AT_WRITE_REGB(a, reg, value) (\
613 writeb((value), ((a)->hw_addr + reg)))
614
615#define AT_READ_REGB(a, reg) (\
616 readb((a)->hw_addr + reg))
617
618#define AT_WRITE_REGW(a, reg, value) (\
619 writew((value), ((a)->hw_addr + reg)))
620
621#define AT_READ_REGW(a, reg) (\
622 readw((a)->hw_addr + reg))
623
624#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
625 writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
626
627#define AT_READ_REG_ARRAY(a, reg, offset) ( \
628 readl(((a)->hw_addr + reg) + ((offset) << 2)))
629
630extern char atl1c_driver_name[];
631extern char atl1c_driver_version[];
632
633extern void atl1c_reinit_locked(struct atl1c_adapter *adapter);
634extern s32 atl1c_reset_hw(struct atl1c_hw *hw);
635extern void atl1c_set_ethtool_ops(struct net_device *netdev);
636#endif /* _ATL1C_H_ */
diff --git a/drivers/net/atl1c/atl1c_ethtool.c b/drivers/net/atl1c/atl1c_ethtool.c
deleted file mode 100644
index 7be884d0aaf6..000000000000
--- a/drivers/net/atl1c/atl1c_ethtool.c
+++ /dev/null
@@ -1,311 +0,0 @@
1/*
2 * Copyright(c) 2009 - 2009 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 *
21 */
22
23#include <linux/netdevice.h>
24#include <linux/ethtool.h>
25#include <linux/slab.h>
26
27#include "atl1c.h"
28
29static int atl1c_get_settings(struct net_device *netdev,
30 struct ethtool_cmd *ecmd)
31{
32 struct atl1c_adapter *adapter = netdev_priv(netdev);
33 struct atl1c_hw *hw = &adapter->hw;
34
35 ecmd->supported = (SUPPORTED_10baseT_Half |
36 SUPPORTED_10baseT_Full |
37 SUPPORTED_100baseT_Half |
38 SUPPORTED_100baseT_Full |
39 SUPPORTED_Autoneg |
40 SUPPORTED_TP);
41 if (hw->link_cap_flags & ATL1C_LINK_CAP_1000M)
42 ecmd->supported |= SUPPORTED_1000baseT_Full;
43
44 ecmd->advertising = ADVERTISED_TP;
45
46 ecmd->advertising |= hw->autoneg_advertised;
47
48 ecmd->port = PORT_TP;
49 ecmd->phy_address = 0;
50 ecmd->transceiver = XCVR_INTERNAL;
51
52 if (adapter->link_speed != SPEED_0) {
53 ethtool_cmd_speed_set(ecmd, adapter->link_speed);
54 if (adapter->link_duplex == FULL_DUPLEX)
55 ecmd->duplex = DUPLEX_FULL;
56 else
57 ecmd->duplex = DUPLEX_HALF;
58 } else {
59 ethtool_cmd_speed_set(ecmd, -1);
60 ecmd->duplex = -1;
61 }
62
63 ecmd->autoneg = AUTONEG_ENABLE;
64 return 0;
65}
66
67static int atl1c_set_settings(struct net_device *netdev,
68 struct ethtool_cmd *ecmd)
69{
70 struct atl1c_adapter *adapter = netdev_priv(netdev);
71 struct atl1c_hw *hw = &adapter->hw;
72 u16 autoneg_advertised;
73
74 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
75 msleep(1);
76
77 if (ecmd->autoneg == AUTONEG_ENABLE) {
78 autoneg_advertised = ADVERTISED_Autoneg;
79 } else {
80 u32 speed = ethtool_cmd_speed(ecmd);
81 if (speed == SPEED_1000) {
82 if (ecmd->duplex != DUPLEX_FULL) {
83 if (netif_msg_link(adapter))
84 dev_warn(&adapter->pdev->dev,
85 "1000M half is invalid\n");
86 clear_bit(__AT_RESETTING, &adapter->flags);
87 return -EINVAL;
88 }
89 autoneg_advertised = ADVERTISED_1000baseT_Full;
90 } else if (speed == SPEED_100) {
91 if (ecmd->duplex == DUPLEX_FULL)
92 autoneg_advertised = ADVERTISED_100baseT_Full;
93 else
94 autoneg_advertised = ADVERTISED_100baseT_Half;
95 } else {
96 if (ecmd->duplex == DUPLEX_FULL)
97 autoneg_advertised = ADVERTISED_10baseT_Full;
98 else
99 autoneg_advertised = ADVERTISED_10baseT_Half;
100 }
101 }
102
103 if (hw->autoneg_advertised != autoneg_advertised) {
104 hw->autoneg_advertised = autoneg_advertised;
105 if (atl1c_restart_autoneg(hw) != 0) {
106 if (netif_msg_link(adapter))
107 dev_warn(&adapter->pdev->dev,
108 "ethtool speed/duplex setting failed\n");
109 clear_bit(__AT_RESETTING, &adapter->flags);
110 return -EINVAL;
111 }
112 }
113 clear_bit(__AT_RESETTING, &adapter->flags);
114 return 0;
115}
116
117static u32 atl1c_get_msglevel(struct net_device *netdev)
118{
119 struct atl1c_adapter *adapter = netdev_priv(netdev);
120 return adapter->msg_enable;
121}
122
123static void atl1c_set_msglevel(struct net_device *netdev, u32 data)
124{
125 struct atl1c_adapter *adapter = netdev_priv(netdev);
126 adapter->msg_enable = data;
127}
128
129static int atl1c_get_regs_len(struct net_device *netdev)
130{
131 return AT_REGS_LEN;
132}
133
134static void atl1c_get_regs(struct net_device *netdev,
135 struct ethtool_regs *regs, void *p)
136{
137 struct atl1c_adapter *adapter = netdev_priv(netdev);
138 struct atl1c_hw *hw = &adapter->hw;
139 u32 *regs_buff = p;
140 u16 phy_data;
141
142 memset(p, 0, AT_REGS_LEN);
143
144 regs->version = 0;
145 AT_READ_REG(hw, REG_VPD_CAP, p++);
146 AT_READ_REG(hw, REG_PM_CTRL, p++);
147 AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL, p++);
148 AT_READ_REG(hw, REG_TWSI_CTRL, p++);
149 AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL, p++);
150 AT_READ_REG(hw, REG_MASTER_CTRL, p++);
151 AT_READ_REG(hw, REG_MANUAL_TIMER_INIT, p++);
152 AT_READ_REG(hw, REG_IRQ_MODRT_TIMER_INIT, p++);
153 AT_READ_REG(hw, REG_GPHY_CTRL, p++);
154 AT_READ_REG(hw, REG_LINK_CTRL, p++);
155 AT_READ_REG(hw, REG_IDLE_STATUS, p++);
156 AT_READ_REG(hw, REG_MDIO_CTRL, p++);
157 AT_READ_REG(hw, REG_SERDES_LOCK, p++);
158 AT_READ_REG(hw, REG_MAC_CTRL, p++);
159 AT_READ_REG(hw, REG_MAC_IPG_IFG, p++);
160 AT_READ_REG(hw, REG_MAC_STA_ADDR, p++);
161 AT_READ_REG(hw, REG_MAC_STA_ADDR+4, p++);
162 AT_READ_REG(hw, REG_RX_HASH_TABLE, p++);
163 AT_READ_REG(hw, REG_RX_HASH_TABLE+4, p++);
164 AT_READ_REG(hw, REG_RXQ_CTRL, p++);
165 AT_READ_REG(hw, REG_TXQ_CTRL, p++);
166 AT_READ_REG(hw, REG_MTU, p++);
167 AT_READ_REG(hw, REG_WOL_CTRL, p++);
168
169 atl1c_read_phy_reg(hw, MII_BMCR, &phy_data);
170 regs_buff[73] = (u32) phy_data;
171 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
172 regs_buff[74] = (u32) phy_data;
173}
174
175static int atl1c_get_eeprom_len(struct net_device *netdev)
176{
177 struct atl1c_adapter *adapter = netdev_priv(netdev);
178
179 if (atl1c_check_eeprom_exist(&adapter->hw))
180 return AT_EEPROM_LEN;
181 else
182 return 0;
183}
184
185static int atl1c_get_eeprom(struct net_device *netdev,
186 struct ethtool_eeprom *eeprom, u8 *bytes)
187{
188 struct atl1c_adapter *adapter = netdev_priv(netdev);
189 struct atl1c_hw *hw = &adapter->hw;
190 u32 *eeprom_buff;
191 int first_dword, last_dword;
192 int ret_val = 0;
193 int i;
194
195 if (eeprom->len == 0)
196 return -EINVAL;
197
198 if (!atl1c_check_eeprom_exist(hw)) /* not exist */
199 return -EINVAL;
200
201 eeprom->magic = adapter->pdev->vendor |
202 (adapter->pdev->device << 16);
203
204 first_dword = eeprom->offset >> 2;
205 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
206
207 eeprom_buff = kmalloc(sizeof(u32) *
208 (last_dword - first_dword + 1), GFP_KERNEL);
209 if (eeprom_buff == NULL)
210 return -ENOMEM;
211
212 for (i = first_dword; i < last_dword; i++) {
213 if (!atl1c_read_eeprom(hw, i * 4, &(eeprom_buff[i-first_dword]))) {
214 kfree(eeprom_buff);
215 return -EIO;
216 }
217 }
218
219 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
220 eeprom->len);
221 kfree(eeprom_buff);
222
223 return ret_val;
224 return 0;
225}
226
227static void atl1c_get_drvinfo(struct net_device *netdev,
228 struct ethtool_drvinfo *drvinfo)
229{
230 struct atl1c_adapter *adapter = netdev_priv(netdev);
231
232 strlcpy(drvinfo->driver, atl1c_driver_name, sizeof(drvinfo->driver));
233 strlcpy(drvinfo->version, atl1c_driver_version,
234 sizeof(drvinfo->version));
235 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
236 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
237 sizeof(drvinfo->bus_info));
238 drvinfo->n_stats = 0;
239 drvinfo->testinfo_len = 0;
240 drvinfo->regdump_len = atl1c_get_regs_len(netdev);
241 drvinfo->eedump_len = atl1c_get_eeprom_len(netdev);
242}
243
244static void atl1c_get_wol(struct net_device *netdev,
245 struct ethtool_wolinfo *wol)
246{
247 struct atl1c_adapter *adapter = netdev_priv(netdev);
248
249 wol->supported = WAKE_MAGIC | WAKE_PHY;
250 wol->wolopts = 0;
251
252 if (adapter->wol & AT_WUFC_EX)
253 wol->wolopts |= WAKE_UCAST;
254 if (adapter->wol & AT_WUFC_MC)
255 wol->wolopts |= WAKE_MCAST;
256 if (adapter->wol & AT_WUFC_BC)
257 wol->wolopts |= WAKE_BCAST;
258 if (adapter->wol & AT_WUFC_MAG)
259 wol->wolopts |= WAKE_MAGIC;
260 if (adapter->wol & AT_WUFC_LNKC)
261 wol->wolopts |= WAKE_PHY;
262}
263
264static int atl1c_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
265{
266 struct atl1c_adapter *adapter = netdev_priv(netdev);
267
268 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE |
269 WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
270 return -EOPNOTSUPP;
271 /* these settings will always override what we currently have */
272 adapter->wol = 0;
273
274 if (wol->wolopts & WAKE_MAGIC)
275 adapter->wol |= AT_WUFC_MAG;
276 if (wol->wolopts & WAKE_PHY)
277 adapter->wol |= AT_WUFC_LNKC;
278
279 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
280
281 return 0;
282}
283
284static int atl1c_nway_reset(struct net_device *netdev)
285{
286 struct atl1c_adapter *adapter = netdev_priv(netdev);
287 if (netif_running(netdev))
288 atl1c_reinit_locked(adapter);
289 return 0;
290}
291
292static const struct ethtool_ops atl1c_ethtool_ops = {
293 .get_settings = atl1c_get_settings,
294 .set_settings = atl1c_set_settings,
295 .get_drvinfo = atl1c_get_drvinfo,
296 .get_regs_len = atl1c_get_regs_len,
297 .get_regs = atl1c_get_regs,
298 .get_wol = atl1c_get_wol,
299 .set_wol = atl1c_set_wol,
300 .get_msglevel = atl1c_get_msglevel,
301 .set_msglevel = atl1c_set_msglevel,
302 .nway_reset = atl1c_nway_reset,
303 .get_link = ethtool_op_get_link,
304 .get_eeprom_len = atl1c_get_eeprom_len,
305 .get_eeprom = atl1c_get_eeprom,
306};
307
308void atl1c_set_ethtool_ops(struct net_device *netdev)
309{
310 SET_ETHTOOL_OPS(netdev, &atl1c_ethtool_ops);
311}
diff --git a/drivers/net/atl1c/atl1c_hw.c b/drivers/net/atl1c/atl1c_hw.c
deleted file mode 100644
index 23f2ab0f2fa8..000000000000
--- a/drivers/net/atl1c/atl1c_hw.c
+++ /dev/null
@@ -1,662 +0,0 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#include <linux/pci.h>
22#include <linux/delay.h>
23#include <linux/mii.h>
24#include <linux/crc32.h>
25
26#include "atl1c.h"
27
28/*
29 * check_eeprom_exist
30 * return 1 if eeprom exist
31 */
32int atl1c_check_eeprom_exist(struct atl1c_hw *hw)
33{
34 u32 data;
35
36 AT_READ_REG(hw, REG_TWSI_DEBUG, &data);
37 if (data & TWSI_DEBUG_DEV_EXIST)
38 return 1;
39
40 AT_READ_REG(hw, REG_MASTER_CTRL, &data);
41 if (data & MASTER_CTRL_OTP_SEL)
42 return 1;
43 return 0;
44}
45
46void atl1c_hw_set_mac_addr(struct atl1c_hw *hw)
47{
48 u32 value;
49 /*
50 * 00-0B-6A-F6-00-DC
51 * 0: 6AF600DC 1: 000B
52 * low dword
53 */
54 value = (((u32)hw->mac_addr[2]) << 24) |
55 (((u32)hw->mac_addr[3]) << 16) |
56 (((u32)hw->mac_addr[4]) << 8) |
57 (((u32)hw->mac_addr[5])) ;
58 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
59 /* hight dword */
60 value = (((u32)hw->mac_addr[0]) << 8) |
61 (((u32)hw->mac_addr[1])) ;
62 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
63}
64
65/*
66 * atl1c_get_permanent_address
67 * return 0 if get valid mac address,
68 */
69static int atl1c_get_permanent_address(struct atl1c_hw *hw)
70{
71 u32 addr[2];
72 u32 i;
73 u32 otp_ctrl_data;
74 u32 twsi_ctrl_data;
75 u32 ltssm_ctrl_data;
76 u32 wol_data;
77 u8 eth_addr[ETH_ALEN];
78 u16 phy_data;
79 bool raise_vol = false;
80
81 /* init */
82 addr[0] = addr[1] = 0;
83 AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
84 if (atl1c_check_eeprom_exist(hw)) {
85 if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
86 /* Enable OTP CLK */
87 if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) {
88 otp_ctrl_data |= OTP_CTRL_CLK_EN;
89 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
90 AT_WRITE_FLUSH(hw);
91 msleep(1);
92 }
93 }
94
95 if (hw->nic_type == athr_l2c_b ||
96 hw->nic_type == athr_l2c_b2 ||
97 hw->nic_type == athr_l1d) {
98 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x00);
99 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
100 goto out;
101 phy_data &= 0xFF7F;
102 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
103
104 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
105 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
106 goto out;
107 phy_data |= 0x8;
108 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
109 udelay(20);
110 raise_vol = true;
111 }
112 /* close open bit of ReadOnly*/
113 AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &ltssm_ctrl_data);
114 ltssm_ctrl_data &= ~LTSSM_ID_EN_WRO;
115 AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, ltssm_ctrl_data);
116
117 /* clear any WOL settings */
118 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
119 AT_READ_REG(hw, REG_WOL_CTRL, &wol_data);
120
121
122 AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
123 twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
124 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
125 for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
126 msleep(10);
127 AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
128 if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
129 break;
130 }
131 if (i >= AT_TWSI_EEPROM_TIMEOUT)
132 return -1;
133 }
134 /* Disable OTP_CLK */
135 if ((hw->nic_type == athr_l1c || hw->nic_type == athr_l2c)) {
136 otp_ctrl_data &= ~OTP_CTRL_CLK_EN;
137 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
138 msleep(1);
139 }
140 if (raise_vol) {
141 if (hw->nic_type == athr_l2c_b ||
142 hw->nic_type == athr_l2c_b2 ||
143 hw->nic_type == athr_l1d ||
144 hw->nic_type == athr_l1d_2) {
145 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x00);
146 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
147 goto out;
148 phy_data |= 0x80;
149 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
150
151 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
152 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
153 goto out;
154 phy_data &= 0xFFF7;
155 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
156 udelay(20);
157 }
158 }
159
160 /* maybe MAC-address is from BIOS */
161 AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]);
162 AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]);
163 *(u32 *) &eth_addr[2] = swab32(addr[0]);
164 *(u16 *) &eth_addr[0] = swab16(*(u16 *)&addr[1]);
165
166 if (is_valid_ether_addr(eth_addr)) {
167 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
168 return 0;
169 }
170
171out:
172 return -1;
173}
174
175bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value)
176{
177 int i;
178 int ret = false;
179 u32 otp_ctrl_data;
180 u32 control;
181 u32 data;
182
183 if (offset & 3)
184 return ret; /* address do not align */
185
186 AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
187 if (!(otp_ctrl_data & OTP_CTRL_CLK_EN))
188 AT_WRITE_REG(hw, REG_OTP_CTRL,
189 (otp_ctrl_data | OTP_CTRL_CLK_EN));
190
191 AT_WRITE_REG(hw, REG_EEPROM_DATA_LO, 0);
192 control = (offset & EEPROM_CTRL_ADDR_MASK) << EEPROM_CTRL_ADDR_SHIFT;
193 AT_WRITE_REG(hw, REG_EEPROM_CTRL, control);
194
195 for (i = 0; i < 10; i++) {
196 udelay(100);
197 AT_READ_REG(hw, REG_EEPROM_CTRL, &control);
198 if (control & EEPROM_CTRL_RW)
199 break;
200 }
201 if (control & EEPROM_CTRL_RW) {
202 AT_READ_REG(hw, REG_EEPROM_CTRL, &data);
203 AT_READ_REG(hw, REG_EEPROM_DATA_LO, p_value);
204 data = data & 0xFFFF;
205 *p_value = swab32((data << 16) | (*p_value >> 16));
206 ret = true;
207 }
208 if (!(otp_ctrl_data & OTP_CTRL_CLK_EN))
209 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
210
211 return ret;
212}
213/*
214 * Reads the adapter's MAC address from the EEPROM
215 *
216 * hw - Struct containing variables accessed by shared code
217 */
218int atl1c_read_mac_addr(struct atl1c_hw *hw)
219{
220 int err = 0;
221
222 err = atl1c_get_permanent_address(hw);
223 if (err)
224 random_ether_addr(hw->perm_mac_addr);
225
226 memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
227 return 0;
228}
229
230/*
231 * atl1c_hash_mc_addr
232 * purpose
233 * set hash value for a multicast address
234 * hash calcu processing :
235 * 1. calcu 32bit CRC for multicast address
236 * 2. reverse crc with MSB to LSB
237 */
238u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr)
239{
240 u32 crc32;
241 u32 value = 0;
242 int i;
243
244 crc32 = ether_crc_le(6, mc_addr);
245 for (i = 0; i < 32; i++)
246 value |= (((crc32 >> i) & 1) << (31 - i));
247
248 return value;
249}
250
251/*
252 * Sets the bit in the multicast table corresponding to the hash value.
253 * hw - Struct containing variables accessed by shared code
254 * hash_value - Multicast address hash value
255 */
256void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value)
257{
258 u32 hash_bit, hash_reg;
259 u32 mta;
260
261 /*
262 * The HASH Table is a register array of 2 32-bit registers.
263 * It is treated like an array of 64 bits. We want to set
264 * bit BitArray[hash_value]. So we figure out what register
265 * the bit is in, read it, OR in the new bit, then write
266 * back the new value. The register is determined by the
267 * upper bit of the hash value and the bit within that
268 * register are determined by the lower 5 bits of the value.
269 */
270 hash_reg = (hash_value >> 31) & 0x1;
271 hash_bit = (hash_value >> 26) & 0x1F;
272
273 mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
274
275 mta |= (1 << hash_bit);
276
277 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
278}
279
280/*
281 * Reads the value from a PHY register
282 * hw - Struct containing variables accessed by shared code
283 * reg_addr - address of the PHY register to read
284 */
285int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
286{
287 u32 val;
288 int i;
289
290 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
291 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
292 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
293
294 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
295
296 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
297 udelay(2);
298 AT_READ_REG(hw, REG_MDIO_CTRL, &val);
299 if (!(val & (MDIO_START | MDIO_BUSY)))
300 break;
301 }
302 if (!(val & (MDIO_START | MDIO_BUSY))) {
303 *phy_data = (u16)val;
304 return 0;
305 }
306
307 return -1;
308}
309
310/*
311 * Writes a value to a PHY register
312 * hw - Struct containing variables accessed by shared code
313 * reg_addr - address of the PHY register to write
314 * data - data to write to the PHY
315 */
316int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data)
317{
318 int i;
319 u32 val;
320
321 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
322 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
323 MDIO_SUP_PREAMBLE | MDIO_START |
324 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
325
326 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
327
328 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
329 udelay(2);
330 AT_READ_REG(hw, REG_MDIO_CTRL, &val);
331 if (!(val & (MDIO_START | MDIO_BUSY)))
332 break;
333 }
334
335 if (!(val & (MDIO_START | MDIO_BUSY)))
336 return 0;
337
338 return -1;
339}
340
341/*
342 * Configures PHY autoneg and flow control advertisement settings
343 *
344 * hw - Struct containing variables accessed by shared code
345 */
346static int atl1c_phy_setup_adv(struct atl1c_hw *hw)
347{
348 u16 mii_adv_data = ADVERTISE_DEFAULT_CAP & ~ADVERTISE_ALL;
349 u16 mii_giga_ctrl_data = GIGA_CR_1000T_DEFAULT_CAP &
350 ~GIGA_CR_1000T_SPEED_MASK;
351
352 if (hw->autoneg_advertised & ADVERTISED_10baseT_Half)
353 mii_adv_data |= ADVERTISE_10HALF;
354 if (hw->autoneg_advertised & ADVERTISED_10baseT_Full)
355 mii_adv_data |= ADVERTISE_10FULL;
356 if (hw->autoneg_advertised & ADVERTISED_100baseT_Half)
357 mii_adv_data |= ADVERTISE_100HALF;
358 if (hw->autoneg_advertised & ADVERTISED_100baseT_Full)
359 mii_adv_data |= ADVERTISE_100FULL;
360
361 if (hw->autoneg_advertised & ADVERTISED_Autoneg)
362 mii_adv_data |= ADVERTISE_10HALF | ADVERTISE_10FULL |
363 ADVERTISE_100HALF | ADVERTISE_100FULL;
364
365 if (hw->link_cap_flags & ATL1C_LINK_CAP_1000M) {
366 if (hw->autoneg_advertised & ADVERTISED_1000baseT_Half)
367 mii_giga_ctrl_data |= ADVERTISE_1000HALF;
368 if (hw->autoneg_advertised & ADVERTISED_1000baseT_Full)
369 mii_giga_ctrl_data |= ADVERTISE_1000FULL;
370 if (hw->autoneg_advertised & ADVERTISED_Autoneg)
371 mii_giga_ctrl_data |= ADVERTISE_1000HALF |
372 ADVERTISE_1000FULL;
373 }
374
375 if (atl1c_write_phy_reg(hw, MII_ADVERTISE, mii_adv_data) != 0 ||
376 atl1c_write_phy_reg(hw, MII_CTRL1000, mii_giga_ctrl_data) != 0)
377 return -1;
378 return 0;
379}
380
381void atl1c_phy_disable(struct atl1c_hw *hw)
382{
383 AT_WRITE_REGW(hw, REG_GPHY_CTRL,
384 GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
385}
386
387static void atl1c_phy_magic_data(struct atl1c_hw *hw)
388{
389 u16 data;
390
391 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
392 ((1 & ANA_INTERVAL_SEL_TIMER_MASK) <<
393 ANA_INTERVAL_SEL_TIMER_SHIFT);
394
395 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_18);
396 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
397
398 data = (2 & ANA_SERDES_CDR_BW_MASK) | ANA_MS_PAD_DBG |
399 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
400 ANA_SERDES_EN_LCKDT;
401
402 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_5);
403 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
404
405 data = (44 & ANA_LONG_CABLE_TH_100_MASK) |
406 ((33 & ANA_SHORT_CABLE_TH_100_MASK) <<
407 ANA_SHORT_CABLE_TH_100_SHIFT) | ANA_BP_BAD_LINK_ACCUM |
408 ANA_BP_SMALL_BW;
409
410 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_54);
411 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
412
413 data = (11 & ANA_IECHO_ADJ_MASK) | ((11 & ANA_IECHO_ADJ_MASK) <<
414 ANA_IECHO_ADJ_2_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
415 ANA_IECHO_ADJ_1_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
416 ANA_IECHO_ADJ_0_SHIFT);
417
418 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_4);
419 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
420
421 data = ANA_RESTART_CAL | ((7 & ANA_MANUL_SWICH_ON_MASK) <<
422 ANA_MANUL_SWICH_ON_SHIFT) | ANA_MAN_ENABLE |
423 ANA_SEL_HSP | ANA_EN_HB | ANA_OEN_125M;
424
425 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_0);
426 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
427
428 if (hw->ctrl_flags & ATL1C_HIB_DISABLE) {
429 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_41);
430 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
431 return;
432 data &= ~ANA_TOP_PS_EN;
433 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
434
435 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_11);
436 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
437 return;
438 data &= ~ANA_PS_HIB_EN;
439 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
440 }
441}
442
443int atl1c_phy_reset(struct atl1c_hw *hw)
444{
445 struct atl1c_adapter *adapter = hw->adapter;
446 struct pci_dev *pdev = adapter->pdev;
447 u16 phy_data;
448 u32 phy_ctrl_data = GPHY_CTRL_DEFAULT;
449 u32 mii_ier_data = IER_LINK_UP | IER_LINK_DOWN;
450 int err;
451
452 if (hw->ctrl_flags & ATL1C_HIB_DISABLE)
453 phy_ctrl_data &= ~GPHY_CTRL_HIB_EN;
454
455 AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
456 AT_WRITE_FLUSH(hw);
457 msleep(40);
458 phy_ctrl_data |= GPHY_CTRL_EXT_RESET;
459 AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
460 AT_WRITE_FLUSH(hw);
461 msleep(10);
462
463 if (hw->nic_type == athr_l2c_b) {
464 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x0A);
465 atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
466 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data & 0xDFFF);
467 }
468
469 if (hw->nic_type == athr_l2c_b ||
470 hw->nic_type == athr_l2c_b2 ||
471 hw->nic_type == athr_l1d ||
472 hw->nic_type == athr_l1d_2) {
473 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
474 atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
475 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data & 0xFFF7);
476 msleep(20);
477 }
478 if (hw->nic_type == athr_l1d) {
479 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x29);
480 atl1c_write_phy_reg(hw, MII_DBG_DATA, 0x929D);
481 }
482 if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c_b2
483 || hw->nic_type == athr_l2c) {
484 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x29);
485 atl1c_write_phy_reg(hw, MII_DBG_DATA, 0xB6DD);
486 }
487 err = atl1c_write_phy_reg(hw, MII_IER, mii_ier_data);
488 if (err) {
489 if (netif_msg_hw(adapter))
490 dev_err(&pdev->dev,
491 "Error enable PHY linkChange Interrupt\n");
492 return err;
493 }
494 if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION))
495 atl1c_phy_magic_data(hw);
496 return 0;
497}
498
499int atl1c_phy_init(struct atl1c_hw *hw)
500{
501 struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
502 struct pci_dev *pdev = adapter->pdev;
503 int ret_val;
504 u16 mii_bmcr_data = BMCR_RESET;
505
506 if ((atl1c_read_phy_reg(hw, MII_PHYSID1, &hw->phy_id1) != 0) ||
507 (atl1c_read_phy_reg(hw, MII_PHYSID2, &hw->phy_id2) != 0)) {
508 dev_err(&pdev->dev, "Error get phy ID\n");
509 return -1;
510 }
511 switch (hw->media_type) {
512 case MEDIA_TYPE_AUTO_SENSOR:
513 ret_val = atl1c_phy_setup_adv(hw);
514 if (ret_val) {
515 if (netif_msg_link(adapter))
516 dev_err(&pdev->dev,
517 "Error Setting up Auto-Negotiation\n");
518 return ret_val;
519 }
520 mii_bmcr_data |= BMCR_ANENABLE | BMCR_ANRESTART;
521 break;
522 case MEDIA_TYPE_100M_FULL:
523 mii_bmcr_data |= BMCR_SPEED100 | BMCR_FULLDPLX;
524 break;
525 case MEDIA_TYPE_100M_HALF:
526 mii_bmcr_data |= BMCR_SPEED100;
527 break;
528 case MEDIA_TYPE_10M_FULL:
529 mii_bmcr_data |= BMCR_FULLDPLX;
530 break;
531 case MEDIA_TYPE_10M_HALF:
532 break;
533 default:
534 if (netif_msg_link(adapter))
535 dev_err(&pdev->dev, "Wrong Media type %d\n",
536 hw->media_type);
537 return -1;
538 break;
539 }
540
541 ret_val = atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
542 if (ret_val)
543 return ret_val;
544 hw->phy_configured = true;
545
546 return 0;
547}
548
549/*
550 * Detects the current speed and duplex settings of the hardware.
551 *
552 * hw - Struct containing variables accessed by shared code
553 * speed - Speed of the connection
554 * duplex - Duplex setting of the connection
555 */
556int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex)
557{
558 int err;
559 u16 phy_data;
560
561 /* Read PHY Specific Status Register (17) */
562 err = atl1c_read_phy_reg(hw, MII_GIGA_PSSR, &phy_data);
563 if (err)
564 return err;
565
566 if (!(phy_data & GIGA_PSSR_SPD_DPLX_RESOLVED))
567 return -1;
568
569 switch (phy_data & GIGA_PSSR_SPEED) {
570 case GIGA_PSSR_1000MBS:
571 *speed = SPEED_1000;
572 break;
573 case GIGA_PSSR_100MBS:
574 *speed = SPEED_100;
575 break;
576 case GIGA_PSSR_10MBS:
577 *speed = SPEED_10;
578 break;
579 default:
580 return -1;
581 break;
582 }
583
584 if (phy_data & GIGA_PSSR_DPLX)
585 *duplex = FULL_DUPLEX;
586 else
587 *duplex = HALF_DUPLEX;
588
589 return 0;
590}
591
592int atl1c_phy_power_saving(struct atl1c_hw *hw)
593{
594 struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
595 struct pci_dev *pdev = adapter->pdev;
596 int ret = 0;
597 u16 autoneg_advertised = ADVERTISED_10baseT_Half;
598 u16 save_autoneg_advertised;
599 u16 phy_data;
600 u16 mii_lpa_data;
601 u16 speed = SPEED_0;
602 u16 duplex = FULL_DUPLEX;
603 int i;
604
605 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
606 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
607 if (phy_data & BMSR_LSTATUS) {
608 atl1c_read_phy_reg(hw, MII_LPA, &mii_lpa_data);
609 if (mii_lpa_data & LPA_10FULL)
610 autoneg_advertised = ADVERTISED_10baseT_Full;
611 else if (mii_lpa_data & LPA_10HALF)
612 autoneg_advertised = ADVERTISED_10baseT_Half;
613 else if (mii_lpa_data & LPA_100HALF)
614 autoneg_advertised = ADVERTISED_100baseT_Half;
615 else if (mii_lpa_data & LPA_100FULL)
616 autoneg_advertised = ADVERTISED_100baseT_Full;
617
618 save_autoneg_advertised = hw->autoneg_advertised;
619 hw->phy_configured = false;
620 hw->autoneg_advertised = autoneg_advertised;
621 if (atl1c_restart_autoneg(hw) != 0) {
622 dev_dbg(&pdev->dev, "phy autoneg failed\n");
623 ret = -1;
624 }
625 hw->autoneg_advertised = save_autoneg_advertised;
626
627 if (mii_lpa_data) {
628 for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) {
629 mdelay(100);
630 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
631 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
632 if (phy_data & BMSR_LSTATUS) {
633 if (atl1c_get_speed_and_duplex(hw, &speed,
634 &duplex) != 0)
635 dev_dbg(&pdev->dev,
636 "get speed and duplex failed\n");
637 break;
638 }
639 }
640 }
641 } else {
642 speed = SPEED_10;
643 duplex = HALF_DUPLEX;
644 }
645 adapter->link_speed = speed;
646 adapter->link_duplex = duplex;
647
648 return ret;
649}
650
651int atl1c_restart_autoneg(struct atl1c_hw *hw)
652{
653 int err = 0;
654 u16 mii_bmcr_data = BMCR_RESET;
655
656 err = atl1c_phy_setup_adv(hw);
657 if (err)
658 return err;
659 mii_bmcr_data |= BMCR_ANENABLE | BMCR_ANRESTART;
660
661 return atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
662}
diff --git a/drivers/net/atl1c/atl1c_hw.h b/drivers/net/atl1c/atl1c_hw.h
deleted file mode 100644
index 655fc6c4a8a4..000000000000
--- a/drivers/net/atl1c/atl1c_hw.h
+++ /dev/null
@@ -1,868 +0,0 @@
1/*
2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef _ATL1C_HW_H_
23#define _ATL1C_HW_H_
24
25#include <linux/types.h>
26#include <linux/mii.h>
27
28struct atl1c_adapter;
29struct atl1c_hw;
30
31/* function prototype */
32void atl1c_phy_disable(struct atl1c_hw *hw);
33void atl1c_hw_set_mac_addr(struct atl1c_hw *hw);
34int atl1c_phy_reset(struct atl1c_hw *hw);
35int atl1c_read_mac_addr(struct atl1c_hw *hw);
36int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex);
37u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr);
38void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value);
39int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
40int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data);
41bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value);
42int atl1c_phy_init(struct atl1c_hw *hw);
43int atl1c_check_eeprom_exist(struct atl1c_hw *hw);
44int atl1c_restart_autoneg(struct atl1c_hw *hw);
45int atl1c_phy_power_saving(struct atl1c_hw *hw);
46/* register definition */
47#define REG_DEVICE_CAP 0x5C
48#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
49#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
50
51#define REG_DEVICE_CTRL 0x60
52#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
53#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
54#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
55#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
56
57#define REG_LINK_CTRL 0x68
58#define LINK_CTRL_L0S_EN 0x01
59#define LINK_CTRL_L1_EN 0x02
60#define LINK_CTRL_EXT_SYNC 0x80
61
62#define REG_VPD_CAP 0x6C
63#define VPD_CAP_ID_MASK 0xff
64#define VPD_CAP_ID_SHIFT 0
65#define VPD_CAP_NEXT_PTR_MASK 0xFF
66#define VPD_CAP_NEXT_PTR_SHIFT 8
67#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
68#define VPD_CAP_VPD_ADDR_SHIFT 16
69#define VPD_CAP_VPD_FLAG 0x80000000
70
71#define REG_VPD_DATA 0x70
72
73#define REG_PCIE_UC_SEVERITY 0x10C
74#define PCIE_UC_SERVRITY_TRN 0x00000001
75#define PCIE_UC_SERVRITY_DLP 0x00000010
76#define PCIE_UC_SERVRITY_PSN_TLP 0x00001000
77#define PCIE_UC_SERVRITY_FCP 0x00002000
78#define PCIE_UC_SERVRITY_CPL_TO 0x00004000
79#define PCIE_UC_SERVRITY_CA 0x00008000
80#define PCIE_UC_SERVRITY_UC 0x00010000
81#define PCIE_UC_SERVRITY_ROV 0x00020000
82#define PCIE_UC_SERVRITY_MLFP 0x00040000
83#define PCIE_UC_SERVRITY_ECRC 0x00080000
84#define PCIE_UC_SERVRITY_UR 0x00100000
85
86#define REG_DEV_SERIALNUM_CTRL 0x200
87#define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */
88#define REG_DEV_MAC_SEL_SHIFT 0
89#define REG_DEV_SERIAL_NUM_EN_MASK 0x1
90#define REG_DEV_SERIAL_NUM_EN_SHIFT 1
91
92#define REG_TWSI_CTRL 0x218
93#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
94#define TWSI_CTRL_LD_OFFSET_SHIFT 0
95#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
96#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
97#define TWSI_CTRL_SW_LDSTART 0x800
98#define TWSI_CTRL_HW_LDSTART 0x1000
99#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
100#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
101#define TWSI_CTRL_LD_EXIST 0x400000
102#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
103#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
104#define TWSI_CTRL_FREQ_SEL_100K 0
105#define TWSI_CTRL_FREQ_SEL_200K 1
106#define TWSI_CTRL_FREQ_SEL_300K 2
107#define TWSI_CTRL_FREQ_SEL_400K 3
108#define TWSI_CTRL_SMB_SLV_ADDR
109#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
110#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
111
112
113#define REG_PCIE_DEV_MISC_CTRL 0x21C
114#define PCIE_DEV_MISC_EXT_PIPE 0x2
115#define PCIE_DEV_MISC_RETRY_BUFDIS 0x1
116#define PCIE_DEV_MISC_SPIROM_EXIST 0x4
117#define PCIE_DEV_MISC_SERDES_ENDIAN 0x8
118#define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10
119
120#define REG_PCIE_PHYMISC 0x1000
121#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
122
123#define REG_PCIE_PHYMISC2 0x1004
124#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x3
125#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
126#define PCIE_PHYMISC2_SERDES_TH_MASK 0x3
127#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
128
129#define REG_TWSI_DEBUG 0x1108
130#define TWSI_DEBUG_DEV_EXIST 0x20000000
131
132#define REG_EEPROM_CTRL 0x12C0
133#define EEPROM_CTRL_DATA_HI_MASK 0xFFFF
134#define EEPROM_CTRL_DATA_HI_SHIFT 0
135#define EEPROM_CTRL_ADDR_MASK 0x3FF
136#define EEPROM_CTRL_ADDR_SHIFT 16
137#define EEPROM_CTRL_ACK 0x40000000
138#define EEPROM_CTRL_RW 0x80000000
139
140#define REG_EEPROM_DATA_LO 0x12C4
141
142#define REG_OTP_CTRL 0x12F0
143#define OTP_CTRL_CLK_EN 0x0002
144
145#define REG_PM_CTRL 0x12F8
146#define PM_CTRL_SDES_EN 0x00000001
147#define PM_CTRL_RBER_EN 0x00000002
148#define PM_CTRL_CLK_REQ_EN 0x00000004
149#define PM_CTRL_ASPM_L1_EN 0x00000008
150#define PM_CTRL_SERDES_L1_EN 0x00000010
151#define PM_CTRL_SERDES_PLL_L1_EN 0x00000020
152#define PM_CTRL_SERDES_PD_EX_L1 0x00000040
153#define PM_CTRL_SERDES_BUDS_RX_L1_EN 0x00000080
154#define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xF
155#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8
156#define PM_CTRL_ASPM_L0S_EN 0x00001000
157#define PM_CTRL_CLK_SWH_L1 0x00002000
158#define PM_CTRL_CLK_PWM_VER1_1 0x00004000
159#define PM_CTRL_RCVR_WT_TIMER 0x00008000
160#define PM_CTRL_L1_ENTRY_TIMER_MASK 0xF
161#define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16
162#define PM_CTRL_PM_REQ_TIMER_MASK 0xF
163#define PM_CTRL_PM_REQ_TIMER_SHIFT 20
164#define PM_CTRL_LCKDET_TIMER_MASK 0xF
165#define PM_CTRL_LCKDET_TIMER_SHIFT 24
166#define PM_CTRL_EN_BUFS_RX_L0S 0x10000000
167#define PM_CTRL_SA_DLY_EN 0x20000000
168#define PM_CTRL_MAC_ASPM_CHK 0x40000000
169#define PM_CTRL_HOTRST 0x80000000
170
171#define REG_LTSSM_ID_CTRL 0x12FC
172#define LTSSM_ID_EN_WRO 0x1000
173/* Selene Master Control Register */
174#define REG_MASTER_CTRL 0x1400
175#define MASTER_CTRL_SOFT_RST 0x1
176#define MASTER_CTRL_TEST_MODE_MASK 0x3
177#define MASTER_CTRL_TEST_MODE_SHIFT 2
178#define MASTER_CTRL_BERT_START 0x10
179#define MASTER_CTRL_OOB_DIS_OFF 0x40
180#define MASTER_CTRL_SA_TIMER_EN 0x80
181#define MASTER_CTRL_MTIMER_EN 0x100
182#define MASTER_CTRL_MANUAL_INT 0x200
183#define MASTER_CTRL_TX_ITIMER_EN 0x400
184#define MASTER_CTRL_RX_ITIMER_EN 0x800
185#define MASTER_CTRL_CLK_SEL_DIS 0x1000
186#define MASTER_CTRL_CLK_SWH_MODE 0x2000
187#define MASTER_CTRL_INT_RDCLR 0x4000
188#define MASTER_CTRL_REV_NUM_SHIFT 16
189#define MASTER_CTRL_REV_NUM_MASK 0xff
190#define MASTER_CTRL_DEV_ID_SHIFT 24
191#define MASTER_CTRL_DEV_ID_MASK 0x7f
192#define MASTER_CTRL_OTP_SEL 0x80000000
193
194/* Timer Initial Value Register */
195#define REG_MANUAL_TIMER_INIT 0x1404
196
197/* IRQ ModeratorTimer Initial Value Register */
198#define REG_IRQ_MODRT_TIMER_INIT 0x1408
199#define IRQ_MODRT_TIMER_MASK 0xffff
200#define IRQ_MODRT_TX_TIMER_SHIFT 0
201#define IRQ_MODRT_RX_TIMER_SHIFT 16
202
203#define REG_GPHY_CTRL 0x140C
204#define GPHY_CTRL_EXT_RESET 0x1
205#define GPHY_CTRL_RTL_MODE 0x2
206#define GPHY_CTRL_LED_MODE 0x4
207#define GPHY_CTRL_ANEG_NOW 0x8
208#define GPHY_CTRL_REV_ANEG 0x10
209#define GPHY_CTRL_GATE_25M_EN 0x20
210#define GPHY_CTRL_LPW_EXIT 0x40
211#define GPHY_CTRL_PHY_IDDQ 0x80
212#define GPHY_CTRL_PHY_IDDQ_DIS 0x100
213#define GPHY_CTRL_GIGA_DIS 0x200
214#define GPHY_CTRL_HIB_EN 0x400
215#define GPHY_CTRL_HIB_PULSE 0x800
216#define GPHY_CTRL_SEL_ANA_RST 0x1000
217#define GPHY_CTRL_PHY_PLL_ON 0x2000
218#define GPHY_CTRL_PWDOWN_HW 0x4000
219#define GPHY_CTRL_PHY_PLL_BYPASS 0x8000
220
221#define GPHY_CTRL_DEFAULT ( \
222 GPHY_CTRL_SEL_ANA_RST |\
223 GPHY_CTRL_HIB_PULSE |\
224 GPHY_CTRL_HIB_EN)
225
226#define GPHY_CTRL_PW_WOL_DIS ( \
227 GPHY_CTRL_SEL_ANA_RST |\
228 GPHY_CTRL_HIB_PULSE |\
229 GPHY_CTRL_HIB_EN |\
230 GPHY_CTRL_PWDOWN_HW |\
231 GPHY_CTRL_PHY_IDDQ)
232
233#define GPHY_CTRL_POWER_SAVING ( \
234 GPHY_CTRL_SEL_ANA_RST |\
235 GPHY_CTRL_HIB_EN |\
236 GPHY_CTRL_HIB_PULSE |\
237 GPHY_CTRL_PWDOWN_HW |\
238 GPHY_CTRL_PHY_IDDQ)
239/* Block IDLE Status Register */
240#define REG_IDLE_STATUS 0x1410
241#define IDLE_STATUS_MASK 0x00FF
242#define IDLE_STATUS_RXMAC_NO_IDLE 0x1
243#define IDLE_STATUS_TXMAC_NO_IDLE 0x2
244#define IDLE_STATUS_RXQ_NO_IDLE 0x4
245#define IDLE_STATUS_TXQ_NO_IDLE 0x8
246#define IDLE_STATUS_DMAR_NO_IDLE 0x10
247#define IDLE_STATUS_DMAW_NO_IDLE 0x20
248#define IDLE_STATUS_SMB_NO_IDLE 0x40
249#define IDLE_STATUS_CMB_NO_IDLE 0x80
250
251/* MDIO Control Register */
252#define REG_MDIO_CTRL 0x1414
253#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit
254 * control data to write to PHY
255 * MII management register */
256#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit
257 * status data that was read
258 * from the PHY MII management register */
259#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
260#define MDIO_REG_ADDR_SHIFT 16
261#define MDIO_RW 0x200000 /* 1: read, 0: write */
262#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
263#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO
264 * master. And this bit is self
265 * cleared after one cycle */
266#define MDIO_CLK_SEL_SHIFT 24
267#define MDIO_CLK_25_4 0
268#define MDIO_CLK_25_6 2
269#define MDIO_CLK_25_8 3
270#define MDIO_CLK_25_10 4
271#define MDIO_CLK_25_14 5
272#define MDIO_CLK_25_20 6
273#define MDIO_CLK_25_28 7
274#define MDIO_BUSY 0x8000000
275#define MDIO_AP_EN 0x10000000
276#define MDIO_WAIT_TIMES 10
277
278/* MII PHY Status Register */
279#define REG_PHY_STATUS 0x1418
280#define PHY_GENERAL_STATUS_MASK 0xFFFF
281#define PHY_STATUS_RECV_ENABLE 0x0001
282#define PHY_OE_PWSP_STATUS_MASK 0x07FF
283#define PHY_OE_PWSP_STATUS_SHIFT 16
284#define PHY_STATUS_LPW_STATE 0x80000000
285/* BIST Control and Status Register0 (for the Packet Memory) */
286#define REG_BIST0_CTRL 0x141c
287#define BIST0_NOW 0x1
288#define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is
289 * un-repairable because
290 * it has address decoder
291 * failure or more than 1 cell
292 * stuck-to-x failure */
293#define BIST0_FUSE_FLAG 0x4
294
295/* BIST Control and Status Register1(for the retry buffer of PCI Express) */
296#define REG_BIST1_CTRL 0x1420
297#define BIST1_NOW 0x1
298#define BIST1_SRAM_FAIL 0x2
299#define BIST1_FUSE_FLAG 0x4
300
301/* SerDes Lock Detect Control and Status Register */
302#define REG_SERDES_LOCK 0x1424
303#define SERDES_LOCK_DETECT 0x1 /* SerDes lock detected. This signal
304 * comes from Analog SerDes */
305#define SERDES_LOCK_DETECT_EN 0x2 /* 1: Enable SerDes Lock detect function */
306#define SERDES_LOCK_STS_SELFB_PLL_SHIFT 0xE
307#define SERDES_LOCK_STS_SELFB_PLL_MASK 0x3
308#define SERDES_OVCLK_18_25 0x0
309#define SERDES_OVCLK_12_18 0x1
310#define SERDES_OVCLK_0_4 0x2
311#define SERDES_OVCLK_4_12 0x3
312#define SERDES_MAC_CLK_SLOWDOWN 0x20000
313#define SERDES_PYH_CLK_SLOWDOWN 0x40000
314
315/* MAC Control Register */
316#define REG_MAC_CTRL 0x1480
317#define MAC_CTRL_TX_EN 0x1
318#define MAC_CTRL_RX_EN 0x2
319#define MAC_CTRL_TX_FLOW 0x4
320#define MAC_CTRL_RX_FLOW 0x8
321#define MAC_CTRL_LOOPBACK 0x10
322#define MAC_CTRL_DUPLX 0x20
323#define MAC_CTRL_ADD_CRC 0x40
324#define MAC_CTRL_PAD 0x80
325#define MAC_CTRL_LENCHK 0x100
326#define MAC_CTRL_HUGE_EN 0x200
327#define MAC_CTRL_PRMLEN_SHIFT 10
328#define MAC_CTRL_PRMLEN_MASK 0xf
329#define MAC_CTRL_RMV_VLAN 0x4000
330#define MAC_CTRL_PROMIS_EN 0x8000
331#define MAC_CTRL_TX_PAUSE 0x10000
332#define MAC_CTRL_SCNT 0x20000
333#define MAC_CTRL_SRST_TX 0x40000
334#define MAC_CTRL_TX_SIMURST 0x80000
335#define MAC_CTRL_SPEED_SHIFT 20
336#define MAC_CTRL_SPEED_MASK 0x3
337#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
338#define MAC_CTRL_TX_HUGE 0x800000
339#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
340#define MAC_CTRL_MC_ALL_EN 0x2000000
341#define MAC_CTRL_BC_EN 0x4000000
342#define MAC_CTRL_DBG 0x8000000
343#define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000
344#define MAC_CTRL_HASH_ALG_CRC32 0x20000000
345#define MAC_CTRL_SPEED_MODE_SW 0x40000000
346
347/* MAC IPG/IFG Control Register */
348#define REG_MAC_IPG_IFG 0x1484
349#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back
350 * inter-packet gap. The
351 * default is 96-bit time */
352#define MAC_IPG_IFG_IPGT_MASK 0x7f
353#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to
354 * enforce in between RX frames */
355#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
356#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
357#define MAC_IPG_IFG_IPGR1_MASK 0x7f
358#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
359#define MAC_IPG_IFG_IPGR2_MASK 0x7f
360
361/* MAC STATION ADDRESS */
362#define REG_MAC_STA_ADDR 0x1488
363
364/* Hash table for multicast address */
365#define REG_RX_HASH_TABLE 0x1490
366
367/* MAC Half-Duplex Control Register */
368#define REG_MAC_HALF_DUPLX_CTRL 0x1498
369#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
370#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
371#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
372#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
373#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
374#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
375#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure,
376 * immediately start the
377 * transmission after back pressure */
378#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
379#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */
380#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
381#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
382#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
383
384/* Maximum Frame Length Control Register */
385#define REG_MTU 0x149c
386
387/* Wake-On-Lan control register */
388#define REG_WOL_CTRL 0x14a0
389#define WOL_PATTERN_EN 0x00000001
390#define WOL_PATTERN_PME_EN 0x00000002
391#define WOL_MAGIC_EN 0x00000004
392#define WOL_MAGIC_PME_EN 0x00000008
393#define WOL_LINK_CHG_EN 0x00000010
394#define WOL_LINK_CHG_PME_EN 0x00000020
395#define WOL_PATTERN_ST 0x00000100
396#define WOL_MAGIC_ST 0x00000200
397#define WOL_LINKCHG_ST 0x00000400
398#define WOL_CLK_SWITCH_EN 0x00008000
399#define WOL_PT0_EN 0x00010000
400#define WOL_PT1_EN 0x00020000
401#define WOL_PT2_EN 0x00040000
402#define WOL_PT3_EN 0x00080000
403#define WOL_PT4_EN 0x00100000
404#define WOL_PT5_EN 0x00200000
405#define WOL_PT6_EN 0x00400000
406
407/* WOL Length ( 2 DWORD ) */
408#define REG_WOL_PATTERN_LEN 0x14a4
409#define WOL_PT_LEN_MASK 0x7f
410#define WOL_PT0_LEN_SHIFT 0
411#define WOL_PT1_LEN_SHIFT 8
412#define WOL_PT2_LEN_SHIFT 16
413#define WOL_PT3_LEN_SHIFT 24
414#define WOL_PT4_LEN_SHIFT 0
415#define WOL_PT5_LEN_SHIFT 8
416#define WOL_PT6_LEN_SHIFT 16
417
418/* Internal SRAM Partition Register */
419#define RFDX_HEAD_ADDR_MASK 0x03FF
420#define RFDX_HARD_ADDR_SHIFT 0
421#define RFDX_TAIL_ADDR_MASK 0x03FF
422#define RFDX_TAIL_ADDR_SHIFT 16
423
424#define REG_SRAM_RFD0_INFO 0x1500
425#define REG_SRAM_RFD1_INFO 0x1504
426#define REG_SRAM_RFD2_INFO 0x1508
427#define REG_SRAM_RFD3_INFO 0x150C
428
429#define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */
430#define RFD_NIC_LEN_MASK 0x03FF
431
432#define REG_SRAM_TRD_ADDR 0x1518
433#define TPD_HEAD_ADDR_MASK 0x03FF
434#define TPD_HEAD_ADDR_SHIFT 0
435#define TPD_TAIL_ADDR_MASK 0x03FF
436#define TPD_TAIL_ADDR_SHIFT 16
437
438#define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */
439#define TPD_NIC_LEN_MASK 0x03FF
440
441#define REG_SRAM_RXF_ADDR 0x1520
442#define REG_SRAM_RXF_LEN 0x1524
443#define REG_SRAM_TXF_ADDR 0x1528
444#define REG_SRAM_TXF_LEN 0x152C
445#define REG_SRAM_TCPH_ADDR 0x1530
446#define REG_SRAM_PKTH_ADDR 0x1532
447
448/*
449 * Load Ptr Register
450 * Software sets this bit after the initialization of the head and tail */
451#define REG_LOAD_PTR 0x1534
452
453/*
454 * addresses of all descriptors, as well as the following descriptor
455 * control register, which triggers each function block to load the head
456 * pointer to prepare for the operation. This bit is then self-cleared
457 * after one cycle.
458 */
459#define REG_RX_BASE_ADDR_HI 0x1540
460#define REG_TX_BASE_ADDR_HI 0x1544
461#define REG_SMB_BASE_ADDR_HI 0x1548
462#define REG_SMB_BASE_ADDR_LO 0x154C
463#define REG_RFD0_HEAD_ADDR_LO 0x1550
464#define REG_RFD1_HEAD_ADDR_LO 0x1554
465#define REG_RFD2_HEAD_ADDR_LO 0x1558
466#define REG_RFD3_HEAD_ADDR_LO 0x155C
467#define REG_RFD_RING_SIZE 0x1560
468#define RFD_RING_SIZE_MASK 0x0FFF
469#define REG_RX_BUF_SIZE 0x1564
470#define RX_BUF_SIZE_MASK 0xFFFF
471#define REG_RRD0_HEAD_ADDR_LO 0x1568
472#define REG_RRD1_HEAD_ADDR_LO 0x156C
473#define REG_RRD2_HEAD_ADDR_LO 0x1570
474#define REG_RRD3_HEAD_ADDR_LO 0x1574
475#define REG_RRD_RING_SIZE 0x1578
476#define RRD_RING_SIZE_MASK 0x0FFF
477#define REG_HTPD_HEAD_ADDR_LO 0x157C
478#define REG_NTPD_HEAD_ADDR_LO 0x1580
479#define REG_TPD_RING_SIZE 0x1584
480#define TPD_RING_SIZE_MASK 0xFFFF
481#define REG_CMB_BASE_ADDR_LO 0x1588
482
483/* RSS about */
484#define REG_RSS_KEY0 0x14B0
485#define REG_RSS_KEY1 0x14B4
486#define REG_RSS_KEY2 0x14B8
487#define REG_RSS_KEY3 0x14BC
488#define REG_RSS_KEY4 0x14C0
489#define REG_RSS_KEY5 0x14C4
490#define REG_RSS_KEY6 0x14C8
491#define REG_RSS_KEY7 0x14CC
492#define REG_RSS_KEY8 0x14D0
493#define REG_RSS_KEY9 0x14D4
494#define REG_IDT_TABLE0 0x14E0
495#define REG_IDT_TABLE1 0x14E4
496#define REG_IDT_TABLE2 0x14E8
497#define REG_IDT_TABLE3 0x14EC
498#define REG_IDT_TABLE4 0x14F0
499#define REG_IDT_TABLE5 0x14F4
500#define REG_IDT_TABLE6 0x14F8
501#define REG_IDT_TABLE7 0x14FC
502#define REG_IDT_TABLE REG_IDT_TABLE0
503#define REG_RSS_HASH_VALUE 0x15B0
504#define REG_RSS_HASH_FLAG 0x15B4
505#define REG_BASE_CPU_NUMBER 0x15B8
506
507/* TXQ Control Register */
508#define REG_TXQ_CTRL 0x1590
509#define TXQ_NUM_TPD_BURST_MASK 0xF
510#define TXQ_NUM_TPD_BURST_SHIFT 0
511#define TXQ_CTRL_IP_OPTION_EN 0x10
512#define TXQ_CTRL_EN 0x20
513#define TXQ_CTRL_ENH_MODE 0x40
514#define TXQ_CTRL_LS_8023_EN 0x80
515#define TXQ_TXF_BURST_NUM_SHIFT 16
516#define TXQ_TXF_BURST_NUM_MASK 0xFFFF
517
518/* Jumbo packet Threshold for task offload */
519#define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */
520#define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF
521
522#define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */
523#define TXF_WATER_MARK_MASK 0x0FFF
524#define TXF_LOW_WATER_MARK_SHIFT 0
525#define TXF_HIGH_WATER_MARK_SHIFT 16
526#define TXQ_CTRL_BURST_MODE_EN 0x80000000
527
528#define REG_THRUPUT_MON_CTRL 0x159C
529#define THRUPUT_MON_RATE_MASK 0x3
530#define THRUPUT_MON_RATE_SHIFT 0
531#define THRUPUT_MON_EN 0x80
532
533/* RXQ Control Register */
534#define REG_RXQ_CTRL 0x15A0
535#define ASPM_THRUPUT_LIMIT_MASK 0x3
536#define ASPM_THRUPUT_LIMIT_SHIFT 0
537#define ASPM_THRUPUT_LIMIT_NO 0x00
538#define ASPM_THRUPUT_LIMIT_1M 0x01
539#define ASPM_THRUPUT_LIMIT_10M 0x02
540#define ASPM_THRUPUT_LIMIT_100M 0x04
541#define RXQ1_CTRL_EN 0x10
542#define RXQ2_CTRL_EN 0x20
543#define RXQ3_CTRL_EN 0x40
544#define IPV6_CHKSUM_CTRL_EN 0x80
545#define RSS_HASH_BITS_MASK 0x00FF
546#define RSS_HASH_BITS_SHIFT 8
547#define RSS_HASH_IPV4 0x10000
548#define RSS_HASH_IPV4_TCP 0x20000
549#define RSS_HASH_IPV6 0x40000
550#define RSS_HASH_IPV6_TCP 0x80000
551#define RXQ_RFD_BURST_NUM_MASK 0x003F
552#define RXQ_RFD_BURST_NUM_SHIFT 20
553#define RSS_MODE_MASK 0x0003
554#define RSS_MODE_SHIFT 26
555#define RSS_NIP_QUEUE_SEL_MASK 0x1
556#define RSS_NIP_QUEUE_SEL_SHIFT 28
557#define RRS_HASH_CTRL_EN 0x20000000
558#define RX_CUT_THRU_EN 0x40000000
559#define RXQ_CTRL_EN 0x80000000
560
561#define REG_RFD_FREE_THRESH 0x15A4
562#define RFD_FREE_THRESH_MASK 0x003F
563#define RFD_FREE_HI_THRESH_SHIFT 0
564#define RFD_FREE_LO_THRESH_SHIFT 6
565
566/* RXF flow control register */
567#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
568#define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
569#define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF
570#define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
571#define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF
572
573#define REG_RXD_DMA_CTRL 0x15AC
574#define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */
575#define RXD_DMA_THRESH_SHIFT 0
576#define RXD_DMA_DOWN_TIMER_MASK 0xFFFF
577#define RXD_DMA_DOWN_TIMER_SHIFT 16
578
579/* DMA Engine Control Register */
580#define REG_DMA_CTRL 0x15C0
581#define DMA_CTRL_DMAR_IN_ORDER 0x1
582#define DMA_CTRL_DMAR_ENH_ORDER 0x2
583#define DMA_CTRL_DMAR_OUT_ORDER 0x4
584#define DMA_CTRL_RCB_VALUE 0x8
585#define DMA_CTRL_DMAR_BURST_LEN_MASK 0x0007
586#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
587#define DMA_CTRL_DMAW_BURST_LEN_MASK 0x0007
588#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
589#define DMA_CTRL_DMAR_REQ_PRI 0x400
590#define DMA_CTRL_DMAR_DLY_CNT_MASK 0x001F
591#define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
592#define DMA_CTRL_DMAW_DLY_CNT_MASK 0x000F
593#define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
594#define DMA_CTRL_CMB_EN 0x100000
595#define DMA_CTRL_SMB_EN 0x200000
596#define DMA_CTRL_CMB_NOW 0x400000
597#define MAC_CTRL_SMB_DIS 0x1000000
598#define DMA_CTRL_SMB_NOW 0x80000000
599
600/* CMB/SMB Control Register */
601#define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */
602#define SMB_STAT_TIMER_MASK 0xFFFFFF
603#define REG_CMB_TPD_THRESH 0x15C8
604#define CMB_TPD_THRESH_MASK 0xFFFF
605#define REG_CMB_TX_TIMER 0x15CC /* 2us resolution */
606#define CMB_TX_TIMER_MASK 0xFFFF
607
608/* Mail box */
609#define MB_RFDX_PROD_IDX_MASK 0xFFFF
610#define REG_MB_RFD0_PROD_IDX 0x15E0
611#define REG_MB_RFD1_PROD_IDX 0x15E4
612#define REG_MB_RFD2_PROD_IDX 0x15E8
613#define REG_MB_RFD3_PROD_IDX 0x15EC
614
615#define MB_PRIO_PROD_IDX_MASK 0xFFFF
616#define REG_MB_PRIO_PROD_IDX 0x15F0
617#define MB_HTPD_PROD_IDX_SHIFT 0
618#define MB_NTPD_PROD_IDX_SHIFT 16
619
620#define MB_PRIO_CONS_IDX_MASK 0xFFFF
621#define REG_MB_PRIO_CONS_IDX 0x15F4
622#define MB_HTPD_CONS_IDX_SHIFT 0
623#define MB_NTPD_CONS_IDX_SHIFT 16
624
625#define REG_MB_RFD01_CONS_IDX 0x15F8
626#define MB_RFD0_CONS_IDX_MASK 0x0000FFFF
627#define MB_RFD1_CONS_IDX_MASK 0xFFFF0000
628#define REG_MB_RFD23_CONS_IDX 0x15FC
629#define MB_RFD2_CONS_IDX_MASK 0x0000FFFF
630#define MB_RFD3_CONS_IDX_MASK 0xFFFF0000
631
632/* Interrupt Status Register */
633#define REG_ISR 0x1600
634#define ISR_SMB 0x00000001
635#define ISR_TIMER 0x00000002
636/*
637 * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
638 * in Table 51 Selene Master Control Register (Offset 0x1400).
639 */
640#define ISR_MANUAL 0x00000004
641#define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */
642#define ISR_RFD0_UR 0x00000010 /* RFD0 under run */
643#define ISR_RFD1_UR 0x00000020
644#define ISR_RFD2_UR 0x00000040
645#define ISR_RFD3_UR 0x00000080
646#define ISR_TXF_UR 0x00000100
647#define ISR_DMAR_TO_RST 0x00000200
648#define ISR_DMAW_TO_RST 0x00000400
649#define ISR_TX_CREDIT 0x00000800
650#define ISR_GPHY 0x00001000
651/* GPHY low power state interrupt */
652#define ISR_GPHY_LPW 0x00002000
653#define ISR_TXQ_TO_RST 0x00004000
654#define ISR_TX_PKT 0x00008000
655#define ISR_RX_PKT_0 0x00010000
656#define ISR_RX_PKT_1 0x00020000
657#define ISR_RX_PKT_2 0x00040000
658#define ISR_RX_PKT_3 0x00080000
659#define ISR_MAC_RX 0x00100000
660#define ISR_MAC_TX 0x00200000
661#define ISR_UR_DETECTED 0x00400000
662#define ISR_FERR_DETECTED 0x00800000
663#define ISR_NFERR_DETECTED 0x01000000
664#define ISR_CERR_DETECTED 0x02000000
665#define ISR_PHY_LINKDOWN 0x04000000
666#define ISR_DIS_INT 0x80000000
667
668/* Interrupt Mask Register */
669#define REG_IMR 0x1604
670
671#define IMR_NORMAL_MASK (\
672 ISR_MANUAL |\
673 ISR_HW_RXF_OV |\
674 ISR_RFD0_UR |\
675 ISR_TXF_UR |\
676 ISR_DMAR_TO_RST |\
677 ISR_TXQ_TO_RST |\
678 ISR_DMAW_TO_RST |\
679 ISR_GPHY |\
680 ISR_TX_PKT |\
681 ISR_RX_PKT_0 |\
682 ISR_GPHY_LPW |\
683 ISR_PHY_LINKDOWN)
684
685#define ISR_RX_PKT (\
686 ISR_RX_PKT_0 |\
687 ISR_RX_PKT_1 |\
688 ISR_RX_PKT_2 |\
689 ISR_RX_PKT_3)
690
691#define ISR_OVER (\
692 ISR_RFD0_UR |\
693 ISR_RFD1_UR |\
694 ISR_RFD2_UR |\
695 ISR_RFD3_UR |\
696 ISR_HW_RXF_OV |\
697 ISR_TXF_UR)
698
699#define ISR_ERROR (\
700 ISR_DMAR_TO_RST |\
701 ISR_TXQ_TO_RST |\
702 ISR_DMAW_TO_RST |\
703 ISR_PHY_LINKDOWN)
704
705#define REG_INT_RETRIG_TIMER 0x1608
706#define INT_RETRIG_TIMER_MASK 0xFFFF
707
708#define REG_HDS_CTRL 0x160C
709#define HDS_CTRL_EN 0x0001
710#define HDS_CTRL_BACKFILLSIZE_SHIFT 8
711#define HDS_CTRL_BACKFILLSIZE_MASK 0x0FFF
712#define HDS_CTRL_MAX_HDRSIZE_SHIFT 20
713#define HDS_CTRL_MAC_HDRSIZE_MASK 0x0FFF
714
715#define REG_MAC_RX_STATUS_BIN 0x1700
716#define REG_MAC_RX_STATUS_END 0x175c
717#define REG_MAC_TX_STATUS_BIN 0x1760
718#define REG_MAC_TX_STATUS_END 0x17c0
719
720#define REG_CLK_GATING_CTRL 0x1814
721#define CLK_GATING_DMAW_EN 0x0001
722#define CLK_GATING_DMAR_EN 0x0002
723#define CLK_GATING_TXQ_EN 0x0004
724#define CLK_GATING_RXQ_EN 0x0008
725#define CLK_GATING_TXMAC_EN 0x0010
726#define CLK_GATING_RXMAC_EN 0x0020
727
728#define CLK_GATING_EN_ALL (CLK_GATING_DMAW_EN |\
729 CLK_GATING_DMAR_EN |\
730 CLK_GATING_TXQ_EN |\
731 CLK_GATING_RXQ_EN |\
732 CLK_GATING_TXMAC_EN|\
733 CLK_GATING_RXMAC_EN)
734
735/* DEBUG ADDR */
736#define REG_DEBUG_DATA0 0x1900
737#define REG_DEBUG_DATA1 0x1904
738
739#define L1D_MPW_PHYID1 0xD01C /* V7 */
740#define L1D_MPW_PHYID2 0xD01D /* V1-V6 */
741#define L1D_MPW_PHYID3 0xD01E /* V8 */
742
743
744/* Autoneg Advertisement Register */
745#define ADVERTISE_DEFAULT_CAP \
746 (ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)
747
748/* 1000BASE-T Control Register */
749#define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */
750
751#define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
752#define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
753#define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
754#define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
755#define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
756#define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
757#define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
758#define GIGA_CR_1000T_SPEED_MASK 0x0300
759#define GIGA_CR_1000T_DEFAULT_CAP 0x0300
760
761/* PHY Specific Status Register */
762#define MII_GIGA_PSSR 0x11
763#define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
764#define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
765#define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
766#define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */
767#define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */
768#define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
769
770/* PHY Interrupt Enable Register */
771#define MII_IER 0x12
772#define IER_LINK_UP 0x0400
773#define IER_LINK_DOWN 0x0800
774
775/* PHY Interrupt Status Register */
776#define MII_ISR 0x13
777#define ISR_LINK_UP 0x0400
778#define ISR_LINK_DOWN 0x0800
779
780/* Cable-Detect-Test Control Register */
781#define MII_CDTC 0x16
782#define CDTC_EN_OFF 0 /* sc */
783#define CDTC_EN_BITS 1
784#define CDTC_PAIR_OFF 8
785#define CDTC_PAIR_BIT 2
786
787/* Cable-Detect-Test Status Register */
788#define MII_CDTS 0x1C
789#define CDTS_STATUS_OFF 8
790#define CDTS_STATUS_BITS 2
791#define CDTS_STATUS_NORMAL 0
792#define CDTS_STATUS_SHORT 1
793#define CDTS_STATUS_OPEN 2
794#define CDTS_STATUS_INVALID 3
795
796#define MII_DBG_ADDR 0x1D
797#define MII_DBG_DATA 0x1E
798
799#define MII_ANA_CTRL_0 0x0
800#define ANA_RESTART_CAL 0x0001
801#define ANA_MANUL_SWICH_ON_SHIFT 0x1
802#define ANA_MANUL_SWICH_ON_MASK 0xF
803#define ANA_MAN_ENABLE 0x0020
804#define ANA_SEL_HSP 0x0040
805#define ANA_EN_HB 0x0080
806#define ANA_EN_HBIAS 0x0100
807#define ANA_OEN_125M 0x0200
808#define ANA_EN_LCKDT 0x0400
809#define ANA_LCKDT_PHY 0x0800
810#define ANA_AFE_MODE 0x1000
811#define ANA_VCO_SLOW 0x2000
812#define ANA_VCO_FAST 0x4000
813#define ANA_SEL_CLK125M_DSP 0x8000
814
815#define MII_ANA_CTRL_4 0x4
816#define ANA_IECHO_ADJ_MASK 0xF
817#define ANA_IECHO_ADJ_3_SHIFT 0
818#define ANA_IECHO_ADJ_2_SHIFT 4
819#define ANA_IECHO_ADJ_1_SHIFT 8
820#define ANA_IECHO_ADJ_0_SHIFT 12
821
822#define MII_ANA_CTRL_5 0x5
823#define ANA_SERDES_CDR_BW_SHIFT 0
824#define ANA_SERDES_CDR_BW_MASK 0x3
825#define ANA_MS_PAD_DBG 0x0004
826#define ANA_SPEEDUP_DBG 0x0008
827#define ANA_SERDES_TH_LOS_SHIFT 4
828#define ANA_SERDES_TH_LOS_MASK 0x3
829#define ANA_SERDES_EN_DEEM 0x0040
830#define ANA_SERDES_TXELECIDLE 0x0080
831#define ANA_SERDES_BEACON 0x0100
832#define ANA_SERDES_HALFTXDR 0x0200
833#define ANA_SERDES_SEL_HSP 0x0400
834#define ANA_SERDES_EN_PLL 0x0800
835#define ANA_SERDES_EN 0x1000
836#define ANA_SERDES_EN_LCKDT 0x2000
837
838#define MII_ANA_CTRL_11 0xB
839#define ANA_PS_HIB_EN 0x8000
840
841#define MII_ANA_CTRL_18 0x12
842#define ANA_TEST_MODE_10BT_01SHIFT 0
843#define ANA_TEST_MODE_10BT_01MASK 0x3
844#define ANA_LOOP_SEL_10BT 0x0004
845#define ANA_RGMII_MODE_SW 0x0008
846#define ANA_EN_LONGECABLE 0x0010
847#define ANA_TEST_MODE_10BT_2 0x0020
848#define ANA_EN_10BT_IDLE 0x0400
849#define ANA_EN_MASK_TB 0x0800
850#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
851#define ANA_TRIGGER_SEL_TIMER_MASK 0x3
852#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
853#define ANA_INTERVAL_SEL_TIMER_MASK 0x3
854
855#define MII_ANA_CTRL_41 0x29
856#define ANA_TOP_PS_EN 0x8000
857
858#define MII_ANA_CTRL_54 0x36
859#define ANA_LONG_CABLE_TH_100_SHIFT 0
860#define ANA_LONG_CABLE_TH_100_MASK 0x3F
861#define ANA_DESERVED 0x0040
862#define ANA_EN_LIT_CH 0x0080
863#define ANA_SHORT_CABLE_TH_100_SHIFT 8
864#define ANA_SHORT_CABLE_TH_100_MASK 0x3F
865#define ANA_BP_BAD_LINK_ACCUM 0x4000
866#define ANA_BP_SMALL_BW 0x8000
867
868#endif /*_ATL1C_HW_H_*/
diff --git a/drivers/net/atl1c/atl1c_main.c b/drivers/net/atl1c/atl1c_main.c
deleted file mode 100644
index 972244218408..000000000000
--- a/drivers/net/atl1c/atl1c_main.c
+++ /dev/null
@@ -1,2934 +0,0 @@
1/*
2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "atl1c.h"
23
24#define ATL1C_DRV_VERSION "1.0.1.0-NAPI"
25char atl1c_driver_name[] = "atl1c";
26char atl1c_driver_version[] = ATL1C_DRV_VERSION;
27#define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
28#define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
29#define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
30#define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
31#define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
32#define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
33#define L2CB_V10 0xc0
34#define L2CB_V11 0xc1
35
36/*
37 * atl1c_pci_tbl - PCI Device ID Table
38 *
39 * Wildcard entries (PCI_ANY_ID) should come last
40 * Last entry must be all 0s
41 *
42 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
43 * Class, Class Mask, private data (not used) }
44 */
45static DEFINE_PCI_DEVICE_TABLE(atl1c_pci_tbl) = {
46 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
47 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
48 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
49 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
50 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
51 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D_2_0)},
52 /* required last entry */
53 { 0 }
54};
55MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
56
57MODULE_AUTHOR("Jie Yang <jie.yang@atheros.com>");
58MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
59MODULE_LICENSE("GPL");
60MODULE_VERSION(ATL1C_DRV_VERSION);
61
62static int atl1c_stop_mac(struct atl1c_hw *hw);
63static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw);
64static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw);
65static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
66static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup);
67static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter);
68static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
69 int *work_done, int work_to_do);
70static int atl1c_up(struct atl1c_adapter *adapter);
71static void atl1c_down(struct atl1c_adapter *adapter);
72
73static const u16 atl1c_pay_load_size[] = {
74 128, 256, 512, 1024, 2048, 4096,
75};
76
77static const u16 atl1c_rfd_prod_idx_regs[AT_MAX_RECEIVE_QUEUE] =
78{
79 REG_MB_RFD0_PROD_IDX,
80 REG_MB_RFD1_PROD_IDX,
81 REG_MB_RFD2_PROD_IDX,
82 REG_MB_RFD3_PROD_IDX
83};
84
85static const u16 atl1c_rfd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
86{
87 REG_RFD0_HEAD_ADDR_LO,
88 REG_RFD1_HEAD_ADDR_LO,
89 REG_RFD2_HEAD_ADDR_LO,
90 REG_RFD3_HEAD_ADDR_LO
91};
92
93static const u16 atl1c_rrd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
94{
95 REG_RRD0_HEAD_ADDR_LO,
96 REG_RRD1_HEAD_ADDR_LO,
97 REG_RRD2_HEAD_ADDR_LO,
98 REG_RRD3_HEAD_ADDR_LO
99};
100
101static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
102 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
103static void atl1c_pcie_patch(struct atl1c_hw *hw)
104{
105 u32 data;
106
107 AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
108 data |= PCIE_PHYMISC_FORCE_RCV_DET;
109 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
110
111 if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
112 AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
113
114 data &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK <<
115 PCIE_PHYMISC2_SERDES_CDR_SHIFT);
116 data |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
117 data &= ~(PCIE_PHYMISC2_SERDES_TH_MASK <<
118 PCIE_PHYMISC2_SERDES_TH_SHIFT);
119 data |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
120 AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
121 }
122}
123
124/* FIXME: no need any more ? */
125/*
126 * atl1c_init_pcie - init PCIE module
127 */
128static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
129{
130 u32 data;
131 u32 pci_cmd;
132 struct pci_dev *pdev = hw->adapter->pdev;
133
134 AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
135 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
136 pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
137 PCI_COMMAND_IO);
138 AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
139
140 /*
141 * Clear any PowerSaveing Settings
142 */
143 pci_enable_wake(pdev, PCI_D3hot, 0);
144 pci_enable_wake(pdev, PCI_D3cold, 0);
145
146 /*
147 * Mask some pcie error bits
148 */
149 AT_READ_REG(hw, REG_PCIE_UC_SEVERITY, &data);
150 data &= ~PCIE_UC_SERVRITY_DLP;
151 data &= ~PCIE_UC_SERVRITY_FCP;
152 AT_WRITE_REG(hw, REG_PCIE_UC_SEVERITY, data);
153
154 AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
155 data &= ~LTSSM_ID_EN_WRO;
156 AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
157
158 atl1c_pcie_patch(hw);
159 if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
160 atl1c_disable_l0s_l1(hw);
161 if (flag & ATL1C_PCIE_PHY_RESET)
162 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
163 else
164 AT_WRITE_REG(hw, REG_GPHY_CTRL,
165 GPHY_CTRL_DEFAULT | GPHY_CTRL_EXT_RESET);
166
167 msleep(5);
168}
169
170/*
171 * atl1c_irq_enable - Enable default interrupt generation settings
172 * @adapter: board private structure
173 */
174static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
175{
176 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
177 AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
178 AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
179 AT_WRITE_FLUSH(&adapter->hw);
180 }
181}
182
183/*
184 * atl1c_irq_disable - Mask off interrupt generation on the NIC
185 * @adapter: board private structure
186 */
187static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
188{
189 atomic_inc(&adapter->irq_sem);
190 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
191 AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
192 AT_WRITE_FLUSH(&adapter->hw);
193 synchronize_irq(adapter->pdev->irq);
194}
195
196/*
197 * atl1c_irq_reset - reset interrupt confiure on the NIC
198 * @adapter: board private structure
199 */
200static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
201{
202 atomic_set(&adapter->irq_sem, 1);
203 atl1c_irq_enable(adapter);
204}
205
206/*
207 * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
208 * of the idle status register until the device is actually idle
209 */
210static u32 atl1c_wait_until_idle(struct atl1c_hw *hw)
211{
212 int timeout;
213 u32 data;
214
215 for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
216 AT_READ_REG(hw, REG_IDLE_STATUS, &data);
217 if ((data & IDLE_STATUS_MASK) == 0)
218 return 0;
219 msleep(1);
220 }
221 return data;
222}
223
224/*
225 * atl1c_phy_config - Timer Call-back
226 * @data: pointer to netdev cast into an unsigned long
227 */
228static void atl1c_phy_config(unsigned long data)
229{
230 struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
231 struct atl1c_hw *hw = &adapter->hw;
232 unsigned long flags;
233
234 spin_lock_irqsave(&adapter->mdio_lock, flags);
235 atl1c_restart_autoneg(hw);
236 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
237}
238
239void atl1c_reinit_locked(struct atl1c_adapter *adapter)
240{
241 WARN_ON(in_interrupt());
242 atl1c_down(adapter);
243 atl1c_up(adapter);
244 clear_bit(__AT_RESETTING, &adapter->flags);
245}
246
247static void atl1c_check_link_status(struct atl1c_adapter *adapter)
248{
249 struct atl1c_hw *hw = &adapter->hw;
250 struct net_device *netdev = adapter->netdev;
251 struct pci_dev *pdev = adapter->pdev;
252 int err;
253 unsigned long flags;
254 u16 speed, duplex, phy_data;
255
256 spin_lock_irqsave(&adapter->mdio_lock, flags);
257 /* MII_BMSR must read twise */
258 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
259 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
260 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
261
262 if ((phy_data & BMSR_LSTATUS) == 0) {
263 /* link down */
264 hw->hibernate = true;
265 if (atl1c_stop_mac(hw) != 0)
266 if (netif_msg_hw(adapter))
267 dev_warn(&pdev->dev, "stop mac failed\n");
268 atl1c_set_aspm(hw, false);
269 netif_carrier_off(netdev);
270 netif_stop_queue(netdev);
271 atl1c_phy_reset(hw);
272 atl1c_phy_init(&adapter->hw);
273 } else {
274 /* Link Up */
275 hw->hibernate = false;
276 spin_lock_irqsave(&adapter->mdio_lock, flags);
277 err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
278 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
279 if (unlikely(err))
280 return;
281 /* link result is our setting */
282 if (adapter->link_speed != speed ||
283 adapter->link_duplex != duplex) {
284 adapter->link_speed = speed;
285 adapter->link_duplex = duplex;
286 atl1c_set_aspm(hw, true);
287 atl1c_enable_tx_ctrl(hw);
288 atl1c_enable_rx_ctrl(hw);
289 atl1c_setup_mac_ctrl(adapter);
290 if (netif_msg_link(adapter))
291 dev_info(&pdev->dev,
292 "%s: %s NIC Link is Up<%d Mbps %s>\n",
293 atl1c_driver_name, netdev->name,
294 adapter->link_speed,
295 adapter->link_duplex == FULL_DUPLEX ?
296 "Full Duplex" : "Half Duplex");
297 }
298 if (!netif_carrier_ok(netdev))
299 netif_carrier_on(netdev);
300 }
301}
302
303static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct pci_dev *pdev = adapter->pdev;
307 u16 phy_data;
308 u16 link_up;
309
310 spin_lock(&adapter->mdio_lock);
311 atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
312 atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
313 spin_unlock(&adapter->mdio_lock);
314 link_up = phy_data & BMSR_LSTATUS;
315 /* notify upper layer link down ASAP */
316 if (!link_up) {
317 if (netif_carrier_ok(netdev)) {
318 /* old link state: Up */
319 netif_carrier_off(netdev);
320 if (netif_msg_link(adapter))
321 dev_info(&pdev->dev,
322 "%s: %s NIC Link is Down\n",
323 atl1c_driver_name, netdev->name);
324 adapter->link_speed = SPEED_0;
325 }
326 }
327
328 set_bit(ATL1C_WORK_EVENT_LINK_CHANGE, &adapter->work_event);
329 schedule_work(&adapter->common_task);
330}
331
332static void atl1c_common_task(struct work_struct *work)
333{
334 struct atl1c_adapter *adapter;
335 struct net_device *netdev;
336
337 adapter = container_of(work, struct atl1c_adapter, common_task);
338 netdev = adapter->netdev;
339
340 if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
341 netif_device_detach(netdev);
342 atl1c_down(adapter);
343 atl1c_up(adapter);
344 netif_device_attach(netdev);
345 }
346
347 if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
348 &adapter->work_event))
349 atl1c_check_link_status(adapter);
350}
351
352
353static void atl1c_del_timer(struct atl1c_adapter *adapter)
354{
355 del_timer_sync(&adapter->phy_config_timer);
356}
357
358
359/*
360 * atl1c_tx_timeout - Respond to a Tx Hang
361 * @netdev: network interface device structure
362 */
363static void atl1c_tx_timeout(struct net_device *netdev)
364{
365 struct atl1c_adapter *adapter = netdev_priv(netdev);
366
367 /* Do the reset outside of interrupt context */
368 set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
369 schedule_work(&adapter->common_task);
370}
371
372/*
373 * atl1c_set_multi - Multicast and Promiscuous mode set
374 * @netdev: network interface device structure
375 *
376 * The set_multi entry point is called whenever the multicast address
377 * list or the network interface flags are updated. This routine is
378 * responsible for configuring the hardware for proper multicast,
379 * promiscuous mode, and all-multi behavior.
380 */
381static void atl1c_set_multi(struct net_device *netdev)
382{
383 struct atl1c_adapter *adapter = netdev_priv(netdev);
384 struct atl1c_hw *hw = &adapter->hw;
385 struct netdev_hw_addr *ha;
386 u32 mac_ctrl_data;
387 u32 hash_value;
388
389 /* Check for Promiscuous and All Multicast modes */
390 AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
391
392 if (netdev->flags & IFF_PROMISC) {
393 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
394 } else if (netdev->flags & IFF_ALLMULTI) {
395 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
396 mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
397 } else {
398 mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
399 }
400
401 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
402
403 /* clear the old settings from the multicast hash table */
404 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
405 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
406
407 /* comoute mc addresses' hash value ,and put it into hash table */
408 netdev_for_each_mc_addr(ha, netdev) {
409 hash_value = atl1c_hash_mc_addr(hw, ha->addr);
410 atl1c_hash_set(hw, hash_value);
411 }
412}
413
414static void __atl1c_vlan_mode(u32 features, u32 *mac_ctrl_data)
415{
416 if (features & NETIF_F_HW_VLAN_RX) {
417 /* enable VLAN tag insert/strip */
418 *mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
419 } else {
420 /* disable VLAN tag insert/strip */
421 *mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
422 }
423}
424
425static void atl1c_vlan_mode(struct net_device *netdev, u32 features)
426{
427 struct atl1c_adapter *adapter = netdev_priv(netdev);
428 struct pci_dev *pdev = adapter->pdev;
429 u32 mac_ctrl_data = 0;
430
431 if (netif_msg_pktdata(adapter))
432 dev_dbg(&pdev->dev, "atl1c_vlan_mode\n");
433
434 atl1c_irq_disable(adapter);
435 AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
436 __atl1c_vlan_mode(features, &mac_ctrl_data);
437 AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
438 atl1c_irq_enable(adapter);
439}
440
441static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
442{
443 struct pci_dev *pdev = adapter->pdev;
444
445 if (netif_msg_pktdata(adapter))
446 dev_dbg(&pdev->dev, "atl1c_restore_vlan\n");
447 atl1c_vlan_mode(adapter->netdev, adapter->netdev->features);
448}
449
450/*
451 * atl1c_set_mac - Change the Ethernet Address of the NIC
452 * @netdev: network interface device structure
453 * @p: pointer to an address structure
454 *
455 * Returns 0 on success, negative on failure
456 */
457static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
458{
459 struct atl1c_adapter *adapter = netdev_priv(netdev);
460 struct sockaddr *addr = p;
461
462 if (!is_valid_ether_addr(addr->sa_data))
463 return -EADDRNOTAVAIL;
464
465 if (netif_running(netdev))
466 return -EBUSY;
467
468 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
469 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
470
471 atl1c_hw_set_mac_addr(&adapter->hw);
472
473 return 0;
474}
475
476static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
477 struct net_device *dev)
478{
479 int mtu = dev->mtu;
480
481 adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
482 roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
483}
484
485static u32 atl1c_fix_features(struct net_device *netdev, u32 features)
486{
487 /*
488 * Since there is no support for separate rx/tx vlan accel
489 * enable/disable make sure tx flag is always in same state as rx.
490 */
491 if (features & NETIF_F_HW_VLAN_RX)
492 features |= NETIF_F_HW_VLAN_TX;
493 else
494 features &= ~NETIF_F_HW_VLAN_TX;
495
496 if (netdev->mtu > MAX_TSO_FRAME_SIZE)
497 features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
498
499 return features;
500}
501
502static int atl1c_set_features(struct net_device *netdev, u32 features)
503{
504 u32 changed = netdev->features ^ features;
505
506 if (changed & NETIF_F_HW_VLAN_RX)
507 atl1c_vlan_mode(netdev, features);
508
509 return 0;
510}
511
512/*
513 * atl1c_change_mtu - Change the Maximum Transfer Unit
514 * @netdev: network interface device structure
515 * @new_mtu: new value for maximum frame size
516 *
517 * Returns 0 on success, negative on failure
518 */
519static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
520{
521 struct atl1c_adapter *adapter = netdev_priv(netdev);
522 int old_mtu = netdev->mtu;
523 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
524
525 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
526 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
527 if (netif_msg_link(adapter))
528 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
529 return -EINVAL;
530 }
531 /* set MTU */
532 if (old_mtu != new_mtu && netif_running(netdev)) {
533 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
534 msleep(1);
535 netdev->mtu = new_mtu;
536 adapter->hw.max_frame_size = new_mtu;
537 atl1c_set_rxbufsize(adapter, netdev);
538 atl1c_down(adapter);
539 netdev_update_features(netdev);
540 atl1c_up(adapter);
541 clear_bit(__AT_RESETTING, &adapter->flags);
542 if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
543 u32 phy_data;
544
545 AT_READ_REG(&adapter->hw, 0x1414, &phy_data);
546 phy_data |= 0x10000000;
547 AT_WRITE_REG(&adapter->hw, 0x1414, phy_data);
548 }
549
550 }
551 return 0;
552}
553
554/*
555 * caller should hold mdio_lock
556 */
557static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
558{
559 struct atl1c_adapter *adapter = netdev_priv(netdev);
560 u16 result;
561
562 atl1c_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
563 return result;
564}
565
566static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
567 int reg_num, int val)
568{
569 struct atl1c_adapter *adapter = netdev_priv(netdev);
570
571 atl1c_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
572}
573
574/*
575 * atl1c_mii_ioctl -
576 * @netdev:
577 * @ifreq:
578 * @cmd:
579 */
580static int atl1c_mii_ioctl(struct net_device *netdev,
581 struct ifreq *ifr, int cmd)
582{
583 struct atl1c_adapter *adapter = netdev_priv(netdev);
584 struct pci_dev *pdev = adapter->pdev;
585 struct mii_ioctl_data *data = if_mii(ifr);
586 unsigned long flags;
587 int retval = 0;
588
589 if (!netif_running(netdev))
590 return -EINVAL;
591
592 spin_lock_irqsave(&adapter->mdio_lock, flags);
593 switch (cmd) {
594 case SIOCGMIIPHY:
595 data->phy_id = 0;
596 break;
597
598 case SIOCGMIIREG:
599 if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
600 &data->val_out)) {
601 retval = -EIO;
602 goto out;
603 }
604 break;
605
606 case SIOCSMIIREG:
607 if (data->reg_num & ~(0x1F)) {
608 retval = -EFAULT;
609 goto out;
610 }
611
612 dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
613 data->reg_num, data->val_in);
614 if (atl1c_write_phy_reg(&adapter->hw,
615 data->reg_num, data->val_in)) {
616 retval = -EIO;
617 goto out;
618 }
619 break;
620
621 default:
622 retval = -EOPNOTSUPP;
623 break;
624 }
625out:
626 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
627 return retval;
628}
629
630/*
631 * atl1c_ioctl -
632 * @netdev:
633 * @ifreq:
634 * @cmd:
635 */
636static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
637{
638 switch (cmd) {
639 case SIOCGMIIPHY:
640 case SIOCGMIIREG:
641 case SIOCSMIIREG:
642 return atl1c_mii_ioctl(netdev, ifr, cmd);
643 default:
644 return -EOPNOTSUPP;
645 }
646}
647
648/*
649 * atl1c_alloc_queues - Allocate memory for all rings
650 * @adapter: board private structure to initialize
651 *
652 */
653static int __devinit atl1c_alloc_queues(struct atl1c_adapter *adapter)
654{
655 return 0;
656}
657
658static void atl1c_set_mac_type(struct atl1c_hw *hw)
659{
660 switch (hw->device_id) {
661 case PCI_DEVICE_ID_ATTANSIC_L2C:
662 hw->nic_type = athr_l2c;
663 break;
664 case PCI_DEVICE_ID_ATTANSIC_L1C:
665 hw->nic_type = athr_l1c;
666 break;
667 case PCI_DEVICE_ID_ATHEROS_L2C_B:
668 hw->nic_type = athr_l2c_b;
669 break;
670 case PCI_DEVICE_ID_ATHEROS_L2C_B2:
671 hw->nic_type = athr_l2c_b2;
672 break;
673 case PCI_DEVICE_ID_ATHEROS_L1D:
674 hw->nic_type = athr_l1d;
675 break;
676 case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
677 hw->nic_type = athr_l1d_2;
678 break;
679 default:
680 break;
681 }
682}
683
684static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
685{
686 u32 phy_status_data;
687 u32 link_ctrl_data;
688
689 atl1c_set_mac_type(hw);
690 AT_READ_REG(hw, REG_PHY_STATUS, &phy_status_data);
691 AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
692
693 hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
694 ATL1C_TXQ_MODE_ENHANCE;
695 if (link_ctrl_data & LINK_CTRL_L0S_EN)
696 hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT;
697 if (link_ctrl_data & LINK_CTRL_L1_EN)
698 hw->ctrl_flags |= ATL1C_ASPM_L1_SUPPORT;
699 if (link_ctrl_data & LINK_CTRL_EXT_SYNC)
700 hw->ctrl_flags |= ATL1C_LINK_EXT_SYNC;
701 hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
702
703 if (hw->nic_type == athr_l1c ||
704 hw->nic_type == athr_l1d ||
705 hw->nic_type == athr_l1d_2)
706 hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
707 return 0;
708}
709/*
710 * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
711 * @adapter: board private structure to initialize
712 *
713 * atl1c_sw_init initializes the Adapter private data structure.
714 * Fields are initialized based on PCI device information and
715 * OS network device settings (MTU size).
716 */
717static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
718{
719 struct atl1c_hw *hw = &adapter->hw;
720 struct pci_dev *pdev = adapter->pdev;
721 u32 revision;
722
723
724 adapter->wol = 0;
725 device_set_wakeup_enable(&pdev->dev, false);
726 adapter->link_speed = SPEED_0;
727 adapter->link_duplex = FULL_DUPLEX;
728 adapter->num_rx_queues = AT_DEF_RECEIVE_QUEUE;
729 adapter->tpd_ring[0].count = 1024;
730 adapter->rfd_ring[0].count = 512;
731
732 hw->vendor_id = pdev->vendor;
733 hw->device_id = pdev->device;
734 hw->subsystem_vendor_id = pdev->subsystem_vendor;
735 hw->subsystem_id = pdev->subsystem_device;
736 AT_READ_REG(hw, PCI_CLASS_REVISION, &revision);
737 hw->revision_id = revision & 0xFF;
738 /* before link up, we assume hibernate is true */
739 hw->hibernate = true;
740 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
741 if (atl1c_setup_mac_funcs(hw) != 0) {
742 dev_err(&pdev->dev, "set mac function pointers failed\n");
743 return -1;
744 }
745 hw->intr_mask = IMR_NORMAL_MASK;
746 hw->phy_configured = false;
747 hw->preamble_len = 7;
748 hw->max_frame_size = adapter->netdev->mtu;
749 if (adapter->num_rx_queues < 2) {
750 hw->rss_type = atl1c_rss_disable;
751 hw->rss_mode = atl1c_rss_mode_disable;
752 } else {
753 hw->rss_type = atl1c_rss_ipv4;
754 hw->rss_mode = atl1c_rss_mul_que_mul_int;
755 hw->rss_hash_bits = 16;
756 }
757 hw->autoneg_advertised = ADVERTISED_Autoneg;
758 hw->indirect_tab = 0xE4E4E4E4;
759 hw->base_cpu = 0;
760
761 hw->ict = 50000; /* 100ms */
762 hw->smb_timer = 200000; /* 400ms */
763 hw->cmb_tpd = 4;
764 hw->cmb_tx_timer = 1; /* 2 us */
765 hw->rx_imt = 200;
766 hw->tx_imt = 1000;
767
768 hw->tpd_burst = 5;
769 hw->rfd_burst = 8;
770 hw->dma_order = atl1c_dma_ord_out;
771 hw->dmar_block = atl1c_dma_req_1024;
772 hw->dmaw_block = atl1c_dma_req_1024;
773 hw->dmar_dly_cnt = 15;
774 hw->dmaw_dly_cnt = 4;
775
776 if (atl1c_alloc_queues(adapter)) {
777 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
778 return -ENOMEM;
779 }
780 /* TODO */
781 atl1c_set_rxbufsize(adapter, adapter->netdev);
782 atomic_set(&adapter->irq_sem, 1);
783 spin_lock_init(&adapter->mdio_lock);
784 spin_lock_init(&adapter->tx_lock);
785 set_bit(__AT_DOWN, &adapter->flags);
786
787 return 0;
788}
789
790static inline void atl1c_clean_buffer(struct pci_dev *pdev,
791 struct atl1c_buffer *buffer_info, int in_irq)
792{
793 u16 pci_driection;
794 if (buffer_info->flags & ATL1C_BUFFER_FREE)
795 return;
796 if (buffer_info->dma) {
797 if (buffer_info->flags & ATL1C_PCIMAP_FROMDEVICE)
798 pci_driection = PCI_DMA_FROMDEVICE;
799 else
800 pci_driection = PCI_DMA_TODEVICE;
801
802 if (buffer_info->flags & ATL1C_PCIMAP_SINGLE)
803 pci_unmap_single(pdev, buffer_info->dma,
804 buffer_info->length, pci_driection);
805 else if (buffer_info->flags & ATL1C_PCIMAP_PAGE)
806 pci_unmap_page(pdev, buffer_info->dma,
807 buffer_info->length, pci_driection);
808 }
809 if (buffer_info->skb) {
810 if (in_irq)
811 dev_kfree_skb_irq(buffer_info->skb);
812 else
813 dev_kfree_skb(buffer_info->skb);
814 }
815 buffer_info->dma = 0;
816 buffer_info->skb = NULL;
817 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
818}
819/*
820 * atl1c_clean_tx_ring - Free Tx-skb
821 * @adapter: board private structure
822 */
823static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
824 enum atl1c_trans_queue type)
825{
826 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
827 struct atl1c_buffer *buffer_info;
828 struct pci_dev *pdev = adapter->pdev;
829 u16 index, ring_count;
830
831 ring_count = tpd_ring->count;
832 for (index = 0; index < ring_count; index++) {
833 buffer_info = &tpd_ring->buffer_info[index];
834 atl1c_clean_buffer(pdev, buffer_info, 0);
835 }
836
837 /* Zero out Tx-buffers */
838 memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
839 ring_count);
840 atomic_set(&tpd_ring->next_to_clean, 0);
841 tpd_ring->next_to_use = 0;
842}
843
844/*
845 * atl1c_clean_rx_ring - Free rx-reservation skbs
846 * @adapter: board private structure
847 */
848static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
849{
850 struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
851 struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
852 struct atl1c_buffer *buffer_info;
853 struct pci_dev *pdev = adapter->pdev;
854 int i, j;
855
856 for (i = 0; i < adapter->num_rx_queues; i++) {
857 for (j = 0; j < rfd_ring[i].count; j++) {
858 buffer_info = &rfd_ring[i].buffer_info[j];
859 atl1c_clean_buffer(pdev, buffer_info, 0);
860 }
861 /* zero out the descriptor ring */
862 memset(rfd_ring[i].desc, 0, rfd_ring[i].size);
863 rfd_ring[i].next_to_clean = 0;
864 rfd_ring[i].next_to_use = 0;
865 rrd_ring[i].next_to_use = 0;
866 rrd_ring[i].next_to_clean = 0;
867 }
868}
869
870/*
871 * Read / Write Ptr Initialize:
872 */
873static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
874{
875 struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
876 struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
877 struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
878 struct atl1c_buffer *buffer_info;
879 int i, j;
880
881 for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
882 tpd_ring[i].next_to_use = 0;
883 atomic_set(&tpd_ring[i].next_to_clean, 0);
884 buffer_info = tpd_ring[i].buffer_info;
885 for (j = 0; j < tpd_ring->count; j++)
886 ATL1C_SET_BUFFER_STATE(&buffer_info[i],
887 ATL1C_BUFFER_FREE);
888 }
889 for (i = 0; i < adapter->num_rx_queues; i++) {
890 rfd_ring[i].next_to_use = 0;
891 rfd_ring[i].next_to_clean = 0;
892 rrd_ring[i].next_to_use = 0;
893 rrd_ring[i].next_to_clean = 0;
894 for (j = 0; j < rfd_ring[i].count; j++) {
895 buffer_info = &rfd_ring[i].buffer_info[j];
896 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
897 }
898 }
899}
900
901/*
902 * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
903 * @adapter: board private structure
904 *
905 * Free all transmit software resources
906 */
907static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
908{
909 struct pci_dev *pdev = adapter->pdev;
910
911 pci_free_consistent(pdev, adapter->ring_header.size,
912 adapter->ring_header.desc,
913 adapter->ring_header.dma);
914 adapter->ring_header.desc = NULL;
915
916 /* Note: just free tdp_ring.buffer_info,
917 * it contain rfd_ring.buffer_info, do not double free */
918 if (adapter->tpd_ring[0].buffer_info) {
919 kfree(adapter->tpd_ring[0].buffer_info);
920 adapter->tpd_ring[0].buffer_info = NULL;
921 }
922}
923
924/*
925 * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
926 * @adapter: board private structure
927 *
928 * Return 0 on success, negative on failure
929 */
930static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
931{
932 struct pci_dev *pdev = adapter->pdev;
933 struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
934 struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
935 struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
936 struct atl1c_ring_header *ring_header = &adapter->ring_header;
937 int num_rx_queues = adapter->num_rx_queues;
938 int size;
939 int i;
940 int count = 0;
941 int rx_desc_count = 0;
942 u32 offset = 0;
943
944 rrd_ring[0].count = rfd_ring[0].count;
945 for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
946 tpd_ring[i].count = tpd_ring[0].count;
947
948 for (i = 1; i < adapter->num_rx_queues; i++)
949 rfd_ring[i].count = rrd_ring[i].count = rfd_ring[0].count;
950
951 /* 2 tpd queue, one high priority queue,
952 * another normal priority queue */
953 size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
954 rfd_ring->count * num_rx_queues);
955 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
956 if (unlikely(!tpd_ring->buffer_info)) {
957 dev_err(&pdev->dev, "kzalloc failed, size = %d\n",
958 size);
959 goto err_nomem;
960 }
961 for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
962 tpd_ring[i].buffer_info =
963 (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
964 count += tpd_ring[i].count;
965 }
966
967 for (i = 0; i < num_rx_queues; i++) {
968 rfd_ring[i].buffer_info =
969 (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
970 count += rfd_ring[i].count;
971 rx_desc_count += rfd_ring[i].count;
972 }
973 /*
974 * real ring DMA buffer
975 * each ring/block may need up to 8 bytes for alignment, hence the
976 * additional bytes tacked onto the end.
977 */
978 ring_header->size = size =
979 sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
980 sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
981 sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
982 sizeof(struct atl1c_hw_stats) +
983 8 * 4 + 8 * 2 * num_rx_queues;
984
985 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
986 &ring_header->dma);
987 if (unlikely(!ring_header->desc)) {
988 dev_err(&pdev->dev, "pci_alloc_consistend failed\n");
989 goto err_nomem;
990 }
991 memset(ring_header->desc, 0, ring_header->size);
992 /* init TPD ring */
993
994 tpd_ring[0].dma = roundup(ring_header->dma, 8);
995 offset = tpd_ring[0].dma - ring_header->dma;
996 for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
997 tpd_ring[i].dma = ring_header->dma + offset;
998 tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
999 tpd_ring[i].size =
1000 sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
1001 offset += roundup(tpd_ring[i].size, 8);
1002 }
1003 /* init RFD ring */
1004 for (i = 0; i < num_rx_queues; i++) {
1005 rfd_ring[i].dma = ring_header->dma + offset;
1006 rfd_ring[i].desc = (u8 *) ring_header->desc + offset;
1007 rfd_ring[i].size = sizeof(struct atl1c_rx_free_desc) *
1008 rfd_ring[i].count;
1009 offset += roundup(rfd_ring[i].size, 8);
1010 }
1011
1012 /* init RRD ring */
1013 for (i = 0; i < num_rx_queues; i++) {
1014 rrd_ring[i].dma = ring_header->dma + offset;
1015 rrd_ring[i].desc = (u8 *) ring_header->desc + offset;
1016 rrd_ring[i].size = sizeof(struct atl1c_recv_ret_status) *
1017 rrd_ring[i].count;
1018 offset += roundup(rrd_ring[i].size, 8);
1019 }
1020
1021 adapter->smb.dma = ring_header->dma + offset;
1022 adapter->smb.smb = (u8 *)ring_header->desc + offset;
1023 return 0;
1024
1025err_nomem:
1026 kfree(tpd_ring->buffer_info);
1027 return -ENOMEM;
1028}
1029
1030static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
1031{
1032 struct atl1c_hw *hw = &adapter->hw;
1033 struct atl1c_rfd_ring *rfd_ring = (struct atl1c_rfd_ring *)
1034 adapter->rfd_ring;
1035 struct atl1c_rrd_ring *rrd_ring = (struct atl1c_rrd_ring *)
1036 adapter->rrd_ring;
1037 struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
1038 adapter->tpd_ring;
1039 struct atl1c_cmb *cmb = (struct atl1c_cmb *) &adapter->cmb;
1040 struct atl1c_smb *smb = (struct atl1c_smb *) &adapter->smb;
1041 int i;
1042 u32 data;
1043
1044 /* TPD */
1045 AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
1046 (u32)((tpd_ring[atl1c_trans_normal].dma &
1047 AT_DMA_HI_ADDR_MASK) >> 32));
1048 /* just enable normal priority TX queue */
1049 AT_WRITE_REG(hw, REG_NTPD_HEAD_ADDR_LO,
1050 (u32)(tpd_ring[atl1c_trans_normal].dma &
1051 AT_DMA_LO_ADDR_MASK));
1052 AT_WRITE_REG(hw, REG_HTPD_HEAD_ADDR_LO,
1053 (u32)(tpd_ring[atl1c_trans_high].dma &
1054 AT_DMA_LO_ADDR_MASK));
1055 AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
1056 (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
1057
1058
1059 /* RFD */
1060 AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
1061 (u32)((rfd_ring[0].dma & AT_DMA_HI_ADDR_MASK) >> 32));
1062 for (i = 0; i < adapter->num_rx_queues; i++)
1063 AT_WRITE_REG(hw, atl1c_rfd_addr_lo_regs[i],
1064 (u32)(rfd_ring[i].dma & AT_DMA_LO_ADDR_MASK));
1065
1066 AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
1067 rfd_ring[0].count & RFD_RING_SIZE_MASK);
1068 AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
1069 adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
1070
1071 /* RRD */
1072 for (i = 0; i < adapter->num_rx_queues; i++)
1073 AT_WRITE_REG(hw, atl1c_rrd_addr_lo_regs[i],
1074 (u32)(rrd_ring[i].dma & AT_DMA_LO_ADDR_MASK));
1075 AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
1076 (rrd_ring[0].count & RRD_RING_SIZE_MASK));
1077
1078 /* CMB */
1079 AT_WRITE_REG(hw, REG_CMB_BASE_ADDR_LO, cmb->dma & AT_DMA_LO_ADDR_MASK);
1080
1081 /* SMB */
1082 AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_HI,
1083 (u32)((smb->dma & AT_DMA_HI_ADDR_MASK) >> 32));
1084 AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_LO,
1085 (u32)(smb->dma & AT_DMA_LO_ADDR_MASK));
1086 if (hw->nic_type == athr_l2c_b) {
1087 AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
1088 AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
1089 AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
1090 AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
1091 AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
1092 AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
1093 AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
1094 AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
1095 }
1096 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d_2) {
1097 /* Power Saving for L2c_B */
1098 AT_READ_REG(hw, REG_SERDES_LOCK, &data);
1099 data |= SERDES_MAC_CLK_SLOWDOWN;
1100 data |= SERDES_PYH_CLK_SLOWDOWN;
1101 AT_WRITE_REG(hw, REG_SERDES_LOCK, data);
1102 }
1103 /* Load all of base address above */
1104 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
1105}
1106
1107static void atl1c_configure_tx(struct atl1c_adapter *adapter)
1108{
1109 struct atl1c_hw *hw = &adapter->hw;
1110 u32 dev_ctrl_data;
1111 u32 max_pay_load;
1112 u16 tx_offload_thresh;
1113 u32 txq_ctrl_data;
1114 u32 max_pay_load_data;
1115
1116 tx_offload_thresh = MAX_TX_OFFLOAD_THRESH;
1117 AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
1118 (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
1119 AT_READ_REG(hw, REG_DEVICE_CTRL, &dev_ctrl_data);
1120 max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT) &
1121 DEVICE_CTRL_MAX_PAYLOAD_MASK;
1122 hw->dmaw_block = min_t(u32, max_pay_load, hw->dmaw_block);
1123 max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT) &
1124 DEVICE_CTRL_MAX_RREQ_SZ_MASK;
1125 hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
1126
1127 txq_ctrl_data = (hw->tpd_burst & TXQ_NUM_TPD_BURST_MASK) <<
1128 TXQ_NUM_TPD_BURST_SHIFT;
1129 if (hw->ctrl_flags & ATL1C_TXQ_MODE_ENHANCE)
1130 txq_ctrl_data |= TXQ_CTRL_ENH_MODE;
1131 max_pay_load_data = (atl1c_pay_load_size[hw->dmar_block] &
1132 TXQ_TXF_BURST_NUM_MASK) << TXQ_TXF_BURST_NUM_SHIFT;
1133 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2)
1134 max_pay_load_data >>= 1;
1135 txq_ctrl_data |= max_pay_load_data;
1136
1137 AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
1138}
1139
1140static void atl1c_configure_rx(struct atl1c_adapter *adapter)
1141{
1142 struct atl1c_hw *hw = &adapter->hw;
1143 u32 rxq_ctrl_data;
1144
1145 rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
1146 RXQ_RFD_BURST_NUM_SHIFT;
1147
1148 if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
1149 rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
1150 if (hw->rss_type == atl1c_rss_ipv4)
1151 rxq_ctrl_data |= RSS_HASH_IPV4;
1152 if (hw->rss_type == atl1c_rss_ipv4_tcp)
1153 rxq_ctrl_data |= RSS_HASH_IPV4_TCP;
1154 if (hw->rss_type == atl1c_rss_ipv6)
1155 rxq_ctrl_data |= RSS_HASH_IPV6;
1156 if (hw->rss_type == atl1c_rss_ipv6_tcp)
1157 rxq_ctrl_data |= RSS_HASH_IPV6_TCP;
1158 if (hw->rss_type != atl1c_rss_disable)
1159 rxq_ctrl_data |= RRS_HASH_CTRL_EN;
1160
1161 rxq_ctrl_data |= (hw->rss_mode & RSS_MODE_MASK) <<
1162 RSS_MODE_SHIFT;
1163 rxq_ctrl_data |= (hw->rss_hash_bits & RSS_HASH_BITS_MASK) <<
1164 RSS_HASH_BITS_SHIFT;
1165 if (hw->ctrl_flags & ATL1C_ASPM_CTRL_MON)
1166 rxq_ctrl_data |= (ASPM_THRUPUT_LIMIT_1M &
1167 ASPM_THRUPUT_LIMIT_MASK) << ASPM_THRUPUT_LIMIT_SHIFT;
1168
1169 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1170}
1171
1172static void atl1c_configure_rss(struct atl1c_adapter *adapter)
1173{
1174 struct atl1c_hw *hw = &adapter->hw;
1175
1176 AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
1177 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
1178}
1179
1180static void atl1c_configure_dma(struct atl1c_adapter *adapter)
1181{
1182 struct atl1c_hw *hw = &adapter->hw;
1183 u32 dma_ctrl_data;
1184
1185 dma_ctrl_data = DMA_CTRL_DMAR_REQ_PRI;
1186 if (hw->ctrl_flags & ATL1C_CMB_ENABLE)
1187 dma_ctrl_data |= DMA_CTRL_CMB_EN;
1188 if (hw->ctrl_flags & ATL1C_SMB_ENABLE)
1189 dma_ctrl_data |= DMA_CTRL_SMB_EN;
1190 else
1191 dma_ctrl_data |= MAC_CTRL_SMB_DIS;
1192
1193 switch (hw->dma_order) {
1194 case atl1c_dma_ord_in:
1195 dma_ctrl_data |= DMA_CTRL_DMAR_IN_ORDER;
1196 break;
1197 case atl1c_dma_ord_enh:
1198 dma_ctrl_data |= DMA_CTRL_DMAR_ENH_ORDER;
1199 break;
1200 case atl1c_dma_ord_out:
1201 dma_ctrl_data |= DMA_CTRL_DMAR_OUT_ORDER;
1202 break;
1203 default:
1204 break;
1205 }
1206
1207 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1208 << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
1209 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1210 << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
1211 dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
1212 << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
1213 dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
1214 << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
1215
1216 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1217}
1218
1219/*
1220 * Stop the mac, transmit and receive units
1221 * hw - Struct containing variables accessed by shared code
1222 * return : 0 or idle status (if error)
1223 */
1224static int atl1c_stop_mac(struct atl1c_hw *hw)
1225{
1226 u32 data;
1227
1228 AT_READ_REG(hw, REG_RXQ_CTRL, &data);
1229 data &= ~(RXQ1_CTRL_EN | RXQ2_CTRL_EN |
1230 RXQ3_CTRL_EN | RXQ_CTRL_EN);
1231 AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
1232
1233 AT_READ_REG(hw, REG_TXQ_CTRL, &data);
1234 data &= ~TXQ_CTRL_EN;
1235 AT_WRITE_REG(hw, REG_TWSI_CTRL, data);
1236
1237 atl1c_wait_until_idle(hw);
1238
1239 AT_READ_REG(hw, REG_MAC_CTRL, &data);
1240 data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
1241 AT_WRITE_REG(hw, REG_MAC_CTRL, data);
1242
1243 return (int)atl1c_wait_until_idle(hw);
1244}
1245
1246static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw)
1247{
1248 u32 data;
1249
1250 AT_READ_REG(hw, REG_RXQ_CTRL, &data);
1251 switch (hw->adapter->num_rx_queues) {
1252 case 4:
1253 data |= (RXQ3_CTRL_EN | RXQ2_CTRL_EN | RXQ1_CTRL_EN);
1254 break;
1255 case 3:
1256 data |= (RXQ2_CTRL_EN | RXQ1_CTRL_EN);
1257 break;
1258 case 2:
1259 data |= RXQ1_CTRL_EN;
1260 break;
1261 default:
1262 break;
1263 }
1264 data |= RXQ_CTRL_EN;
1265 AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
1266}
1267
1268static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw)
1269{
1270 u32 data;
1271
1272 AT_READ_REG(hw, REG_TXQ_CTRL, &data);
1273 data |= TXQ_CTRL_EN;
1274 AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
1275}
1276
1277/*
1278 * Reset the transmit and receive units; mask and clear all interrupts.
1279 * hw - Struct containing variables accessed by shared code
1280 * return : 0 or idle status (if error)
1281 */
1282static int atl1c_reset_mac(struct atl1c_hw *hw)
1283{
1284 struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
1285 struct pci_dev *pdev = adapter->pdev;
1286 u32 master_ctrl_data = 0;
1287
1288 AT_WRITE_REG(hw, REG_IMR, 0);
1289 AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT);
1290
1291 atl1c_stop_mac(hw);
1292 /*
1293 * Issue Soft Reset to the MAC. This will reset the chip's
1294 * transmit, receive, DMA. It will not effect
1295 * the current PCI configuration. The global reset bit is self-
1296 * clearing, and should clear within a microsecond.
1297 */
1298 AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
1299 master_ctrl_data |= MASTER_CTRL_OOB_DIS_OFF;
1300 AT_WRITE_REGW(hw, REG_MASTER_CTRL, ((master_ctrl_data | MASTER_CTRL_SOFT_RST)
1301 & 0xFFFF));
1302
1303 AT_WRITE_FLUSH(hw);
1304 msleep(10);
1305 /* Wait at least 10ms for All module to be Idle */
1306
1307 if (atl1c_wait_until_idle(hw)) {
1308 dev_err(&pdev->dev,
1309 "MAC state machine can't be idle since"
1310 " disabled for 10ms second\n");
1311 return -1;
1312 }
1313 return 0;
1314}
1315
1316static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
1317{
1318 u32 pm_ctrl_data;
1319
1320 AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
1321 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
1322 PM_CTRL_L1_ENTRY_TIMER_SHIFT);
1323 pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
1324 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1325 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1326 pm_ctrl_data &= ~PM_CTRL_MAC_ASPM_CHK;
1327 pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
1328
1329 pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
1330 pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
1331 pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
1332 AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
1333}
1334
1335/*
1336 * Set ASPM state.
1337 * Enable/disable L0s/L1 depend on link state.
1338 */
1339static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup)
1340{
1341 u32 pm_ctrl_data;
1342 u32 link_ctrl_data;
1343 u32 link_l1_timer = 0xF;
1344
1345 AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
1346 AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
1347
1348 pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
1349 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
1350 PM_CTRL_L1_ENTRY_TIMER_SHIFT);
1351 pm_ctrl_data &= ~(PM_CTRL_LCKDET_TIMER_MASK <<
1352 PM_CTRL_LCKDET_TIMER_SHIFT);
1353 pm_ctrl_data |= AT_LCKDET_TIMER << PM_CTRL_LCKDET_TIMER_SHIFT;
1354
1355 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
1356 hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
1357 link_ctrl_data &= ~LINK_CTRL_EXT_SYNC;
1358 if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE)) {
1359 if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10)
1360 link_ctrl_data |= LINK_CTRL_EXT_SYNC;
1361 }
1362
1363 AT_WRITE_REG(hw, REG_LINK_CTRL, link_ctrl_data);
1364
1365 pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER;
1366 pm_ctrl_data &= ~(PM_CTRL_PM_REQ_TIMER_MASK <<
1367 PM_CTRL_PM_REQ_TIMER_SHIFT);
1368 pm_ctrl_data |= AT_ASPM_L1_TIMER <<
1369 PM_CTRL_PM_REQ_TIMER_SHIFT;
1370 pm_ctrl_data &= ~PM_CTRL_SA_DLY_EN;
1371 pm_ctrl_data &= ~PM_CTRL_HOTRST;
1372 pm_ctrl_data |= 1 << PM_CTRL_L1_ENTRY_TIMER_SHIFT;
1373 pm_ctrl_data |= PM_CTRL_SERDES_PD_EX_L1;
1374 }
1375 pm_ctrl_data |= PM_CTRL_MAC_ASPM_CHK;
1376 if (linkup) {
1377 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1378 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1379 if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
1380 pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
1381 if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT)
1382 pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN;
1383
1384 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
1385 hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
1386 if (hw->nic_type == athr_l2c_b)
1387 if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE))
1388 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1389 pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
1390 pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
1391 pm_ctrl_data &= ~PM_CTRL_SERDES_BUDS_RX_L1_EN;
1392 pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
1393 if (hw->adapter->link_speed == SPEED_100 ||
1394 hw->adapter->link_speed == SPEED_1000) {
1395 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
1396 PM_CTRL_L1_ENTRY_TIMER_SHIFT);
1397 if (hw->nic_type == athr_l2c_b)
1398 link_l1_timer = 7;
1399 else if (hw->nic_type == athr_l2c_b2 ||
1400 hw->nic_type == athr_l1d_2)
1401 link_l1_timer = 4;
1402 pm_ctrl_data |= link_l1_timer <<
1403 PM_CTRL_L1_ENTRY_TIMER_SHIFT;
1404 }
1405 } else {
1406 pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
1407 pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
1408 pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
1409 pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
1410 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1411 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1412
1413 }
1414 } else {
1415 pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
1416 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1417 pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
1418 pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
1419
1420 if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
1421 pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
1422 else
1423 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1424 }
1425 AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
1426
1427 return;
1428}
1429
1430static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter)
1431{
1432 struct atl1c_hw *hw = &adapter->hw;
1433 struct net_device *netdev = adapter->netdev;
1434 u32 mac_ctrl_data;
1435
1436 mac_ctrl_data = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1437 mac_ctrl_data |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1438
1439 if (adapter->link_duplex == FULL_DUPLEX) {
1440 hw->mac_duplex = true;
1441 mac_ctrl_data |= MAC_CTRL_DUPLX;
1442 }
1443
1444 if (adapter->link_speed == SPEED_1000)
1445 hw->mac_speed = atl1c_mac_speed_1000;
1446 else
1447 hw->mac_speed = atl1c_mac_speed_10_100;
1448
1449 mac_ctrl_data |= (hw->mac_speed & MAC_CTRL_SPEED_MASK) <<
1450 MAC_CTRL_SPEED_SHIFT;
1451
1452 mac_ctrl_data |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1453 mac_ctrl_data |= ((hw->preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1454 MAC_CTRL_PRMLEN_SHIFT);
1455
1456 __atl1c_vlan_mode(netdev->features, &mac_ctrl_data);
1457
1458 mac_ctrl_data |= MAC_CTRL_BC_EN;
1459 if (netdev->flags & IFF_PROMISC)
1460 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
1461 if (netdev->flags & IFF_ALLMULTI)
1462 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
1463
1464 mac_ctrl_data |= MAC_CTRL_SINGLE_PAUSE_EN;
1465 if (hw->nic_type == athr_l1d || hw->nic_type == athr_l2c_b2 ||
1466 hw->nic_type == athr_l1d_2) {
1467 mac_ctrl_data |= MAC_CTRL_SPEED_MODE_SW;
1468 mac_ctrl_data |= MAC_CTRL_HASH_ALG_CRC32;
1469 }
1470 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
1471}
1472
1473/*
1474 * atl1c_configure - Configure Transmit&Receive Unit after Reset
1475 * @adapter: board private structure
1476 *
1477 * Configure the Tx /Rx unit of the MAC after a reset.
1478 */
1479static int atl1c_configure(struct atl1c_adapter *adapter)
1480{
1481 struct atl1c_hw *hw = &adapter->hw;
1482 u32 master_ctrl_data = 0;
1483 u32 intr_modrt_data;
1484 u32 data;
1485
1486 /* clear interrupt status */
1487 AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
1488 /* Clear any WOL status */
1489 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1490 /* set Interrupt Clear Timer
1491 * HW will enable self to assert interrupt event to system after
1492 * waiting x-time for software to notify it accept interrupt.
1493 */
1494
1495 data = CLK_GATING_EN_ALL;
1496 if (hw->ctrl_flags & ATL1C_CLK_GATING_EN) {
1497 if (hw->nic_type == athr_l2c_b)
1498 data &= ~CLK_GATING_RXMAC_EN;
1499 } else
1500 data = 0;
1501 AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
1502
1503 AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
1504 hw->ict & INT_RETRIG_TIMER_MASK);
1505
1506 atl1c_configure_des_ring(adapter);
1507
1508 if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
1509 intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
1510 IRQ_MODRT_TX_TIMER_SHIFT;
1511 intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
1512 IRQ_MODRT_RX_TIMER_SHIFT;
1513 AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
1514 master_ctrl_data |=
1515 MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
1516 }
1517
1518 if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
1519 master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
1520
1521 master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
1522 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
1523
1524 if (hw->ctrl_flags & ATL1C_CMB_ENABLE) {
1525 AT_WRITE_REG(hw, REG_CMB_TPD_THRESH,
1526 hw->cmb_tpd & CMB_TPD_THRESH_MASK);
1527 AT_WRITE_REG(hw, REG_CMB_TX_TIMER,
1528 hw->cmb_tx_timer & CMB_TX_TIMER_MASK);
1529 }
1530
1531 if (hw->ctrl_flags & ATL1C_SMB_ENABLE)
1532 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
1533 hw->smb_timer & SMB_STAT_TIMER_MASK);
1534 /* set MTU */
1535 AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1536 VLAN_HLEN + ETH_FCS_LEN);
1537 /* HDS, disable */
1538 AT_WRITE_REG(hw, REG_HDS_CTRL, 0);
1539
1540 atl1c_configure_tx(adapter);
1541 atl1c_configure_rx(adapter);
1542 atl1c_configure_rss(adapter);
1543 atl1c_configure_dma(adapter);
1544
1545 return 0;
1546}
1547
1548static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
1549{
1550 u16 hw_reg_addr = 0;
1551 unsigned long *stats_item = NULL;
1552 u32 data;
1553
1554 /* update rx status */
1555 hw_reg_addr = REG_MAC_RX_STATUS_BIN;
1556 stats_item = &adapter->hw_stats.rx_ok;
1557 while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
1558 AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
1559 *stats_item += data;
1560 stats_item++;
1561 hw_reg_addr += 4;
1562 }
1563/* update tx status */
1564 hw_reg_addr = REG_MAC_TX_STATUS_BIN;
1565 stats_item = &adapter->hw_stats.tx_ok;
1566 while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
1567 AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
1568 *stats_item += data;
1569 stats_item++;
1570 hw_reg_addr += 4;
1571 }
1572}
1573
1574/*
1575 * atl1c_get_stats - Get System Network Statistics
1576 * @netdev: network interface device structure
1577 *
1578 * Returns the address of the device statistics structure.
1579 * The statistics are actually updated from the timer callback.
1580 */
1581static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
1582{
1583 struct atl1c_adapter *adapter = netdev_priv(netdev);
1584 struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
1585 struct net_device_stats *net_stats = &netdev->stats;
1586
1587 atl1c_update_hw_stats(adapter);
1588 net_stats->rx_packets = hw_stats->rx_ok;
1589 net_stats->tx_packets = hw_stats->tx_ok;
1590 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1591 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1592 net_stats->multicast = hw_stats->rx_mcast;
1593 net_stats->collisions = hw_stats->tx_1_col +
1594 hw_stats->tx_2_col * 2 +
1595 hw_stats->tx_late_col + hw_stats->tx_abort_col;
1596 net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
1597 hw_stats->rx_len_err + hw_stats->rx_sz_ov +
1598 hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
1599 net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
1600 net_stats->rx_length_errors = hw_stats->rx_len_err;
1601 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1602 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1603 net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1604
1605 net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1606
1607 net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
1608 hw_stats->tx_underrun + hw_stats->tx_trunc;
1609 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1610 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1611 net_stats->tx_window_errors = hw_stats->tx_late_col;
1612
1613 return net_stats;
1614}
1615
1616static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
1617{
1618 u16 phy_data;
1619
1620 spin_lock(&adapter->mdio_lock);
1621 atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
1622 spin_unlock(&adapter->mdio_lock);
1623}
1624
1625static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
1626 enum atl1c_trans_queue type)
1627{
1628 struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
1629 &adapter->tpd_ring[type];
1630 struct atl1c_buffer *buffer_info;
1631 struct pci_dev *pdev = adapter->pdev;
1632 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
1633 u16 hw_next_to_clean;
1634 u16 shift;
1635 u32 data;
1636
1637 if (type == atl1c_trans_high)
1638 shift = MB_HTPD_CONS_IDX_SHIFT;
1639 else
1640 shift = MB_NTPD_CONS_IDX_SHIFT;
1641
1642 AT_READ_REG(&adapter->hw, REG_MB_PRIO_CONS_IDX, &data);
1643 hw_next_to_clean = (data >> shift) & MB_PRIO_PROD_IDX_MASK;
1644
1645 while (next_to_clean != hw_next_to_clean) {
1646 buffer_info = &tpd_ring->buffer_info[next_to_clean];
1647 atl1c_clean_buffer(pdev, buffer_info, 1);
1648 if (++next_to_clean == tpd_ring->count)
1649 next_to_clean = 0;
1650 atomic_set(&tpd_ring->next_to_clean, next_to_clean);
1651 }
1652
1653 if (netif_queue_stopped(adapter->netdev) &&
1654 netif_carrier_ok(adapter->netdev)) {
1655 netif_wake_queue(adapter->netdev);
1656 }
1657
1658 return true;
1659}
1660
1661/*
1662 * atl1c_intr - Interrupt Handler
1663 * @irq: interrupt number
1664 * @data: pointer to a network interface device structure
1665 * @pt_regs: CPU registers structure
1666 */
1667static irqreturn_t atl1c_intr(int irq, void *data)
1668{
1669 struct net_device *netdev = data;
1670 struct atl1c_adapter *adapter = netdev_priv(netdev);
1671 struct pci_dev *pdev = adapter->pdev;
1672 struct atl1c_hw *hw = &adapter->hw;
1673 int max_ints = AT_MAX_INT_WORK;
1674 int handled = IRQ_NONE;
1675 u32 status;
1676 u32 reg_data;
1677
1678 do {
1679 AT_READ_REG(hw, REG_ISR, &reg_data);
1680 status = reg_data & hw->intr_mask;
1681
1682 if (status == 0 || (status & ISR_DIS_INT) != 0) {
1683 if (max_ints != AT_MAX_INT_WORK)
1684 handled = IRQ_HANDLED;
1685 break;
1686 }
1687 /* link event */
1688 if (status & ISR_GPHY)
1689 atl1c_clear_phy_int(adapter);
1690 /* Ack ISR */
1691 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1692 if (status & ISR_RX_PKT) {
1693 if (likely(napi_schedule_prep(&adapter->napi))) {
1694 hw->intr_mask &= ~ISR_RX_PKT;
1695 AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
1696 __napi_schedule(&adapter->napi);
1697 }
1698 }
1699 if (status & ISR_TX_PKT)
1700 atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
1701
1702 handled = IRQ_HANDLED;
1703 /* check if PCIE PHY Link down */
1704 if (status & ISR_ERROR) {
1705 if (netif_msg_hw(adapter))
1706 dev_err(&pdev->dev,
1707 "atl1c hardware error (status = 0x%x)\n",
1708 status & ISR_ERROR);
1709 /* reset MAC */
1710 adapter->work_event |= ATL1C_WORK_EVENT_RESET;
1711 schedule_work(&adapter->common_task);
1712 return IRQ_HANDLED;
1713 }
1714
1715 if (status & ISR_OVER)
1716 if (netif_msg_intr(adapter))
1717 dev_warn(&pdev->dev,
1718 "TX/RX overflow (status = 0x%x)\n",
1719 status & ISR_OVER);
1720
1721 /* link event */
1722 if (status & (ISR_GPHY | ISR_MANUAL)) {
1723 netdev->stats.tx_carrier_errors++;
1724 atl1c_link_chg_event(adapter);
1725 break;
1726 }
1727
1728 } while (--max_ints > 0);
1729 /* re-enable Interrupt*/
1730 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1731 return handled;
1732}
1733
1734static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
1735 struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
1736{
1737 /*
1738 * The pid field in RRS in not correct sometimes, so we
1739 * cannot figure out if the packet is fragmented or not,
1740 * so we tell the KERNEL CHECKSUM_NONE
1741 */
1742 skb_checksum_none_assert(skb);
1743}
1744
1745static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter, const int ringid)
1746{
1747 struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[ringid];
1748 struct pci_dev *pdev = adapter->pdev;
1749 struct atl1c_buffer *buffer_info, *next_info;
1750 struct sk_buff *skb;
1751 void *vir_addr = NULL;
1752 u16 num_alloc = 0;
1753 u16 rfd_next_to_use, next_next;
1754 struct atl1c_rx_free_desc *rfd_desc;
1755
1756 next_next = rfd_next_to_use = rfd_ring->next_to_use;
1757 if (++next_next == rfd_ring->count)
1758 next_next = 0;
1759 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1760 next_info = &rfd_ring->buffer_info[next_next];
1761
1762 while (next_info->flags & ATL1C_BUFFER_FREE) {
1763 rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
1764
1765 skb = dev_alloc_skb(adapter->rx_buffer_len);
1766 if (unlikely(!skb)) {
1767 if (netif_msg_rx_err(adapter))
1768 dev_warn(&pdev->dev, "alloc rx buffer failed\n");
1769 break;
1770 }
1771
1772 /*
1773 * Make buffer alignment 2 beyond a 16 byte boundary
1774 * this will result in a 16 byte aligned IP header after
1775 * the 14 byte MAC header is removed
1776 */
1777 vir_addr = skb->data;
1778 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
1779 buffer_info->skb = skb;
1780 buffer_info->length = adapter->rx_buffer_len;
1781 buffer_info->dma = pci_map_single(pdev, vir_addr,
1782 buffer_info->length,
1783 PCI_DMA_FROMDEVICE);
1784 ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
1785 ATL1C_PCIMAP_FROMDEVICE);
1786 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1787 rfd_next_to_use = next_next;
1788 if (++next_next == rfd_ring->count)
1789 next_next = 0;
1790 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1791 next_info = &rfd_ring->buffer_info[next_next];
1792 num_alloc++;
1793 }
1794
1795 if (num_alloc) {
1796 /* TODO: update mailbox here */
1797 wmb();
1798 rfd_ring->next_to_use = rfd_next_to_use;
1799 AT_WRITE_REG(&adapter->hw, atl1c_rfd_prod_idx_regs[ringid],
1800 rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
1801 }
1802
1803 return num_alloc;
1804}
1805
1806static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
1807 struct atl1c_recv_ret_status *rrs, u16 num)
1808{
1809 u16 i;
1810 /* the relationship between rrd and rfd is one map one */
1811 for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
1812 rrd_ring->next_to_clean)) {
1813 rrs->word3 &= ~RRS_RXD_UPDATED;
1814 if (++rrd_ring->next_to_clean == rrd_ring->count)
1815 rrd_ring->next_to_clean = 0;
1816 }
1817}
1818
1819static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
1820 struct atl1c_recv_ret_status *rrs, u16 num)
1821{
1822 u16 i;
1823 u16 rfd_index;
1824 struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
1825
1826 rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
1827 RRS_RX_RFD_INDEX_MASK;
1828 for (i = 0; i < num; i++) {
1829 buffer_info[rfd_index].skb = NULL;
1830 ATL1C_SET_BUFFER_STATE(&buffer_info[rfd_index],
1831 ATL1C_BUFFER_FREE);
1832 if (++rfd_index == rfd_ring->count)
1833 rfd_index = 0;
1834 }
1835 rfd_ring->next_to_clean = rfd_index;
1836}
1837
1838static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
1839 int *work_done, int work_to_do)
1840{
1841 u16 rfd_num, rfd_index;
1842 u16 count = 0;
1843 u16 length;
1844 struct pci_dev *pdev = adapter->pdev;
1845 struct net_device *netdev = adapter->netdev;
1846 struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[que];
1847 struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring[que];
1848 struct sk_buff *skb;
1849 struct atl1c_recv_ret_status *rrs;
1850 struct atl1c_buffer *buffer_info;
1851
1852 while (1) {
1853 if (*work_done >= work_to_do)
1854 break;
1855 rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
1856 if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
1857 rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
1858 RRS_RX_RFD_CNT_MASK;
1859 if (unlikely(rfd_num != 1))
1860 /* TODO support mul rfd*/
1861 if (netif_msg_rx_err(adapter))
1862 dev_warn(&pdev->dev,
1863 "Multi rfd not support yet!\n");
1864 goto rrs_checked;
1865 } else {
1866 break;
1867 }
1868rrs_checked:
1869 atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
1870 if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
1871 atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
1872 if (netif_msg_rx_err(adapter))
1873 dev_warn(&pdev->dev,
1874 "wrong packet! rrs word3 is %x\n",
1875 rrs->word3);
1876 continue;
1877 }
1878
1879 length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
1880 RRS_PKT_SIZE_MASK);
1881 /* Good Receive */
1882 if (likely(rfd_num == 1)) {
1883 rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
1884 RRS_RX_RFD_INDEX_MASK;
1885 buffer_info = &rfd_ring->buffer_info[rfd_index];
1886 pci_unmap_single(pdev, buffer_info->dma,
1887 buffer_info->length, PCI_DMA_FROMDEVICE);
1888 skb = buffer_info->skb;
1889 } else {
1890 /* TODO */
1891 if (netif_msg_rx_err(adapter))
1892 dev_warn(&pdev->dev,
1893 "Multi rfd not support yet!\n");
1894 break;
1895 }
1896 atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
1897 skb_put(skb, length - ETH_FCS_LEN);
1898 skb->protocol = eth_type_trans(skb, netdev);
1899 atl1c_rx_checksum(adapter, skb, rrs);
1900 if (rrs->word3 & RRS_VLAN_INS) {
1901 u16 vlan;
1902
1903 AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
1904 vlan = le16_to_cpu(vlan);
1905 __vlan_hwaccel_put_tag(skb, vlan);
1906 }
1907 netif_receive_skb(skb);
1908
1909 (*work_done)++;
1910 count++;
1911 }
1912 if (count)
1913 atl1c_alloc_rx_buffer(adapter, que);
1914}
1915
1916/*
1917 * atl1c_clean - NAPI Rx polling callback
1918 * @adapter: board private structure
1919 */
1920static int atl1c_clean(struct napi_struct *napi, int budget)
1921{
1922 struct atl1c_adapter *adapter =
1923 container_of(napi, struct atl1c_adapter, napi);
1924 int work_done = 0;
1925
1926 /* Keep link state information with original netdev */
1927 if (!netif_carrier_ok(adapter->netdev))
1928 goto quit_polling;
1929 /* just enable one RXQ */
1930 atl1c_clean_rx_irq(adapter, 0, &work_done, budget);
1931
1932 if (work_done < budget) {
1933quit_polling:
1934 napi_complete(napi);
1935 adapter->hw.intr_mask |= ISR_RX_PKT;
1936 AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
1937 }
1938 return work_done;
1939}
1940
1941#ifdef CONFIG_NET_POLL_CONTROLLER
1942
1943/*
1944 * Polling 'interrupt' - used by things like netconsole to send skbs
1945 * without having to re-enable interrupts. It's not called while
1946 * the interrupt routine is executing.
1947 */
1948static void atl1c_netpoll(struct net_device *netdev)
1949{
1950 struct atl1c_adapter *adapter = netdev_priv(netdev);
1951
1952 disable_irq(adapter->pdev->irq);
1953 atl1c_intr(adapter->pdev->irq, netdev);
1954 enable_irq(adapter->pdev->irq);
1955}
1956#endif
1957
1958static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
1959{
1960 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
1961 u16 next_to_use = 0;
1962 u16 next_to_clean = 0;
1963
1964 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
1965 next_to_use = tpd_ring->next_to_use;
1966
1967 return (u16)(next_to_clean > next_to_use) ?
1968 (next_to_clean - next_to_use - 1) :
1969 (tpd_ring->count + next_to_clean - next_to_use - 1);
1970}
1971
1972/*
1973 * get next usable tpd
1974 * Note: should call atl1c_tdp_avail to make sure
1975 * there is enough tpd to use
1976 */
1977static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
1978 enum atl1c_trans_queue type)
1979{
1980 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
1981 struct atl1c_tpd_desc *tpd_desc;
1982 u16 next_to_use = 0;
1983
1984 next_to_use = tpd_ring->next_to_use;
1985 if (++tpd_ring->next_to_use == tpd_ring->count)
1986 tpd_ring->next_to_use = 0;
1987 tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
1988 memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
1989 return tpd_desc;
1990}
1991
1992static struct atl1c_buffer *
1993atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
1994{
1995 struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
1996
1997 return &tpd_ring->buffer_info[tpd -
1998 (struct atl1c_tpd_desc *)tpd_ring->desc];
1999}
2000
2001/* Calculate the transmit packet descript needed*/
2002static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
2003{
2004 u16 tpd_req;
2005 u16 proto_hdr_len = 0;
2006
2007 tpd_req = skb_shinfo(skb)->nr_frags + 1;
2008
2009 if (skb_is_gso(skb)) {
2010 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2011 if (proto_hdr_len < skb_headlen(skb))
2012 tpd_req++;
2013 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
2014 tpd_req++;
2015 }
2016 return tpd_req;
2017}
2018
2019static int atl1c_tso_csum(struct atl1c_adapter *adapter,
2020 struct sk_buff *skb,
2021 struct atl1c_tpd_desc **tpd,
2022 enum atl1c_trans_queue type)
2023{
2024 struct pci_dev *pdev = adapter->pdev;
2025 u8 hdr_len;
2026 u32 real_len;
2027 unsigned short offload_type;
2028 int err;
2029
2030 if (skb_is_gso(skb)) {
2031 if (skb_header_cloned(skb)) {
2032 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2033 if (unlikely(err))
2034 return -1;
2035 }
2036 offload_type = skb_shinfo(skb)->gso_type;
2037
2038 if (offload_type & SKB_GSO_TCPV4) {
2039 real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
2040 + ntohs(ip_hdr(skb)->tot_len));
2041
2042 if (real_len < skb->len)
2043 pskb_trim(skb, real_len);
2044
2045 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2046 if (unlikely(skb->len == hdr_len)) {
2047 /* only xsum need */
2048 if (netif_msg_tx_queued(adapter))
2049 dev_warn(&pdev->dev,
2050 "IPV4 tso with zero data??\n");
2051 goto check_sum;
2052 } else {
2053 ip_hdr(skb)->check = 0;
2054 tcp_hdr(skb)->check = ~csum_tcpudp_magic(
2055 ip_hdr(skb)->saddr,
2056 ip_hdr(skb)->daddr,
2057 0, IPPROTO_TCP, 0);
2058 (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
2059 }
2060 }
2061
2062 if (offload_type & SKB_GSO_TCPV6) {
2063 struct atl1c_tpd_ext_desc *etpd =
2064 *(struct atl1c_tpd_ext_desc **)(tpd);
2065
2066 memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
2067 *tpd = atl1c_get_tpd(adapter, type);
2068 ipv6_hdr(skb)->payload_len = 0;
2069 /* check payload == 0 byte ? */
2070 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2071 if (unlikely(skb->len == hdr_len)) {
2072 /* only xsum need */
2073 if (netif_msg_tx_queued(adapter))
2074 dev_warn(&pdev->dev,
2075 "IPV6 tso with zero data??\n");
2076 goto check_sum;
2077 } else
2078 tcp_hdr(skb)->check = ~csum_ipv6_magic(
2079 &ipv6_hdr(skb)->saddr,
2080 &ipv6_hdr(skb)->daddr,
2081 0, IPPROTO_TCP, 0);
2082 etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
2083 etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
2084 etpd->pkt_len = cpu_to_le32(skb->len);
2085 (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
2086 }
2087
2088 (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
2089 (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
2090 TPD_TCPHDR_OFFSET_SHIFT;
2091 (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
2092 TPD_MSS_SHIFT;
2093 return 0;
2094 }
2095
2096check_sum:
2097 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2098 u8 css, cso;
2099 cso = skb_checksum_start_offset(skb);
2100
2101 if (unlikely(cso & 0x1)) {
2102 if (netif_msg_tx_err(adapter))
2103 dev_err(&adapter->pdev->dev,
2104 "payload offset should not an event number\n");
2105 return -1;
2106 } else {
2107 css = cso + skb->csum_offset;
2108
2109 (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
2110 TPD_PLOADOFFSET_SHIFT;
2111 (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
2112 TPD_CCSUM_OFFSET_SHIFT;
2113 (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
2114 }
2115 }
2116 return 0;
2117}
2118
2119static void atl1c_tx_map(struct atl1c_adapter *adapter,
2120 struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
2121 enum atl1c_trans_queue type)
2122{
2123 struct atl1c_tpd_desc *use_tpd = NULL;
2124 struct atl1c_buffer *buffer_info = NULL;
2125 u16 buf_len = skb_headlen(skb);
2126 u16 map_len = 0;
2127 u16 mapped_len = 0;
2128 u16 hdr_len = 0;
2129 u16 nr_frags;
2130 u16 f;
2131 int tso;
2132
2133 nr_frags = skb_shinfo(skb)->nr_frags;
2134 tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
2135 if (tso) {
2136 /* TSO */
2137 map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2138 use_tpd = tpd;
2139
2140 buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
2141 buffer_info->length = map_len;
2142 buffer_info->dma = pci_map_single(adapter->pdev,
2143 skb->data, hdr_len, PCI_DMA_TODEVICE);
2144 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
2145 ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
2146 ATL1C_PCIMAP_TODEVICE);
2147 mapped_len += map_len;
2148 use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2149 use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
2150 }
2151
2152 if (mapped_len < buf_len) {
2153 /* mapped_len == 0, means we should use the first tpd,
2154 which is given by caller */
2155 if (mapped_len == 0)
2156 use_tpd = tpd;
2157 else {
2158 use_tpd = atl1c_get_tpd(adapter, type);
2159 memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
2160 }
2161 buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
2162 buffer_info->length = buf_len - mapped_len;
2163 buffer_info->dma =
2164 pci_map_single(adapter->pdev, skb->data + mapped_len,
2165 buffer_info->length, PCI_DMA_TODEVICE);
2166 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
2167 ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
2168 ATL1C_PCIMAP_TODEVICE);
2169 use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2170 use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
2171 }
2172
2173 for (f = 0; f < nr_frags; f++) {
2174 struct skb_frag_struct *frag;
2175
2176 frag = &skb_shinfo(skb)->frags[f];
2177
2178 use_tpd = atl1c_get_tpd(adapter, type);
2179 memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
2180
2181 buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
2182 buffer_info->length = frag->size;
2183 buffer_info->dma =
2184 pci_map_page(adapter->pdev, frag->page,
2185 frag->page_offset,
2186 buffer_info->length,
2187 PCI_DMA_TODEVICE);
2188 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
2189 ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_PAGE,
2190 ATL1C_PCIMAP_TODEVICE);
2191 use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2192 use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
2193 }
2194
2195 /* The last tpd */
2196 use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
2197 /* The last buffer info contain the skb address,
2198 so it will be free after unmap */
2199 buffer_info->skb = skb;
2200}
2201
2202static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
2203 struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
2204{
2205 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
2206 u32 prod_data;
2207
2208 AT_READ_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, &prod_data);
2209 switch (type) {
2210 case atl1c_trans_high:
2211 prod_data &= 0xFFFF0000;
2212 prod_data |= tpd_ring->next_to_use & 0xFFFF;
2213 break;
2214 case atl1c_trans_normal:
2215 prod_data &= 0x0000FFFF;
2216 prod_data |= (tpd_ring->next_to_use & 0xFFFF) << 16;
2217 break;
2218 default:
2219 break;
2220 }
2221 wmb();
2222 AT_WRITE_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, prod_data);
2223}
2224
2225static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
2226 struct net_device *netdev)
2227{
2228 struct atl1c_adapter *adapter = netdev_priv(netdev);
2229 unsigned long flags;
2230 u16 tpd_req = 1;
2231 struct atl1c_tpd_desc *tpd;
2232 enum atl1c_trans_queue type = atl1c_trans_normal;
2233
2234 if (test_bit(__AT_DOWN, &adapter->flags)) {
2235 dev_kfree_skb_any(skb);
2236 return NETDEV_TX_OK;
2237 }
2238
2239 tpd_req = atl1c_cal_tpd_req(skb);
2240 if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
2241 if (netif_msg_pktdata(adapter))
2242 dev_info(&adapter->pdev->dev, "tx locked\n");
2243 return NETDEV_TX_LOCKED;
2244 }
2245 if (skb->mark == 0x01)
2246 type = atl1c_trans_high;
2247 else
2248 type = atl1c_trans_normal;
2249
2250 if (atl1c_tpd_avail(adapter, type) < tpd_req) {
2251 /* no enough descriptor, just stop queue */
2252 netif_stop_queue(netdev);
2253 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2254 return NETDEV_TX_BUSY;
2255 }
2256
2257 tpd = atl1c_get_tpd(adapter, type);
2258
2259 /* do TSO and check sum */
2260 if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
2261 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2262 dev_kfree_skb_any(skb);
2263 return NETDEV_TX_OK;
2264 }
2265
2266 if (unlikely(vlan_tx_tag_present(skb))) {
2267 u16 vlan = vlan_tx_tag_get(skb);
2268 __le16 tag;
2269
2270 vlan = cpu_to_le16(vlan);
2271 AT_VLAN_TO_TAG(vlan, tag);
2272 tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
2273 tpd->vlan_tag = tag;
2274 }
2275
2276 if (skb_network_offset(skb) != ETH_HLEN)
2277 tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
2278
2279 atl1c_tx_map(adapter, skb, tpd, type);
2280 atl1c_tx_queue(adapter, skb, tpd, type);
2281
2282 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2283 return NETDEV_TX_OK;
2284}
2285
2286static void atl1c_free_irq(struct atl1c_adapter *adapter)
2287{
2288 struct net_device *netdev = adapter->netdev;
2289
2290 free_irq(adapter->pdev->irq, netdev);
2291
2292 if (adapter->have_msi)
2293 pci_disable_msi(adapter->pdev);
2294}
2295
2296static int atl1c_request_irq(struct atl1c_adapter *adapter)
2297{
2298 struct pci_dev *pdev = adapter->pdev;
2299 struct net_device *netdev = adapter->netdev;
2300 int flags = 0;
2301 int err = 0;
2302
2303 adapter->have_msi = true;
2304 err = pci_enable_msi(adapter->pdev);
2305 if (err) {
2306 if (netif_msg_ifup(adapter))
2307 dev_err(&pdev->dev,
2308 "Unable to allocate MSI interrupt Error: %d\n",
2309 err);
2310 adapter->have_msi = false;
2311 } else
2312 netdev->irq = pdev->irq;
2313
2314 if (!adapter->have_msi)
2315 flags |= IRQF_SHARED;
2316 err = request_irq(adapter->pdev->irq, atl1c_intr, flags,
2317 netdev->name, netdev);
2318 if (err) {
2319 if (netif_msg_ifup(adapter))
2320 dev_err(&pdev->dev,
2321 "Unable to allocate interrupt Error: %d\n",
2322 err);
2323 if (adapter->have_msi)
2324 pci_disable_msi(adapter->pdev);
2325 return err;
2326 }
2327 if (netif_msg_ifup(adapter))
2328 dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
2329 return err;
2330}
2331
2332static int atl1c_up(struct atl1c_adapter *adapter)
2333{
2334 struct net_device *netdev = adapter->netdev;
2335 int num;
2336 int err;
2337 int i;
2338
2339 netif_carrier_off(netdev);
2340 atl1c_init_ring_ptrs(adapter);
2341 atl1c_set_multi(netdev);
2342 atl1c_restore_vlan(adapter);
2343
2344 for (i = 0; i < adapter->num_rx_queues; i++) {
2345 num = atl1c_alloc_rx_buffer(adapter, i);
2346 if (unlikely(num == 0)) {
2347 err = -ENOMEM;
2348 goto err_alloc_rx;
2349 }
2350 }
2351
2352 if (atl1c_configure(adapter)) {
2353 err = -EIO;
2354 goto err_up;
2355 }
2356
2357 err = atl1c_request_irq(adapter);
2358 if (unlikely(err))
2359 goto err_up;
2360
2361 clear_bit(__AT_DOWN, &adapter->flags);
2362 napi_enable(&adapter->napi);
2363 atl1c_irq_enable(adapter);
2364 atl1c_check_link_status(adapter);
2365 netif_start_queue(netdev);
2366 return err;
2367
2368err_up:
2369err_alloc_rx:
2370 atl1c_clean_rx_ring(adapter);
2371 return err;
2372}
2373
2374static void atl1c_down(struct atl1c_adapter *adapter)
2375{
2376 struct net_device *netdev = adapter->netdev;
2377
2378 atl1c_del_timer(adapter);
2379 adapter->work_event = 0; /* clear all event */
2380 /* signal that we're down so the interrupt handler does not
2381 * reschedule our watchdog timer */
2382 set_bit(__AT_DOWN, &adapter->flags);
2383 netif_carrier_off(netdev);
2384 napi_disable(&adapter->napi);
2385 atl1c_irq_disable(adapter);
2386 atl1c_free_irq(adapter);
2387 /* reset MAC to disable all RX/TX */
2388 atl1c_reset_mac(&adapter->hw);
2389 msleep(1);
2390
2391 adapter->link_speed = SPEED_0;
2392 adapter->link_duplex = -1;
2393 atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
2394 atl1c_clean_tx_ring(adapter, atl1c_trans_high);
2395 atl1c_clean_rx_ring(adapter);
2396}
2397
2398/*
2399 * atl1c_open - Called when a network interface is made active
2400 * @netdev: network interface device structure
2401 *
2402 * Returns 0 on success, negative value on failure
2403 *
2404 * The open entry point is called when a network interface is made
2405 * active by the system (IFF_UP). At this point all resources needed
2406 * for transmit and receive operations are allocated, the interrupt
2407 * handler is registered with the OS, the watchdog timer is started,
2408 * and the stack is notified that the interface is ready.
2409 */
2410static int atl1c_open(struct net_device *netdev)
2411{
2412 struct atl1c_adapter *adapter = netdev_priv(netdev);
2413 int err;
2414
2415 /* disallow open during test */
2416 if (test_bit(__AT_TESTING, &adapter->flags))
2417 return -EBUSY;
2418
2419 /* allocate rx/tx dma buffer & descriptors */
2420 err = atl1c_setup_ring_resources(adapter);
2421 if (unlikely(err))
2422 return err;
2423
2424 err = atl1c_up(adapter);
2425 if (unlikely(err))
2426 goto err_up;
2427
2428 if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
2429 u32 phy_data;
2430
2431 AT_READ_REG(&adapter->hw, REG_MDIO_CTRL, &phy_data);
2432 phy_data |= MDIO_AP_EN;
2433 AT_WRITE_REG(&adapter->hw, REG_MDIO_CTRL, phy_data);
2434 }
2435 return 0;
2436
2437err_up:
2438 atl1c_free_irq(adapter);
2439 atl1c_free_ring_resources(adapter);
2440 atl1c_reset_mac(&adapter->hw);
2441 return err;
2442}
2443
2444/*
2445 * atl1c_close - Disables a network interface
2446 * @netdev: network interface device structure
2447 *
2448 * Returns 0, this is not allowed to fail
2449 *
2450 * The close entry point is called when an interface is de-activated
2451 * by the OS. The hardware is still under the drivers control, but
2452 * needs to be disabled. A global MAC reset is issued to stop the
2453 * hardware, and all transmit and receive resources are freed.
2454 */
2455static int atl1c_close(struct net_device *netdev)
2456{
2457 struct atl1c_adapter *adapter = netdev_priv(netdev);
2458
2459 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2460 atl1c_down(adapter);
2461 atl1c_free_ring_resources(adapter);
2462 return 0;
2463}
2464
2465static int atl1c_suspend(struct device *dev)
2466{
2467 struct pci_dev *pdev = to_pci_dev(dev);
2468 struct net_device *netdev = pci_get_drvdata(pdev);
2469 struct atl1c_adapter *adapter = netdev_priv(netdev);
2470 struct atl1c_hw *hw = &adapter->hw;
2471 u32 mac_ctrl_data = 0;
2472 u32 master_ctrl_data = 0;
2473 u32 wol_ctrl_data = 0;
2474 u16 mii_intr_status_data = 0;
2475 u32 wufc = adapter->wol;
2476
2477 atl1c_disable_l0s_l1(hw);
2478 if (netif_running(netdev)) {
2479 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2480 atl1c_down(adapter);
2481 }
2482 netif_device_detach(netdev);
2483
2484 if (wufc)
2485 if (atl1c_phy_power_saving(hw) != 0)
2486 dev_dbg(&pdev->dev, "phy power saving failed");
2487
2488 AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
2489 AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
2490
2491 master_ctrl_data &= ~MASTER_CTRL_CLK_SEL_DIS;
2492 mac_ctrl_data &= ~(MAC_CTRL_PRMLEN_MASK << MAC_CTRL_PRMLEN_SHIFT);
2493 mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
2494 MAC_CTRL_PRMLEN_MASK) <<
2495 MAC_CTRL_PRMLEN_SHIFT);
2496 mac_ctrl_data &= ~(MAC_CTRL_SPEED_MASK << MAC_CTRL_SPEED_SHIFT);
2497 mac_ctrl_data &= ~MAC_CTRL_DUPLX;
2498
2499 if (wufc) {
2500 mac_ctrl_data |= MAC_CTRL_RX_EN;
2501 if (adapter->link_speed == SPEED_1000 ||
2502 adapter->link_speed == SPEED_0) {
2503 mac_ctrl_data |= atl1c_mac_speed_1000 <<
2504 MAC_CTRL_SPEED_SHIFT;
2505 mac_ctrl_data |= MAC_CTRL_DUPLX;
2506 } else
2507 mac_ctrl_data |= atl1c_mac_speed_10_100 <<
2508 MAC_CTRL_SPEED_SHIFT;
2509
2510 if (adapter->link_duplex == DUPLEX_FULL)
2511 mac_ctrl_data |= MAC_CTRL_DUPLX;
2512
2513 /* turn on magic packet wol */
2514 if (wufc & AT_WUFC_MAG)
2515 wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
2516
2517 if (wufc & AT_WUFC_LNKC) {
2518 wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
2519 /* only link up can wake up */
2520 if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) {
2521 dev_dbg(&pdev->dev, "%s: read write phy "
2522 "register failed.\n",
2523 atl1c_driver_name);
2524 }
2525 }
2526 /* clear phy interrupt */
2527 atl1c_read_phy_reg(hw, MII_ISR, &mii_intr_status_data);
2528 /* Config MAC Ctrl register */
2529 __atl1c_vlan_mode(netdev->features, &mac_ctrl_data);
2530
2531 /* magic packet maybe Broadcast&multicast&Unicast frame */
2532 if (wufc & AT_WUFC_MAG)
2533 mac_ctrl_data |= MAC_CTRL_BC_EN;
2534
2535 dev_dbg(&pdev->dev,
2536 "%s: suspend MAC=0x%x\n",
2537 atl1c_driver_name, mac_ctrl_data);
2538 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
2539 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
2540 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2541
2542 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
2543 GPHY_CTRL_EXT_RESET);
2544 } else {
2545 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_POWER_SAVING);
2546 master_ctrl_data |= MASTER_CTRL_CLK_SEL_DIS;
2547 mac_ctrl_data |= atl1c_mac_speed_10_100 << MAC_CTRL_SPEED_SHIFT;
2548 mac_ctrl_data |= MAC_CTRL_DUPLX;
2549 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
2550 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2551 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
2552 hw->phy_configured = false; /* re-init PHY when resume */
2553 }
2554
2555 return 0;
2556}
2557
2558#ifdef CONFIG_PM_SLEEP
2559static int atl1c_resume(struct device *dev)
2560{
2561 struct pci_dev *pdev = to_pci_dev(dev);
2562 struct net_device *netdev = pci_get_drvdata(pdev);
2563 struct atl1c_adapter *adapter = netdev_priv(netdev);
2564
2565 AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
2566 atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
2567 ATL1C_PCIE_PHY_RESET);
2568
2569 atl1c_phy_reset(&adapter->hw);
2570 atl1c_reset_mac(&adapter->hw);
2571 atl1c_phy_init(&adapter->hw);
2572
2573#if 0
2574 AT_READ_REG(&adapter->hw, REG_PM_CTRLSTAT, &pm_data);
2575 pm_data &= ~PM_CTRLSTAT_PME_EN;
2576 AT_WRITE_REG(&adapter->hw, REG_PM_CTRLSTAT, pm_data);
2577#endif
2578
2579 netif_device_attach(netdev);
2580 if (netif_running(netdev))
2581 atl1c_up(adapter);
2582
2583 return 0;
2584}
2585#endif
2586
2587static void atl1c_shutdown(struct pci_dev *pdev)
2588{
2589 struct net_device *netdev = pci_get_drvdata(pdev);
2590 struct atl1c_adapter *adapter = netdev_priv(netdev);
2591
2592 atl1c_suspend(&pdev->dev);
2593 pci_wake_from_d3(pdev, adapter->wol);
2594 pci_set_power_state(pdev, PCI_D3hot);
2595}
2596
2597static const struct net_device_ops atl1c_netdev_ops = {
2598 .ndo_open = atl1c_open,
2599 .ndo_stop = atl1c_close,
2600 .ndo_validate_addr = eth_validate_addr,
2601 .ndo_start_xmit = atl1c_xmit_frame,
2602 .ndo_set_mac_address = atl1c_set_mac_addr,
2603 .ndo_set_multicast_list = atl1c_set_multi,
2604 .ndo_change_mtu = atl1c_change_mtu,
2605 .ndo_fix_features = atl1c_fix_features,
2606 .ndo_set_features = atl1c_set_features,
2607 .ndo_do_ioctl = atl1c_ioctl,
2608 .ndo_tx_timeout = atl1c_tx_timeout,
2609 .ndo_get_stats = atl1c_get_stats,
2610#ifdef CONFIG_NET_POLL_CONTROLLER
2611 .ndo_poll_controller = atl1c_netpoll,
2612#endif
2613};
2614
2615static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
2616{
2617 SET_NETDEV_DEV(netdev, &pdev->dev);
2618 pci_set_drvdata(pdev, netdev);
2619
2620 netdev->irq = pdev->irq;
2621 netdev->netdev_ops = &atl1c_netdev_ops;
2622 netdev->watchdog_timeo = AT_TX_WATCHDOG;
2623 atl1c_set_ethtool_ops(netdev);
2624
2625 /* TODO: add when ready */
2626 netdev->hw_features = NETIF_F_SG |
2627 NETIF_F_HW_CSUM |
2628 NETIF_F_HW_VLAN_RX |
2629 NETIF_F_TSO |
2630 NETIF_F_TSO6;
2631 netdev->features = netdev->hw_features |
2632 NETIF_F_HW_VLAN_TX;
2633 return 0;
2634}
2635
2636/*
2637 * atl1c_probe - Device Initialization Routine
2638 * @pdev: PCI device information struct
2639 * @ent: entry in atl1c_pci_tbl
2640 *
2641 * Returns 0 on success, negative on failure
2642 *
2643 * atl1c_probe initializes an adapter identified by a pci_dev structure.
2644 * The OS initialization, configuring of the adapter private structure,
2645 * and a hardware reset occur.
2646 */
2647static int __devinit atl1c_probe(struct pci_dev *pdev,
2648 const struct pci_device_id *ent)
2649{
2650 struct net_device *netdev;
2651 struct atl1c_adapter *adapter;
2652 static int cards_found;
2653
2654 int err = 0;
2655
2656 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2657 err = pci_enable_device_mem(pdev);
2658 if (err) {
2659 dev_err(&pdev->dev, "cannot enable PCI device\n");
2660 return err;
2661 }
2662
2663 /*
2664 * The atl1c chip can DMA to 64-bit addresses, but it uses a single
2665 * shared register for the high 32 bits, so only a single, aligned,
2666 * 4 GB physical address range can be used at a time.
2667 *
2668 * Supporting 64-bit DMA on this hardware is more trouble than it's
2669 * worth. It is far easier to limit to 32-bit DMA than update
2670 * various kernel subsystems to support the mechanics required by a
2671 * fixed-high-32-bit system.
2672 */
2673 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2674 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2675 dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
2676 goto err_dma;
2677 }
2678
2679 err = pci_request_regions(pdev, atl1c_driver_name);
2680 if (err) {
2681 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
2682 goto err_pci_reg;
2683 }
2684
2685 pci_set_master(pdev);
2686
2687 netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
2688 if (netdev == NULL) {
2689 err = -ENOMEM;
2690 dev_err(&pdev->dev, "etherdev alloc failed\n");
2691 goto err_alloc_etherdev;
2692 }
2693
2694 err = atl1c_init_netdev(netdev, pdev);
2695 if (err) {
2696 dev_err(&pdev->dev, "init netdevice failed\n");
2697 goto err_init_netdev;
2698 }
2699 adapter = netdev_priv(netdev);
2700 adapter->bd_number = cards_found;
2701 adapter->netdev = netdev;
2702 adapter->pdev = pdev;
2703 adapter->hw.adapter = adapter;
2704 adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
2705 adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
2706 if (!adapter->hw.hw_addr) {
2707 err = -EIO;
2708 dev_err(&pdev->dev, "cannot map device registers\n");
2709 goto err_ioremap;
2710 }
2711 netdev->base_addr = (unsigned long)adapter->hw.hw_addr;
2712
2713 /* init mii data */
2714 adapter->mii.dev = netdev;
2715 adapter->mii.mdio_read = atl1c_mdio_read;
2716 adapter->mii.mdio_write = atl1c_mdio_write;
2717 adapter->mii.phy_id_mask = 0x1f;
2718 adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
2719 netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
2720 setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
2721 (unsigned long)adapter);
2722 /* setup the private structure */
2723 err = atl1c_sw_init(adapter);
2724 if (err) {
2725 dev_err(&pdev->dev, "net device private data init failed\n");
2726 goto err_sw_init;
2727 }
2728 atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
2729 ATL1C_PCIE_PHY_RESET);
2730
2731 /* Init GPHY as early as possible due to power saving issue */
2732 atl1c_phy_reset(&adapter->hw);
2733
2734 err = atl1c_reset_mac(&adapter->hw);
2735 if (err) {
2736 err = -EIO;
2737 goto err_reset;
2738 }
2739
2740 /* reset the controller to
2741 * put the device in a known good starting state */
2742 err = atl1c_phy_init(&adapter->hw);
2743 if (err) {
2744 err = -EIO;
2745 goto err_reset;
2746 }
2747 if (atl1c_read_mac_addr(&adapter->hw) != 0) {
2748 err = -EIO;
2749 dev_err(&pdev->dev, "get mac address failed\n");
2750 goto err_eeprom;
2751 }
2752 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2753 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
2754 if (netif_msg_probe(adapter))
2755 dev_dbg(&pdev->dev, "mac address : %pM\n",
2756 adapter->hw.mac_addr);
2757
2758 atl1c_hw_set_mac_addr(&adapter->hw);
2759 INIT_WORK(&adapter->common_task, atl1c_common_task);
2760 adapter->work_event = 0;
2761 err = register_netdev(netdev);
2762 if (err) {
2763 dev_err(&pdev->dev, "register netdevice failed\n");
2764 goto err_register;
2765 }
2766
2767 if (netif_msg_probe(adapter))
2768 dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
2769 cards_found++;
2770 return 0;
2771
2772err_reset:
2773err_register:
2774err_sw_init:
2775err_eeprom:
2776 iounmap(adapter->hw.hw_addr);
2777err_init_netdev:
2778err_ioremap:
2779 free_netdev(netdev);
2780err_alloc_etherdev:
2781 pci_release_regions(pdev);
2782err_pci_reg:
2783err_dma:
2784 pci_disable_device(pdev);
2785 return err;
2786}
2787
2788/*
2789 * atl1c_remove - Device Removal Routine
2790 * @pdev: PCI device information struct
2791 *
2792 * atl1c_remove is called by the PCI subsystem to alert the driver
2793 * that it should release a PCI device. The could be caused by a
2794 * Hot-Plug event, or because the driver is going to be removed from
2795 * memory.
2796 */
2797static void __devexit atl1c_remove(struct pci_dev *pdev)
2798{
2799 struct net_device *netdev = pci_get_drvdata(pdev);
2800 struct atl1c_adapter *adapter = netdev_priv(netdev);
2801
2802 unregister_netdev(netdev);
2803 atl1c_phy_disable(&adapter->hw);
2804
2805 iounmap(adapter->hw.hw_addr);
2806
2807 pci_release_regions(pdev);
2808 pci_disable_device(pdev);
2809 free_netdev(netdev);
2810}
2811
2812/*
2813 * atl1c_io_error_detected - called when PCI error is detected
2814 * @pdev: Pointer to PCI device
2815 * @state: The current pci connection state
2816 *
2817 * This function is called after a PCI bus error affecting
2818 * this device has been detected.
2819 */
2820static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
2821 pci_channel_state_t state)
2822{
2823 struct net_device *netdev = pci_get_drvdata(pdev);
2824 struct atl1c_adapter *adapter = netdev_priv(netdev);
2825
2826 netif_device_detach(netdev);
2827
2828 if (state == pci_channel_io_perm_failure)
2829 return PCI_ERS_RESULT_DISCONNECT;
2830
2831 if (netif_running(netdev))
2832 atl1c_down(adapter);
2833
2834 pci_disable_device(pdev);
2835
2836 /* Request a slot slot reset. */
2837 return PCI_ERS_RESULT_NEED_RESET;
2838}
2839
2840/*
2841 * atl1c_io_slot_reset - called after the pci bus has been reset.
2842 * @pdev: Pointer to PCI device
2843 *
2844 * Restart the card from scratch, as if from a cold-boot. Implementation
2845 * resembles the first-half of the e1000_resume routine.
2846 */
2847static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
2848{
2849 struct net_device *netdev = pci_get_drvdata(pdev);
2850 struct atl1c_adapter *adapter = netdev_priv(netdev);
2851
2852 if (pci_enable_device(pdev)) {
2853 if (netif_msg_hw(adapter))
2854 dev_err(&pdev->dev,
2855 "Cannot re-enable PCI device after reset\n");
2856 return PCI_ERS_RESULT_DISCONNECT;
2857 }
2858 pci_set_master(pdev);
2859
2860 pci_enable_wake(pdev, PCI_D3hot, 0);
2861 pci_enable_wake(pdev, PCI_D3cold, 0);
2862
2863 atl1c_reset_mac(&adapter->hw);
2864
2865 return PCI_ERS_RESULT_RECOVERED;
2866}
2867
2868/*
2869 * atl1c_io_resume - called when traffic can start flowing again.
2870 * @pdev: Pointer to PCI device
2871 *
2872 * This callback is called when the error recovery driver tells us that
2873 * its OK to resume normal operation. Implementation resembles the
2874 * second-half of the atl1c_resume routine.
2875 */
2876static void atl1c_io_resume(struct pci_dev *pdev)
2877{
2878 struct net_device *netdev = pci_get_drvdata(pdev);
2879 struct atl1c_adapter *adapter = netdev_priv(netdev);
2880
2881 if (netif_running(netdev)) {
2882 if (atl1c_up(adapter)) {
2883 if (netif_msg_hw(adapter))
2884 dev_err(&pdev->dev,
2885 "Cannot bring device back up after reset\n");
2886 return;
2887 }
2888 }
2889
2890 netif_device_attach(netdev);
2891}
2892
2893static struct pci_error_handlers atl1c_err_handler = {
2894 .error_detected = atl1c_io_error_detected,
2895 .slot_reset = atl1c_io_slot_reset,
2896 .resume = atl1c_io_resume,
2897};
2898
2899static SIMPLE_DEV_PM_OPS(atl1c_pm_ops, atl1c_suspend, atl1c_resume);
2900
2901static struct pci_driver atl1c_driver = {
2902 .name = atl1c_driver_name,
2903 .id_table = atl1c_pci_tbl,
2904 .probe = atl1c_probe,
2905 .remove = __devexit_p(atl1c_remove),
2906 .shutdown = atl1c_shutdown,
2907 .err_handler = &atl1c_err_handler,
2908 .driver.pm = &atl1c_pm_ops,
2909};
2910
2911/*
2912 * atl1c_init_module - Driver Registration Routine
2913 *
2914 * atl1c_init_module is the first routine called when the driver is
2915 * loaded. All it does is register with the PCI subsystem.
2916 */
2917static int __init atl1c_init_module(void)
2918{
2919 return pci_register_driver(&atl1c_driver);
2920}
2921
2922/*
2923 * atl1c_exit_module - Driver Exit Cleanup Routine
2924 *
2925 * atl1c_exit_module is called just before the driver is removed
2926 * from memory.
2927 */
2928static void __exit atl1c_exit_module(void)
2929{
2930 pci_unregister_driver(&atl1c_driver);
2931}
2932
2933module_init(atl1c_init_module);
2934module_exit(atl1c_exit_module);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-30 11:43:03 -0500