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authorLuis R. Rodriguez <lrodriguez@atheros.com>2010-02-16 18:16:45 -0500
committerDavid S. Miller <davem@davemloft.net>2010-02-16 18:16:45 -0500
commit496c185c9495629ef1c65387cb2594578393cfe0 (patch)
tree4bf3e64ffd535328d9b5f05740d411298982cc37 /drivers/net/atl1c/atl1c_hw.h
parentd5aa407f59f5b83d2c50ec88f5bf56d40f1f8978 (diff)
atl1c: Add support for Atheros AR8152 and AR8152
AR8151 is a Gigabit Ethernet device. AR8152 devices are Fast Ethernet devices, there are two revisions, a 1.0 and a 2.0 revision. This has been tested against these devices: Driver Model-name vendor:device Type atl1c AR8131 1969:1063 Gigabit Ethernet atl1c AR8132 1969:1062 Fast Ethernet atl1c AR8151(v1.0) 1969:1073 Gigabit Ethernet atl1c AR8152(v1.1) 1969:2060 Fast Ethernet This device has no hardware available yet so it goes untested, but it should work: atl1c AR8152(v2.0) 1969:2062 Fast Ethernet Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/atl1c/atl1c_hw.h')
-rw-r--r--drivers/net/atl1c/atl1c_hw.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/net/atl1c/atl1c_hw.h b/drivers/net/atl1c/atl1c_hw.h
index c2c738df5c63..1eeb3ed9f0cb 100644
--- a/drivers/net/atl1c/atl1c_hw.h
+++ b/drivers/net/atl1c/atl1c_hw.h
@@ -57,6 +57,7 @@ int atl1c_restart_autoneg(struct atl1c_hw *hw);
57#define REG_LINK_CTRL 0x68 57#define REG_LINK_CTRL 0x68
58#define LINK_CTRL_L0S_EN 0x01 58#define LINK_CTRL_L0S_EN 0x01
59#define LINK_CTRL_L1_EN 0x02 59#define LINK_CTRL_L1_EN 0x02
60#define LINK_CTRL_EXT_SYNC 0x80
60 61
61#define REG_VPD_CAP 0x6C 62#define REG_VPD_CAP 0x6C
62#define VPD_CAP_ID_MASK 0xff 63#define VPD_CAP_ID_MASK 0xff
@@ -156,6 +157,8 @@ int atl1c_restart_autoneg(struct atl1c_hw *hw);
156#define PM_CTRL_PM_REQ_TIMER_SHIFT 20 157#define PM_CTRL_PM_REQ_TIMER_SHIFT 20
157#define PM_CTRL_LCKDET_TIMER_MASK 0x3F 158#define PM_CTRL_LCKDET_TIMER_MASK 0x3F
158#define PM_CTRL_LCKDET_TIMER_SHIFT 24 159#define PM_CTRL_LCKDET_TIMER_SHIFT 24
160#define PM_CTRL_EN_BUFS_RX_L0S 0x10000000
161#define PM_CTRL_SA_DLY_EN 0x20000000
159#define PM_CTRL_MAC_ASPM_CHK 0x40000000 162#define PM_CTRL_MAC_ASPM_CHK 0x40000000
160#define PM_CTRL_HOTRST 0x80000000 163#define PM_CTRL_HOTRST 0x80000000
161 164
@@ -314,6 +317,8 @@ int atl1c_restart_autoneg(struct atl1c_hw *hw);
314#define MAC_CTRL_BC_EN 0x4000000 317#define MAC_CTRL_BC_EN 0x4000000
315#define MAC_CTRL_DBG 0x8000000 318#define MAC_CTRL_DBG 0x8000000
316#define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000 319#define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000
320#define MAC_CTRL_HASH_ALG_CRC32 0x20000000
321#define MAC_CTRL_SPEED_MODE_SW 0x40000000
317 322
318/* MAC IPG/IFG Control Register */ 323/* MAC IPG/IFG Control Register */
319#define REG_MAC_IPG_IFG 0x1484 324#define REG_MAC_IPG_IFG 0x1484