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authorJay Cliburn <jacliburn@bellsouth.net>2007-02-08 10:42:37 -0500
committerJeff Garzik <jeff@garzik.org>2007-02-08 10:42:37 -0500
commitf3cc28c797604fa1cda4aef3f250f465de54a0ca (patch)
tree457722c6be1715307563a12b266bdf7910e8bb7f /drivers/net/atl1
parentc4184f117af7441fb83bc413d2214d92920e0289 (diff)
Add Attansic L1 ethernet driver.
This driver is a modified version of the Attansic reference driver for the L1 ethernet adapter. Attansic has granted permission for its inclusion in the mainline kernel. Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/atl1')
-rw-r--r--drivers/net/atl1/Makefile2
-rw-r--r--drivers/net/atl1/atl1.h283
-rw-r--r--drivers/net/atl1/atl1_ethtool.c508
-rw-r--r--drivers/net/atl1/atl1_hw.c718
-rw-r--r--drivers/net/atl1/atl1_hw.h951
-rw-r--r--drivers/net/atl1/atl1_main.c2468
-rw-r--r--drivers/net/atl1/atl1_param.c206
7 files changed, 5136 insertions, 0 deletions
diff --git a/drivers/net/atl1/Makefile b/drivers/net/atl1/Makefile
new file mode 100644
index 000000000000..a6b707e4e69e
--- /dev/null
+++ b/drivers/net/atl1/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_ATL1) += atl1.o
2atl1-y += atl1_main.o atl1_hw.o atl1_ethtool.o atl1_param.o
diff --git a/drivers/net/atl1/atl1.h b/drivers/net/atl1/atl1.h
new file mode 100644
index 000000000000..b1c6034e68fa
--- /dev/null
+++ b/drivers/net/atl1/atl1.h
@@ -0,0 +1,283 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#ifndef _ATL1_H_
25#define _ATL1_H_
26
27#include <linux/types.h>
28#include <linux/if_vlan.h>
29
30#include "atl1_hw.h"
31
32/* function prototypes needed by multiple files */
33s32 atl1_up(struct atl1_adapter *adapter);
34void atl1_down(struct atl1_adapter *adapter);
35int atl1_reset(struct atl1_adapter *adapter);
36s32 atl1_setup_ring_resources(struct atl1_adapter *adapter);
37void atl1_free_ring_resources(struct atl1_adapter *adapter);
38
39extern char atl1_driver_name[];
40extern char atl1_driver_version[];
41extern const struct ethtool_ops atl1_ethtool_ops;
42
43struct atl1_adapter;
44
45#define ATL1_MAX_INTR 3
46
47#define ATL1_DEFAULT_TPD 256
48#define ATL1_MAX_TPD 1024
49#define ATL1_MIN_TPD 64
50#define ATL1_DEFAULT_RFD 512
51#define ATL1_MIN_RFD 128
52#define ATL1_MAX_RFD 2048
53
54#define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
55#define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc)
56#define ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc)
57#define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc)
58
59/*
60 * Some workarounds require millisecond delays and are run during interrupt
61 * context. Most notably, when establishing link, the phy may need tweaking
62 * but cannot process phy register reads/writes faster than millisecond
63 * intervals...and we establish link due to a "link status change" interrupt.
64 */
65
66/*
67 * wrapper around a pointer to a socket buffer,
68 * so a DMA handle can be stored along with the buffer
69 */
70struct atl1_buffer {
71 struct sk_buff *skb;
72 u16 length;
73 u16 alloced;
74 dma_addr_t dma;
75};
76
77#define MAX_TX_BUF_LEN 0x3000 /* 12KB */
78
79struct atl1_tpd_ring {
80 void *desc; /* pointer to the descriptor ring memory */
81 dma_addr_t dma; /* physical adress of the descriptor ring */
82 u16 size; /* length of descriptor ring in bytes */
83 u16 count; /* number of descriptors in the ring */
84 u16 hw_idx; /* hardware index */
85 atomic_t next_to_clean;
86 atomic_t next_to_use;
87 struct atl1_buffer *buffer_info;
88};
89
90struct atl1_rfd_ring {
91 void *desc;
92 dma_addr_t dma;
93 u16 size;
94 u16 count;
95 atomic_t next_to_use;
96 u16 next_to_clean;
97 struct atl1_buffer *buffer_info;
98};
99
100struct atl1_rrd_ring {
101 void *desc;
102 dma_addr_t dma;
103 unsigned int size;
104 u16 count;
105 u16 next_to_use;
106 atomic_t next_to_clean;
107};
108
109struct atl1_ring_header {
110 void *desc; /* pointer to the descriptor ring memory */
111 dma_addr_t dma; /* physical adress of the descriptor ring */
112 unsigned int size; /* length of descriptor ring in bytes */
113};
114
115struct atl1_cmb {
116 struct coals_msg_block *cmb;
117 dma_addr_t dma;
118};
119
120struct atl1_smb {
121 struct stats_msg_block *smb;
122 dma_addr_t dma;
123};
124
125/* Statistics counters */
126struct atl1_sft_stats {
127 u64 rx_packets;
128 u64 tx_packets;
129 u64 rx_bytes;
130 u64 tx_bytes;
131 u64 multicast;
132 u64 collisions;
133 u64 rx_errors;
134 u64 rx_length_errors;
135 u64 rx_crc_errors;
136 u64 rx_frame_errors;
137 u64 rx_fifo_errors;
138 u64 rx_missed_errors;
139 u64 tx_errors;
140 u64 tx_fifo_errors;
141 u64 tx_aborted_errors;
142 u64 tx_window_errors;
143 u64 tx_carrier_errors;
144
145 u64 tx_pause; /* num Pause packet transmitted. */
146 u64 excecol; /* num tx packets aborted due to excessive collisions. */
147 u64 deffer; /* num deferred tx packets */
148 u64 scc; /* num packets subsequently transmitted successfully w/ single prior collision. */
149 u64 mcc; /* num packets subsequently transmitted successfully w/ multiple prior collisions. */
150 u64 latecol; /* num tx packets w/ late collisions. */
151 u64 tx_underun; /* num tx packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
152 u64 tx_trunc; /* num tx packets truncated due to size exceeding MTU, regardless whether truncated by Selene or not. (The name doesn't really reflect the meaning in this case.) */
153 u64 rx_pause; /* num Pause packets received. */
154 u64 rx_rrd_ov;
155 u64 rx_trunc;
156};
157
158/* board specific private data structure */
159#define ATL1_REGS_LEN 8
160
161/* Structure containing variables used by the shared code */
162struct atl1_hw {
163 u8 __iomem *hw_addr;
164 struct atl1_adapter *back;
165 enum atl1_dma_order dma_ord;
166 enum atl1_dma_rcb rcb_value;
167 enum atl1_dma_req_block dmar_block;
168 enum atl1_dma_req_block dmaw_block;
169 u8 preamble_len;
170 u8 max_retry; /* Retransmission maximum, after which the packet will be discarded */
171 u8 jam_ipg; /* IPG to start JAM for collision based flow control in half-duplex mode. In units of 8-bit time */
172 u8 ipgt; /* Desired back to back inter-packet gap. The default is 96-bit time */
173 u8 min_ifg; /* Minimum number of IFG to enforce in between RX frames. Frame gap below such IFP is dropped */
174 u8 ipgr1; /* 64bit Carrier-Sense window */
175 u8 ipgr2; /* 96-bit IPG window */
176 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. Each TPD is 16 bytes long */
177 u8 rfd_burst; /* Number of RFD to prefetch in cache-aligned burst. Each RFD is 12 bytes long */
178 u8 rfd_fetch_gap;
179 u8 rrd_burst; /* Threshold number of RRDs that can be retired in a burst. Each RRD is 16 bytes long */
180 u8 tpd_fetch_th;
181 u8 tpd_fetch_gap;
182 u16 tx_jumbo_task_th;
183 u16 txf_burst; /* Number of data bytes to read in a cache-aligned burst. Each SRAM entry is
184 8 bytes long */
185 u16 rx_jumbo_th; /* Jumbo packet size for non-VLAN packet. VLAN packets should add 4 bytes */
186 u16 rx_jumbo_lkah;
187 u16 rrd_ret_timer; /* RRD retirement timer. Decrement by 1 after every 512ns passes. */
188 u16 lcol; /* Collision Window */
189
190 u16 cmb_tpd;
191 u16 cmb_rrd;
192 u16 cmb_rx_timer;
193 u16 cmb_tx_timer;
194 u32 smb_timer;
195 u16 media_type;
196 u16 autoneg_advertised;
197 u16 pci_cmd_word;
198
199 u16 mii_autoneg_adv_reg;
200 u16 mii_1000t_ctrl_reg;
201
202 u32 mem_rang;
203 u32 txcw;
204 u32 max_frame_size;
205 u32 min_frame_size;
206 u32 mc_filter_type;
207 u32 num_mc_addrs;
208 u32 collision_delta;
209 u32 tx_packet_delta;
210 u16 phy_spd_default;
211
212 u16 dev_rev;
213 u8 revision_id;
214
215 /* spi flash */
216 u8 flash_vendor;
217
218 u8 dma_fairness;
219 u8 mac_addr[ETH_ALEN];
220 u8 perm_mac_addr[ETH_ALEN];
221
222 /* bool phy_preamble_sup; */
223 bool phy_configured;
224};
225
226struct atl1_adapter {
227 /* OS defined structs */
228 struct net_device *netdev;
229 struct pci_dev *pdev;
230 struct net_device_stats net_stats;
231 struct atl1_sft_stats soft_stats;
232
233 struct vlan_group *vlgrp;
234 u32 rx_buffer_len;
235 u32 wol;
236 u16 link_speed;
237 u16 link_duplex;
238 spinlock_t lock;
239 atomic_t irq_sem;
240 struct work_struct tx_timeout_task;
241 struct work_struct link_chg_task;
242 struct work_struct pcie_dma_to_rst_task;
243 struct timer_list watchdog_timer;
244 struct timer_list phy_config_timer;
245 bool phy_timer_pending;
246
247 bool mac_disabled;
248
249 /* All descriptor rings' memory */
250 struct atl1_ring_header ring_header;
251
252 /* TX */
253 struct atl1_tpd_ring tpd_ring;
254 spinlock_t mb_lock;
255
256 /* RX */
257 struct atl1_rfd_ring rfd_ring;
258 struct atl1_rrd_ring rrd_ring;
259 u64 hw_csum_err;
260 u64 hw_csum_good;
261
262 u32 gorcl;
263 u64 gorcl_old;
264
265 /* Interrupt Moderator timer ( 2us resolution) */
266 u16 imt;
267 /* Interrupt Clear timer (2us resolution) */
268 u16 ict;
269
270 /* MII interface info */
271 struct mii_if_info mii;
272
273 /* structs defined in atl1_hw.h */
274 u32 bd_number; /* board number */
275 bool pci_using_64;
276 struct atl1_hw hw;
277 struct atl1_smb smb;
278 struct atl1_cmb cmb;
279
280 u32 pci_state[16];
281};
282
283#endif /* _ATL1_H_ */
diff --git a/drivers/net/atl1/atl1_ethtool.c b/drivers/net/atl1/atl1_ethtool.c
new file mode 100644
index 000000000000..c11c27798e5c
--- /dev/null
+++ b/drivers/net/atl1/atl1_ethtool.c
@@ -0,0 +1,508 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#include <linux/types.h>
25#include <linux/pci.h>
26#include <linux/ethtool.h>
27#include <linux/netdevice.h>
28#include <linux/mii.h>
29#include <asm/uaccess.h>
30
31#include "atl1.h"
32
33struct atl1_stats {
34 char stat_string[ETH_GSTRING_LEN];
35 int sizeof_stat;
36 int stat_offset;
37};
38
39#define ATL1_STAT(m) sizeof(((struct atl1_adapter *)0)->m), \
40 offsetof(struct atl1_adapter, m)
41
42static struct atl1_stats atl1_gstrings_stats[] = {
43 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
44 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
45 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
46 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
47 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
48 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
49 {"rx_dropped", ATL1_STAT(net_stats.rx_dropped)},
50 {"tx_dropped", ATL1_STAT(net_stats.tx_dropped)},
51 {"multicast", ATL1_STAT(soft_stats.multicast)},
52 {"collisions", ATL1_STAT(soft_stats.collisions)},
53 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
54 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
55 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
56 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
57 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
58 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
59 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
60 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
61 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
62 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
63 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
64 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
65 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
66 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
67 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
68 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
69 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
70 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
71 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
72 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
73 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
74};
75
76static void atl1_get_ethtool_stats(struct net_device *netdev,
77 struct ethtool_stats *stats, u64 *data)
78{
79 struct atl1_adapter *adapter = netdev_priv(netdev);
80 int i;
81 char *p;
82
83 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
84 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
85 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
86 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
87 }
88
89}
90
91static int atl1_get_stats_count(struct net_device *netdev)
92{
93 return ARRAY_SIZE(atl1_gstrings_stats);
94}
95
96static int atl1_get_settings(struct net_device *netdev,
97 struct ethtool_cmd *ecmd)
98{
99 struct atl1_adapter *adapter = netdev_priv(netdev);
100 struct atl1_hw *hw = &adapter->hw;
101
102 ecmd->supported = (SUPPORTED_10baseT_Half |
103 SUPPORTED_10baseT_Full |
104 SUPPORTED_100baseT_Half |
105 SUPPORTED_100baseT_Full |
106 SUPPORTED_1000baseT_Full |
107 SUPPORTED_Autoneg | SUPPORTED_TP);
108 ecmd->advertising = ADVERTISED_TP;
109 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
110 hw->media_type == MEDIA_TYPE_1000M_FULL) {
111 ecmd->advertising |= ADVERTISED_Autoneg;
112 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
113 ecmd->advertising |= ADVERTISED_Autoneg;
114 ecmd->advertising |=
115 (ADVERTISED_10baseT_Half |
116 ADVERTISED_10baseT_Full |
117 ADVERTISED_100baseT_Half |
118 ADVERTISED_100baseT_Full |
119 ADVERTISED_1000baseT_Full);
120 }
121 else
122 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
123 }
124 ecmd->port = PORT_TP;
125 ecmd->phy_address = 0;
126 ecmd->transceiver = XCVR_INTERNAL;
127
128 if (netif_carrier_ok(adapter->netdev)) {
129 u16 link_speed, link_duplex;
130 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
131 ecmd->speed = link_speed;
132 if (link_duplex == FULL_DUPLEX)
133 ecmd->duplex = DUPLEX_FULL;
134 else
135 ecmd->duplex = DUPLEX_HALF;
136 } else {
137 ecmd->speed = -1;
138 ecmd->duplex = -1;
139 }
140 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
141 hw->media_type == MEDIA_TYPE_1000M_FULL)
142 ecmd->autoneg = AUTONEG_ENABLE;
143 else
144 ecmd->autoneg = AUTONEG_DISABLE;
145
146 return 0;
147}
148
149static int atl1_set_settings(struct net_device *netdev,
150 struct ethtool_cmd *ecmd)
151{
152 struct atl1_adapter *adapter = netdev_priv(netdev);
153 struct atl1_hw *hw = &adapter->hw;
154 u16 phy_data;
155 int ret_val = 0;
156 u16 old_media_type = hw->media_type;
157
158 if (netif_running(adapter->netdev)) {
159 printk(KERN_DEBUG "%s: ethtool shutting down adapter\n",
160 atl1_driver_name);
161 atl1_down(adapter);
162 }
163
164 if (ecmd->autoneg == AUTONEG_ENABLE)
165 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
166 else {
167 if (ecmd->speed == SPEED_1000) {
168 if (ecmd->duplex != DUPLEX_FULL) {
169 printk(KERN_WARNING
170 "%s: can't force to 1000M half duplex\n",
171 atl1_driver_name);
172 ret_val = -EINVAL;
173 goto exit_sset;
174 }
175 hw->media_type = MEDIA_TYPE_1000M_FULL;
176 } else if (ecmd->speed == SPEED_100) {
177 if (ecmd->duplex == DUPLEX_FULL) {
178 hw->media_type = MEDIA_TYPE_100M_FULL;
179 } else
180 hw->media_type = MEDIA_TYPE_100M_HALF;
181 } else {
182 if (ecmd->duplex == DUPLEX_FULL)
183 hw->media_type = MEDIA_TYPE_10M_FULL;
184 else
185 hw->media_type = MEDIA_TYPE_10M_HALF;
186 }
187 }
188 switch (hw->media_type) {
189 case MEDIA_TYPE_AUTO_SENSOR:
190 ecmd->advertising =
191 ADVERTISED_10baseT_Half |
192 ADVERTISED_10baseT_Full |
193 ADVERTISED_100baseT_Half |
194 ADVERTISED_100baseT_Full |
195 ADVERTISED_1000baseT_Full |
196 ADVERTISED_Autoneg | ADVERTISED_TP;
197 break;
198 case MEDIA_TYPE_1000M_FULL:
199 ecmd->advertising =
200 ADVERTISED_1000baseT_Full |
201 ADVERTISED_Autoneg | ADVERTISED_TP;
202 break;
203 default:
204 ecmd->advertising = 0;
205 break;
206 }
207 if (atl1_phy_setup_autoneg_adv(hw)) {
208 ret_val = -EINVAL;
209 printk(KERN_WARNING
210 "%s: invalid ethtool speed/duplex setting\n",
211 atl1_driver_name);
212 goto exit_sset;
213 }
214 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
215 hw->media_type == MEDIA_TYPE_1000M_FULL)
216 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
217 else {
218 switch (hw->media_type) {
219 case MEDIA_TYPE_100M_FULL:
220 phy_data =
221 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
222 MII_CR_RESET;
223 break;
224 case MEDIA_TYPE_100M_HALF:
225 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
226 break;
227 case MEDIA_TYPE_10M_FULL:
228 phy_data =
229 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
230 break;
231 default: /* MEDIA_TYPE_10M_HALF: */
232 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
233 break;
234 }
235 }
236 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
237exit_sset:
238 if (ret_val)
239 hw->media_type = old_media_type;
240
241 if (netif_running(adapter->netdev)) {
242 printk(KERN_DEBUG "%s: ethtool starting adapter\n",
243 atl1_driver_name);
244 atl1_up(adapter);
245 } else if (!ret_val) {
246 printk(KERN_DEBUG "%s: ethtool resetting adapter\n",
247 atl1_driver_name);
248 atl1_reset(adapter);
249 }
250 return ret_val;
251}
252
253static void atl1_get_drvinfo(struct net_device *netdev,
254 struct ethtool_drvinfo *drvinfo)
255{
256 struct atl1_adapter *adapter = netdev_priv(netdev);
257
258 strncpy(drvinfo->driver, atl1_driver_name, sizeof(drvinfo->driver));
259 strncpy(drvinfo->version, atl1_driver_version,
260 sizeof(drvinfo->version));
261 strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
262 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
263 sizeof(drvinfo->bus_info));
264 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
265}
266
267static void atl1_get_wol(struct net_device *netdev,
268 struct ethtool_wolinfo *wol)
269{
270 struct atl1_adapter *adapter = netdev_priv(netdev);
271
272 wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
273 wol->wolopts = 0;
274 if (adapter->wol & ATL1_WUFC_EX)
275 wol->wolopts |= WAKE_UCAST;
276 if (adapter->wol & ATL1_WUFC_MC)
277 wol->wolopts |= WAKE_MCAST;
278 if (adapter->wol & ATL1_WUFC_BC)
279 wol->wolopts |= WAKE_BCAST;
280 if (adapter->wol & ATL1_WUFC_MAG)
281 wol->wolopts |= WAKE_MAGIC;
282 return;
283}
284
285static int atl1_set_wol(struct net_device *netdev,
286 struct ethtool_wolinfo *wol)
287{
288 struct atl1_adapter *adapter = netdev_priv(netdev);
289
290 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
291 return -EOPNOTSUPP;
292 adapter->wol = 0;
293 if (wol->wolopts & WAKE_UCAST)
294 adapter->wol |= ATL1_WUFC_EX;
295 if (wol->wolopts & WAKE_MCAST)
296 adapter->wol |= ATL1_WUFC_MC;
297 if (wol->wolopts & WAKE_BCAST)
298 adapter->wol |= ATL1_WUFC_BC;
299 if (wol->wolopts & WAKE_MAGIC)
300 adapter->wol |= ATL1_WUFC_MAG;
301 return 0;
302}
303
304static void atl1_get_ringparam(struct net_device *netdev,
305 struct ethtool_ringparam *ring)
306{
307 struct atl1_adapter *adapter = netdev_priv(netdev);
308 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
309 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
310
311 ring->rx_max_pending = ATL1_MAX_RFD;
312 ring->tx_max_pending = ATL1_MAX_TPD;
313 ring->rx_mini_max_pending = 0;
314 ring->rx_jumbo_max_pending = 0;
315 ring->rx_pending = rxdr->count;
316 ring->tx_pending = txdr->count;
317 ring->rx_mini_pending = 0;
318 ring->rx_jumbo_pending = 0;
319}
320
321static int atl1_set_ringparam(struct net_device *netdev,
322 struct ethtool_ringparam *ring)
323{
324 struct atl1_adapter *adapter = netdev_priv(netdev);
325 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
326 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
327 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
328
329 struct atl1_tpd_ring tpd_old, tpd_new;
330 struct atl1_rfd_ring rfd_old, rfd_new;
331 struct atl1_rrd_ring rrd_old, rrd_new;
332 struct atl1_ring_header rhdr_old, rhdr_new;
333 int err;
334
335 tpd_old = adapter->tpd_ring;
336 rfd_old = adapter->rfd_ring;
337 rrd_old = adapter->rrd_ring;
338 rhdr_old = adapter->ring_header;
339
340 if (netif_running(adapter->netdev))
341 atl1_down(adapter);
342
343 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
344 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
345 rfdr->count;
346 rfdr->count = (rfdr->count + 3) & ~3;
347 rrdr->count = rfdr->count;
348
349 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
350 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
351 tpdr->count;
352 tpdr->count = (tpdr->count + 3) & ~3;
353
354 if (netif_running(adapter->netdev)) {
355 /* try to get new resources before deleting old */
356 err = atl1_setup_ring_resources(adapter);
357 if (err)
358 goto err_setup_ring;
359
360 /*
361 * save the new, restore the old in order to free it,
362 * then restore the new back again
363 */
364
365 rfd_new = adapter->rfd_ring;
366 rrd_new = adapter->rrd_ring;
367 tpd_new = adapter->tpd_ring;
368 rhdr_new = adapter->ring_header;
369 adapter->rfd_ring = rfd_old;
370 adapter->rrd_ring = rrd_old;
371 adapter->tpd_ring = tpd_old;
372 adapter->ring_header = rhdr_old;
373 atl1_free_ring_resources(adapter);
374 adapter->rfd_ring = rfd_new;
375 adapter->rrd_ring = rrd_new;
376 adapter->tpd_ring = tpd_new;
377 adapter->ring_header = rhdr_new;
378
379 err = atl1_up(adapter);
380 if (err)
381 return err;
382 }
383 return 0;
384
385err_setup_ring:
386 adapter->rfd_ring = rfd_old;
387 adapter->rrd_ring = rrd_old;
388 adapter->tpd_ring = tpd_old;
389 adapter->ring_header = rhdr_old;
390 atl1_up(adapter);
391 return err;
392}
393
394static void atl1_get_pauseparam(struct net_device *netdev,
395 struct ethtool_pauseparam *epause)
396{
397 struct atl1_adapter *adapter = netdev_priv(netdev);
398 struct atl1_hw *hw = &adapter->hw;
399
400 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
401 hw->media_type == MEDIA_TYPE_1000M_FULL) {
402 epause->autoneg = AUTONEG_ENABLE;
403 } else {
404 epause->autoneg = AUTONEG_DISABLE;
405 }
406 epause->rx_pause = 1;
407 epause->tx_pause = 1;
408}
409
410static int atl1_set_pauseparam(struct net_device *netdev,
411 struct ethtool_pauseparam *epause)
412{
413 struct atl1_adapter *adapter = netdev_priv(netdev);
414 struct atl1_hw *hw = &adapter->hw;
415
416 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
417 hw->media_type == MEDIA_TYPE_1000M_FULL) {
418 epause->autoneg = AUTONEG_ENABLE;
419 } else {
420 epause->autoneg = AUTONEG_DISABLE;
421 }
422
423 epause->rx_pause = 1;
424 epause->tx_pause = 1;
425
426 return 0;
427}
428
429static u32 atl1_get_rx_csum(struct net_device *netdev)
430{
431 return 1;
432}
433
434static void atl1_get_strings(struct net_device *netdev, u32 stringset,
435 u8 *data)
436{
437 u8 *p = data;
438 int i;
439
440 switch (stringset) {
441 case ETH_SS_STATS:
442 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
443 memcpy(p, atl1_gstrings_stats[i].stat_string,
444 ETH_GSTRING_LEN);
445 p += ETH_GSTRING_LEN;
446 }
447 break;
448 }
449}
450
451static int atl1_nway_reset(struct net_device *netdev)
452{
453 struct atl1_adapter *adapter = netdev_priv(netdev);
454 struct atl1_hw *hw = &adapter->hw;
455
456 if (netif_running(netdev)) {
457 u16 phy_data;
458 atl1_down(adapter);
459
460 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
461 hw->media_type == MEDIA_TYPE_1000M_FULL) {
462 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
463 } else {
464 switch (hw->media_type) {
465 case MEDIA_TYPE_100M_FULL:
466 phy_data = MII_CR_FULL_DUPLEX |
467 MII_CR_SPEED_100 | MII_CR_RESET;
468 break;
469 case MEDIA_TYPE_100M_HALF:
470 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
471 break;
472 case MEDIA_TYPE_10M_FULL:
473 phy_data = MII_CR_FULL_DUPLEX |
474 MII_CR_SPEED_10 | MII_CR_RESET;
475 break;
476 default: /* MEDIA_TYPE_10M_HALF */
477 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
478 }
479 }
480 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
481 atl1_up(adapter);
482 }
483 return 0;
484}
485
486const struct ethtool_ops atl1_ethtool_ops = {
487 .get_settings = atl1_get_settings,
488 .set_settings = atl1_set_settings,
489 .get_drvinfo = atl1_get_drvinfo,
490 .get_wol = atl1_get_wol,
491 .set_wol = atl1_set_wol,
492 .get_ringparam = atl1_get_ringparam,
493 .set_ringparam = atl1_set_ringparam,
494 .get_pauseparam = atl1_get_pauseparam,
495 .set_pauseparam = atl1_set_pauseparam,
496 .get_rx_csum = atl1_get_rx_csum,
497 .get_tx_csum = ethtool_op_get_tx_csum,
498 .set_tx_csum = ethtool_op_set_tx_hw_csum,
499 .get_link = ethtool_op_get_link,
500 .get_sg = ethtool_op_get_sg,
501 .set_sg = ethtool_op_set_sg,
502 .get_strings = atl1_get_strings,
503 .nway_reset = atl1_nway_reset,
504 .get_ethtool_stats = atl1_get_ethtool_stats,
505 .get_stats_count = atl1_get_stats_count,
506 .get_tso = ethtool_op_get_tso,
507 .set_tso = ethtool_op_set_tso,
508};
diff --git a/drivers/net/atl1/atl1_hw.c b/drivers/net/atl1/atl1_hw.c
new file mode 100644
index 000000000000..08b2d785469d
--- /dev/null
+++ b/drivers/net/atl1/atl1_hw.c
@@ -0,0 +1,718 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#include <linux/types.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/if_vlan.h>
28#include <linux/etherdevice.h>
29#include <linux/crc32.h>
30#include <asm/byteorder.h>
31
32#include "atl1.h"
33
34/*
35 * Reset the transmit and receive units; mask and clear all interrupts.
36 * hw - Struct containing variables accessed by shared code
37 * return : ATL1_SUCCESS or idle status (if error)
38 */
39s32 atl1_reset_hw(struct atl1_hw *hw)
40{
41 u32 icr;
42 int i;
43
44 /*
45 * Clear Interrupt mask to stop board from generating
46 * interrupts & Clear any pending interrupt events
47 */
48 /*
49 * iowrite32(0, hw->hw_addr + REG_IMR);
50 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
51 */
52
53 /*
54 * Issue Soft Reset to the MAC. This will reset the chip's
55 * transmit, receive, DMA. It will not effect
56 * the current PCI configuration. The global reset bit is self-
57 * clearing, and should clear within a microsecond.
58 */
59 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
60 ioread32(hw->hw_addr + REG_MASTER_CTRL);
61
62 iowrite16(1, hw->hw_addr + REG_GPHY_ENABLE);
63 ioread16(hw->hw_addr + REG_GPHY_ENABLE);
64
65 msleep(1); /* delay about 1ms */
66
67 /* Wait at least 10ms for All module to be Idle */
68 for (i = 0; i < 10; i++) {
69 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
70 if (!icr)
71 break;
72 msleep(1); /* delay 1 ms */
73 cpu_relax(); /* FIXME: is this still the right way to do this? */
74 }
75
76 if (icr) {
77 printk (KERN_DEBUG "icr = %x\n", icr);
78 return icr;
79 }
80
81 return ATL1_SUCCESS;
82}
83
84/* function about EEPROM
85 *
86 * check_eeprom_exist
87 * return 0 if eeprom exist
88 */
89static int atl1_check_eeprom_exist(struct atl1_hw *hw)
90{
91 u32 value;
92 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
93 if (value & SPI_FLASH_CTRL_EN_VPD) {
94 value &= ~SPI_FLASH_CTRL_EN_VPD;
95 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
96 }
97
98 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
99 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
100}
101
102static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
103{
104 int i;
105 u32 control;
106
107 if (offset & 3)
108 return false; /* address do not align */
109
110 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
111 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
112 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
113 ioread32(hw->hw_addr + REG_VPD_CAP);
114
115 for (i = 0; i < 10; i++) {
116 msleep(2);
117 control = ioread32(hw->hw_addr + REG_VPD_CAP);
118 if (control & VPD_CAP_VPD_FLAG)
119 break;
120 }
121 if (control & VPD_CAP_VPD_FLAG) {
122 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
123 return true;
124 }
125 return false; /* timeout */
126}
127
128/*
129 * Reads the value from a PHY register
130 * hw - Struct containing variables accessed by shared code
131 * reg_addr - address of the PHY register to read
132 */
133s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
134{
135 u32 val;
136 int i;
137
138 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
139 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
140 MDIO_CLK_SEL_SHIFT;
141 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
142 ioread32(hw->hw_addr + REG_MDIO_CTRL);
143
144 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
145 udelay(2);
146 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
147 if (!(val & (MDIO_START | MDIO_BUSY)))
148 break;
149 }
150 if (!(val & (MDIO_START | MDIO_BUSY))) {
151 *phy_data = (u16) val;
152 return ATL1_SUCCESS;
153 }
154 return ATL1_ERR_PHY;
155}
156
157#define CUSTOM_SPI_CS_SETUP 2
158#define CUSTOM_SPI_CLK_HI 2
159#define CUSTOM_SPI_CLK_LO 2
160#define CUSTOM_SPI_CS_HOLD 2
161#define CUSTOM_SPI_CS_HI 3
162
163static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
164{
165 int i;
166 u32 value;
167
168 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
169 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
170
171 value = SPI_FLASH_CTRL_WAIT_READY |
172 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
173 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
174 SPI_FLASH_CTRL_CLK_HI_MASK) <<
175 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
176 SPI_FLASH_CTRL_CLK_LO_MASK) <<
177 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
178 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
179 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
180 SPI_FLASH_CTRL_CS_HI_MASK) <<
181 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
182 SPI_FLASH_CTRL_INS_SHIFT;
183
184 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
185
186 value |= SPI_FLASH_CTRL_START;
187 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
188 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
189
190 for (i = 0; i < 10; i++) {
191 msleep(1); /* 1ms */
192 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
193 if (!(value & SPI_FLASH_CTRL_START))
194 break;
195 }
196
197 if (value & SPI_FLASH_CTRL_START)
198 return false;
199
200 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
201
202 return true;
203}
204
205/*
206 * get_permanent_address
207 * return 0 if get valid mac address,
208 */
209static int atl1_get_permanent_address(struct atl1_hw *hw)
210{
211 u32 addr[2];
212 u32 i, control;
213 u16 reg;
214 u8 eth_addr[ETH_ALEN];
215 bool key_valid;
216
217 if (is_valid_ether_addr(hw->perm_mac_addr))
218 return 0;
219
220 /* init */
221 addr[0] = addr[1] = 0;
222
223 if (!atl1_check_eeprom_exist(hw)) { /* eeprom exist */
224 reg = 0;
225 key_valid = false;
226 /* Read out all EEPROM content */
227 i = 0;
228 while (1) {
229 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
230 if (key_valid) {
231 if (reg == REG_MAC_STA_ADDR)
232 addr[0] = control;
233 else if (reg == (REG_MAC_STA_ADDR + 4))
234 addr[1] = control;
235 key_valid = false;
236 } else if ((control & 0xff) == 0x5A) {
237 key_valid = true;
238 reg = (u16) (control >> 16);
239 } else
240 break; /* assume data end while encount an invalid KEYWORD */
241 } else
242 break; /* read error */
243 i += 4;
244 }
245
246/*
247 * The following 2 lines are the Attansic originals. Saving for posterity.
248 * *(u32 *) & eth_addr[2] = LONGSWAP(addr[0]);
249 * *(u16 *) & eth_addr[0] = SHORTSWAP(*(u16 *) & addr[1]);
250 */
251 *(u32 *) & eth_addr[2] = swab32(addr[0]);
252 *(u16 *) & eth_addr[0] = swab16(*(u16 *) & addr[1]);
253
254 if (is_valid_ether_addr(eth_addr)) {
255 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
256 return 0;
257 }
258 return 1;
259 }
260
261 /* see if SPI FLAGS exist ? */
262 addr[0] = addr[1] = 0;
263 reg = 0;
264 key_valid = false;
265 i = 0;
266 while (1) {
267 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
268 if (key_valid) {
269 if (reg == REG_MAC_STA_ADDR)
270 addr[0] = control;
271 else if (reg == (REG_MAC_STA_ADDR + 4))
272 addr[1] = control;
273 key_valid = false;
274 } else if ((control & 0xff) == 0x5A) {
275 key_valid = true;
276 reg = (u16) (control >> 16);
277 } else
278 break; /* data end */
279 } else
280 break; /* read error */
281 i += 4;
282 }
283
284/*
285 * The following 2 lines are the Attansic originals. Saving for posterity.
286 * *(u32 *) & eth_addr[2] = LONGSWAP(addr[0]);
287 * *(u16 *) & eth_addr[0] = SHORTSWAP(*(u16 *) & addr[1]);
288 */
289 *(u32 *) & eth_addr[2] = swab32(addr[0]);
290 *(u16 *) & eth_addr[0] = swab16(*(u16 *) & addr[1]);
291 if (is_valid_ether_addr(eth_addr)) {
292 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
293 return 0;
294 }
295 return 1;
296}
297
298/*
299 * Reads the adapter's MAC address from the EEPROM
300 * hw - Struct containing variables accessed by shared code
301 */
302s32 atl1_read_mac_addr(struct atl1_hw *hw)
303{
304 u16 i;
305
306 if (atl1_get_permanent_address(hw))
307 random_ether_addr(hw->perm_mac_addr);
308
309 for (i = 0; i < ETH_ALEN; i++)
310 hw->mac_addr[i] = hw->perm_mac_addr[i];
311 return ATL1_SUCCESS;
312}
313
314/*
315 * Hashes an address to determine its location in the multicast table
316 * hw - Struct containing variables accessed by shared code
317 * mc_addr - the multicast address to hash
318 *
319 * atl1_hash_mc_addr
320 * purpose
321 * set hash value for a multicast address
322 * hash calcu processing :
323 * 1. calcu 32bit CRC for multicast address
324 * 2. reverse crc with MSB to LSB
325 */
326u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
327{
328 u32 crc32, value = 0;
329 int i;
330
331 crc32 = ether_crc_le(6, mc_addr);
332 crc32 = ~crc32;
333 for (i = 0; i < 32; i++)
334 value |= (((crc32 >> i) & 1) << (31 - i));
335
336 return value;
337}
338
339/*
340 * Sets the bit in the multicast table corresponding to the hash value.
341 * hw - Struct containing variables accessed by shared code
342 * hash_value - Multicast address hash value
343 */
344void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
345{
346 u32 hash_bit, hash_reg;
347 u32 mta;
348
349 /*
350 * The HASH Table is a register array of 2 32-bit registers.
351 * It is treated like an array of 64 bits. We want to set
352 * bit BitArray[hash_value]. So we figure out what register
353 * the bit is in, read it, OR in the new bit, then write
354 * back the new value. The register is determined by the
355 * upper 7 bits of the hash value and the bit within that
356 * register are determined by the lower 5 bits of the value.
357 */
358 hash_reg = (hash_value >> 31) & 0x1;
359 hash_bit = (hash_value >> 26) & 0x1F;
360 mta = ioread32((hw + REG_RX_HASH_TABLE) + (hash_reg << 2));
361 mta |= (1 << hash_bit);
362 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
363}
364
365/*
366 * Writes a value to a PHY register
367 * hw - Struct containing variables accessed by shared code
368 * reg_addr - address of the PHY register to write
369 * data - data to write to the PHY
370 */
371s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
372{
373 int i;
374 u32 val;
375
376 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
377 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
378 MDIO_SUP_PREAMBLE |
379 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
380 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
381 ioread32(hw->hw_addr + REG_MDIO_CTRL);
382
383 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
384 udelay(2);
385 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
386 if (!(val & (MDIO_START | MDIO_BUSY)))
387 break;
388 }
389
390 if (!(val & (MDIO_START | MDIO_BUSY)))
391 return ATL1_SUCCESS;
392
393 return ATL1_ERR_PHY;
394}
395
396/*
397 * Make L001's PHY out of Power Saving State (bug)
398 * hw - Struct containing variables accessed by shared code
399 * when power on, L001's PHY always on Power saving State
400 * (Gigabit Link forbidden)
401 */
402static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
403{
404 s32 ret;
405 ret = atl1_write_phy_reg(hw, 29, 0x0029);
406 if (ret)
407 return ret;
408 return atl1_write_phy_reg(hw, 30, 0);
409}
410
411/*
412 *TODO: do something or get rid of this
413 */
414s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
415{
416/* s32 ret_val;
417 * u16 phy_data;
418 */
419
420/*
421 ret_val = atl1_write_phy_reg(hw, ...);
422 ret_val = atl1_write_phy_reg(hw, ...);
423 ....
424*/
425 return ATL1_SUCCESS;
426}
427
428/*
429 * Resets the PHY and make all config validate
430 * hw - Struct containing variables accessed by shared code
431 *
432 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
433 */
434static s32 atl1_phy_reset(struct atl1_hw *hw)
435{
436 s32 ret_val;
437 u16 phy_data;
438
439 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
440 hw->media_type == MEDIA_TYPE_1000M_FULL)
441 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
442 else {
443 switch (hw->media_type) {
444 case MEDIA_TYPE_100M_FULL:
445 phy_data =
446 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
447 MII_CR_RESET;
448 break;
449 case MEDIA_TYPE_100M_HALF:
450 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
451 break;
452 case MEDIA_TYPE_10M_FULL:
453 phy_data =
454 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
455 break;
456 default: /* MEDIA_TYPE_10M_HALF: */
457 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
458 break;
459 }
460 }
461
462 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
463 if (ret_val) {
464 u32 val;
465 int i;
466 /* pcie serdes link may be down! */
467 printk(KERN_DEBUG "%s: autoneg caused pcie phy link down\n",
468 atl1_driver_name);
469
470 for (i = 0; i < 25; i++) {
471 msleep(1);
472 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
473 if (!(val & (MDIO_START | MDIO_BUSY)))
474 break;
475 }
476
477 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
478 printk(KERN_WARNING
479 "%s: pcie link down at least for 25ms\n",
480 atl1_driver_name);
481 return ret_val;
482 }
483 }
484 return ATL1_SUCCESS;
485}
486
487/*
488 * Configures PHY autoneg and flow control advertisement settings
489 * hw - Struct containing variables accessed by shared code
490 */
491s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
492{
493 s32 ret_val;
494 s16 mii_autoneg_adv_reg;
495 s16 mii_1000t_ctrl_reg;
496
497 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
498 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
499
500 /* Read the MII 1000Base-T Control Register (Address 9). */
501 mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
502
503 /*
504 * First we clear all the 10/100 mb speed bits in the Auto-Neg
505 * Advertisement Register (Address 4) and the 1000 mb speed bits in
506 * the 1000Base-T Control Register (Address 9).
507 */
508 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
509 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
510
511 /*
512 * Need to parse media_type and set up
513 * the appropriate PHY registers.
514 */
515 switch (hw->media_type) {
516 case MEDIA_TYPE_AUTO_SENSOR:
517 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
518 MII_AR_10T_FD_CAPS |
519 MII_AR_100TX_HD_CAPS |
520 MII_AR_100TX_FD_CAPS);
521 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
522 break;
523
524 case MEDIA_TYPE_1000M_FULL:
525 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
526 break;
527
528 case MEDIA_TYPE_100M_FULL:
529 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
530 break;
531
532 case MEDIA_TYPE_100M_HALF:
533 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
534 break;
535
536 case MEDIA_TYPE_10M_FULL:
537 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
538 break;
539
540 default:
541 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
542 break;
543 }
544
545 /* flow control fixed to enable all */
546 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
547
548 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
549 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
550
551 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
552 if (ret_val)
553 return ret_val;
554
555 ret_val = atl1_write_phy_reg(hw, MII_AT001_CR, mii_1000t_ctrl_reg);
556 if (ret_val)
557 return ret_val;
558
559 return ATL1_SUCCESS;
560}
561
562/*
563 * Configures link settings.
564 * hw - Struct containing variables accessed by shared code
565 * Assumes the hardware has previously been reset and the
566 * transmitter and receiver are not enabled.
567 */
568static s32 atl1_setup_link(struct atl1_hw *hw)
569{
570 s32 ret_val;
571
572 /*
573 * Options:
574 * PHY will advertise value(s) parsed from
575 * autoneg_advertised and fc
576 * no matter what autoneg is , We will not wait link result.
577 */
578 ret_val = atl1_phy_setup_autoneg_adv(hw);
579 if (ret_val) {
580 printk(KERN_DEBUG "%s: error setting up autonegotiation\n",
581 atl1_driver_name);
582 return ret_val;
583 }
584 /* SW.Reset , En-Auto-Neg if needed */
585 ret_val = atl1_phy_reset(hw);
586 if (ret_val) {
587 printk(KERN_DEBUG "%s: error resetting the phy\n",
588 atl1_driver_name);
589 return ret_val;
590 }
591 hw->phy_configured = true;
592 return ret_val;
593}
594
595static struct atl1_spi_flash_dev flash_table[] = {
596/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
597 {"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
598 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
599 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
600};
601
602static void atl1_init_flash_opcode(struct atl1_hw *hw)
603{
604 if (hw->flash_vendor >= sizeof(flash_table) / sizeof(flash_table[0]))
605 hw->flash_vendor = 0; /* ATMEL */
606
607 /* Init OP table */
608 iowrite8(flash_table[hw->flash_vendor].cmd_program,
609 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
610 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
611 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
612 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
613 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
614 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
615 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
616 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
617 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
618 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
619 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
620 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
621 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
622 iowrite8(flash_table[hw->flash_vendor].cmd_read,
623 hw->hw_addr + REG_SPI_FLASH_OP_READ);
624}
625
626/*
627 * Performs basic configuration of the adapter.
628 * hw - Struct containing variables accessed by shared code
629 * Assumes that the controller has previously been reset and is in a
630 * post-reset uninitialized state. Initializes multicast table,
631 * and Calls routines to setup link
632 * Leaves the transmit and receive units disabled and uninitialized.
633 */
634s32 atl1_init_hw(struct atl1_hw *hw)
635{
636 u32 ret_val = 0;
637
638 /* Zero out the Multicast HASH table */
639 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
640 /* clear the old settings from the multicast hash table */
641 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
642
643 atl1_init_flash_opcode(hw);
644
645 if (!hw->phy_configured) {
646 /* enable GPHY LinkChange Interrrupt */
647 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
648 if (ret_val)
649 return ret_val;
650 /* make PHY out of power-saving state */
651 ret_val = atl1_phy_leave_power_saving(hw);
652 if (ret_val)
653 return ret_val;
654 /* Call a subroutine to configure the link */
655 ret_val = atl1_setup_link(hw);
656 }
657 return ret_val;
658}
659
660/*
661 * Detects the current speed and duplex settings of the hardware.
662 * hw - Struct containing variables accessed by shared code
663 * speed - Speed of the connection
664 * duplex - Duplex setting of the connection
665 */
666s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
667{
668 s32 ret_val;
669 u16 phy_data;
670
671 /* ; --- Read PHY Specific Status Register (17) */
672 ret_val = atl1_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
673 if (ret_val)
674 return ret_val;
675
676 if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
677 return ATL1_ERR_PHY_RES;
678
679 switch (phy_data & MII_AT001_PSSR_SPEED) {
680 case MII_AT001_PSSR_1000MBS:
681 *speed = SPEED_1000;
682 break;
683 case MII_AT001_PSSR_100MBS:
684 *speed = SPEED_100;
685 break;
686 case MII_AT001_PSSR_10MBS:
687 *speed = SPEED_10;
688 break;
689 default:
690 printk(KERN_DEBUG "%s: error getting speed\n",
691 atl1_driver_name);
692 return ATL1_ERR_PHY_SPEED;
693 break;
694 }
695 if (phy_data & MII_AT001_PSSR_DPLX)
696 *duplex = FULL_DUPLEX;
697 else
698 *duplex = HALF_DUPLEX;
699
700 return ATL1_SUCCESS;
701}
702
703void atl1_set_mac_addr(struct atl1_hw *hw)
704{
705 u32 value;
706 /*
707 * 00-0B-6A-F6-00-DC
708 * 0: 6AF600DC 1: 000B
709 * low dword
710 */
711 value = (((u32) hw->mac_addr[2]) << 24) |
712 (((u32) hw->mac_addr[3]) << 16) |
713 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
714 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
715 /* high dword */
716 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
717 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
718}
diff --git a/drivers/net/atl1/atl1_hw.h b/drivers/net/atl1/atl1_hw.h
new file mode 100644
index 000000000000..100c09c66e64
--- /dev/null
+++ b/drivers/net/atl1/atl1_hw.h
@@ -0,0 +1,951 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * There are a lot of defines in here that are unused and/or have cryptic
24 * names. Please leave them alone, as they're the closest thing we have
25 * to a spec from Attansic at present. *ahem* -- CHS
26 */
27
28#ifndef _ATL1_HW_H_
29#define _ATL1_HW_H_
30
31#include <linux/types.h>
32#include <linux/mii.h>
33
34struct atl1_adapter;
35struct atl1_hw;
36
37/* function prototypes needed by multiple files */
38s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw);
39s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data);
40s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
41s32 atl1_read_mac_addr(struct atl1_hw *hw);
42s32 atl1_init_hw(struct atl1_hw *hw);
43s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
44s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex);
45u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
46void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
47s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
48void atl1_set_mac_addr(struct atl1_hw *hw);
49s32 atl1_phy_enter_power_saving(struct atl1_hw *hw);
50s32 atl1_reset_hw(struct atl1_hw *hw);
51void atl1_check_options(struct atl1_adapter *adapter);
52
53/* register definitions */
54#define REG_PCIE_CAP_LIST 0x58
55
56#define REG_VPD_CAP 0x6C
57#define VPD_CAP_ID_MASK 0xff
58#define VPD_CAP_ID_SHIFT 0
59#define VPD_CAP_NEXT_PTR_MASK 0xFF
60#define VPD_CAP_NEXT_PTR_SHIFT 8
61#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
62#define VPD_CAP_VPD_ADDR_SHIFT 16
63#define VPD_CAP_VPD_FLAG 0x80000000
64
65#define REG_VPD_DATA 0x70
66
67#define REG_SPI_FLASH_CTRL 0x200
68#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
69#define SPI_FLASH_CTRL_STS_WEN 0x2
70#define SPI_FLASH_CTRL_STS_WPEN 0x80
71#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
72#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
73#define SPI_FLASH_CTRL_INS_MASK 0x7
74#define SPI_FLASH_CTRL_INS_SHIFT 8
75#define SPI_FLASH_CTRL_START 0x800
76#define SPI_FLASH_CTRL_EN_VPD 0x2000
77#define SPI_FLASH_CTRL_LDSTART 0x8000
78#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
79#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
80#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
81#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
82#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
83#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
84#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
85#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
86#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
87#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
88#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
89#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
90#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
91
92#define REG_SPI_ADDR 0x204
93
94#define REG_SPI_DATA 0x208
95
96#define REG_SPI_FLASH_CONFIG 0x20C
97#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
98#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
99#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
100#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
101#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
102
103#define REG_SPI_FLASH_OP_PROGRAM 0x210
104#define REG_SPI_FLASH_OP_SC_ERASE 0x211
105#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
106#define REG_SPI_FLASH_OP_RDID 0x213
107#define REG_SPI_FLASH_OP_WREN 0x214
108#define REG_SPI_FLASH_OP_RDSR 0x215
109#define REG_SPI_FLASH_OP_WRSR 0x216
110#define REG_SPI_FLASH_OP_READ 0x217
111
112#define REG_TWSI_CTRL 0x218
113#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
114#define TWSI_CTRL_LD_OFFSET_SHIFT 0
115#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
116#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
117#define TWSI_CTRL_SW_LDSTART 0x800
118#define TWSI_CTRL_HW_LDSTART 0x1000
119#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
120#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
121#define TWSI_CTRL_LD_EXIST 0x400000
122#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
123#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
124#define TWSI_CTRL_FREQ_SEL_100K 0
125#define TWSI_CTRL_FREQ_SEL_200K 1
126#define TWSI_CTRL_FREQ_SEL_300K 2
127#define TWSI_CTRL_FREQ_SEL_400K 3
128#define TWSI_CTRL_SMB_SLV_ADDR
129#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
130#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
131
132#define REG_PCIE_DEV_MISC_CTRL 0x21C
133#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
134#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
135#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
136#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
137#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
138
139/* Selene Master Control Register */
140#define REG_MASTER_CTRL 0x1400
141#define MASTER_CTRL_SOFT_RST 0x1
142#define MASTER_CTRL_MTIMER_EN 0x2
143#define MASTER_CTRL_ITIMER_EN 0x4
144#define MASTER_CTRL_MANUAL_INT 0x8
145#define MASTER_CTRL_REV_NUM_SHIFT 16
146#define MASTER_CTRL_REV_NUM_MASK 0xff
147#define MASTER_CTRL_DEV_ID_SHIFT 24
148#define MASTER_CTRL_DEV_ID_MASK 0xff
149
150/* Timer Initial Value Register */
151#define REG_MANUAL_TIMER_INIT 0x1404
152
153/* IRQ ModeratorTimer Initial Value Register */
154#define REG_IRQ_MODU_TIMER_INIT 0x1408
155
156#define REG_GPHY_ENABLE 0x140C
157
158/* IRQ Anti-Lost Timer Initial Value Register */
159#define REG_CMBDISDMA_TIMER 0x140E
160
161/* Block IDLE Status Register */
162#define REG_IDLE_STATUS 0x1410
163#define IDLE_STATUS_RXMAC 1
164#define IDLE_STATUS_TXMAC 2
165#define IDLE_STATUS_RXQ 4
166#define IDLE_STATUS_TXQ 8
167#define IDLE_STATUS_DMAR 0x10
168#define IDLE_STATUS_DMAW 0x20
169#define IDLE_STATUS_SMB 0x40
170#define IDLE_STATUS_CMB 0x80
171
172/* MDIO Control Register */
173#define REG_MDIO_CTRL 0x1414
174#define MDIO_DATA_MASK 0xffff
175#define MDIO_DATA_SHIFT 0
176#define MDIO_REG_ADDR_MASK 0x1f
177#define MDIO_REG_ADDR_SHIFT 16
178#define MDIO_RW 0x200000
179#define MDIO_SUP_PREAMBLE 0x400000
180#define MDIO_START 0x800000
181#define MDIO_CLK_SEL_SHIFT 24
182#define MDIO_CLK_25_4 0
183#define MDIO_CLK_25_6 2
184#define MDIO_CLK_25_8 3
185#define MDIO_CLK_25_10 4
186#define MDIO_CLK_25_14 5
187#define MDIO_CLK_25_20 6
188#define MDIO_CLK_25_28 7
189#define MDIO_BUSY 0x8000000
190#define MDIO_WAIT_TIMES 30
191
192/* MII PHY Status Register */
193#define REG_PHY_STATUS 0x1418
194
195/* BIST Control and Status Register0 (for the Packet Memory) */
196#define REG_BIST0_CTRL 0x141c
197#define BIST0_NOW 0x1
198#define BIST0_SRAM_FAIL 0x2
199#define BIST0_FUSE_FLAG 0x4
200#define REG_BIST1_CTRL 0x1420
201#define BIST1_NOW 0x1
202#define BIST1_SRAM_FAIL 0x2
203#define BIST1_FUSE_FLAG 0x4
204
205/* MAC Control Register */
206#define REG_MAC_CTRL 0x1480
207#define MAC_CTRL_TX_EN 1
208#define MAC_CTRL_RX_EN 2
209#define MAC_CTRL_TX_FLOW 4
210#define MAC_CTRL_RX_FLOW 8
211#define MAC_CTRL_LOOPBACK 0x10
212#define MAC_CTRL_DUPLX 0x20
213#define MAC_CTRL_ADD_CRC 0x40
214#define MAC_CTRL_PAD 0x80
215#define MAC_CTRL_LENCHK 0x100
216#define MAC_CTRL_HUGE_EN 0x200
217#define MAC_CTRL_PRMLEN_SHIFT 10
218#define MAC_CTRL_PRMLEN_MASK 0xf
219#define MAC_CTRL_RMV_VLAN 0x4000
220#define MAC_CTRL_PROMIS_EN 0x8000
221#define MAC_CTRL_TX_PAUSE 0x10000
222#define MAC_CTRL_SCNT 0x20000
223#define MAC_CTRL_SRST_TX 0x40000
224#define MAC_CTRL_TX_SIMURST 0x80000
225#define MAC_CTRL_SPEED_SHIFT 20
226#define MAC_CTRL_SPEED_MASK 0x300000
227#define MAC_CTRL_SPEED_1000 2
228#define MAC_CTRL_SPEED_10_100 1
229#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
230#define MAC_CTRL_TX_HUGE 0x800000
231#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
232#define MAC_CTRL_MC_ALL_EN 0x2000000
233#define MAC_CTRL_BC_EN 0x4000000
234#define MAC_CTRL_DBG 0x8000000
235
236/* MAC IPG/IFG Control Register */
237#define REG_MAC_IPG_IFG 0x1484
238#define MAC_IPG_IFG_IPGT_SHIFT 0
239#define MAC_IPG_IFG_IPGT_MASK 0x7f
240#define MAC_IPG_IFG_MIFG_SHIFT 8
241#define MAC_IPG_IFG_MIFG_MASK 0xff
242#define MAC_IPG_IFG_IPGR1_SHIFT 16
243#define MAC_IPG_IFG_IPGR1_MASK 0x7f
244#define MAC_IPG_IFG_IPGR2_SHIFT 24
245#define MAC_IPG_IFG_IPGR2_MASK 0x7f
246
247/* MAC STATION ADDRESS */
248#define REG_MAC_STA_ADDR 0x1488
249
250/* Hash table for multicast address */
251#define REG_RX_HASH_TABLE 0x1490
252
253/* MAC Half-Duplex Control Register */
254#define REG_MAC_HALF_DUPLX_CTRL 0x1498
255#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0
256#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
257#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
258#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
259#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
260#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
261#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000
262#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
263#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
264#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
265#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
266#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf
267
268/* Maximum Frame Length Control Register */
269#define REG_MTU 0x149c
270
271/* Wake-On-Lan control register */
272#define REG_WOL_CTRL 0x14a0
273#define WOL_PATTERN_EN 0x00000001
274#define WOL_PATTERN_PME_EN 0x00000002
275#define WOL_MAGIC_EN 0x00000004
276#define WOL_MAGIC_PME_EN 0x00000008
277#define WOL_LINK_CHG_EN 0x00000010
278#define WOL_LINK_CHG_PME_EN 0x00000020
279#define WOL_PATTERN_ST 0x00000100
280#define WOL_MAGIC_ST 0x00000200
281#define WOL_LINKCHG_ST 0x00000400
282#define WOL_CLK_SWITCH_EN 0x00008000
283#define WOL_PT0_EN 0x00010000
284#define WOL_PT1_EN 0x00020000
285#define WOL_PT2_EN 0x00040000
286#define WOL_PT3_EN 0x00080000
287#define WOL_PT4_EN 0x00100000
288#define WOL_PT5_EN 0x00200000
289#define WOL_PT6_EN 0x00400000
290
291/* WOL Length ( 2 DWORD ) */
292#define REG_WOL_PATTERN_LEN 0x14a4
293#define WOL_PT_LEN_MASK 0x7f
294#define WOL_PT0_LEN_SHIFT 0
295#define WOL_PT1_LEN_SHIFT 8
296#define WOL_PT2_LEN_SHIFT 16
297#define WOL_PT3_LEN_SHIFT 24
298#define WOL_PT4_LEN_SHIFT 0
299#define WOL_PT5_LEN_SHIFT 8
300#define WOL_PT6_LEN_SHIFT 16
301
302/* Internal SRAM Partition Register */
303#define REG_SRAM_RFD_ADDR 0x1500
304#define REG_SRAM_RFD_LEN (REG_SRAM_RFD_ADDR+ 4)
305#define REG_SRAM_RRD_ADDR (REG_SRAM_RFD_ADDR+ 8)
306#define REG_SRAM_RRD_LEN (REG_SRAM_RFD_ADDR+12)
307#define REG_SRAM_TPD_ADDR (REG_SRAM_RFD_ADDR+16)
308#define REG_SRAM_TPD_LEN (REG_SRAM_RFD_ADDR+20)
309#define REG_SRAM_TRD_ADDR (REG_SRAM_RFD_ADDR+24)
310#define REG_SRAM_TRD_LEN (REG_SRAM_RFD_ADDR+28)
311#define REG_SRAM_RXF_ADDR (REG_SRAM_RFD_ADDR+32)
312#define REG_SRAM_RXF_LEN (REG_SRAM_RFD_ADDR+36)
313#define REG_SRAM_TXF_ADDR (REG_SRAM_RFD_ADDR+40)
314#define REG_SRAM_TXF_LEN (REG_SRAM_RFD_ADDR+44)
315#define REG_SRAM_TCPH_PATH_ADDR (REG_SRAM_RFD_ADDR+48)
316#define SRAM_TCPH_ADDR_MASK 0x0fff
317#define SRAM_TCPH_ADDR_SHIFT 0
318#define SRAM_PATH_ADDR_MASK 0x0fff
319#define SRAM_PATH_ADDR_SHIFT 16
320
321/* Load Ptr Register */
322#define REG_LOAD_PTR (REG_SRAM_RFD_ADDR+52)
323
324/* Descriptor Control register */
325#define REG_DESC_BASE_ADDR_HI 0x1540
326#define REG_DESC_RFD_ADDR_LO (REG_DESC_BASE_ADDR_HI+4)
327#define REG_DESC_RRD_ADDR_LO (REG_DESC_BASE_ADDR_HI+8)
328#define REG_DESC_TPD_ADDR_LO (REG_DESC_BASE_ADDR_HI+12)
329#define REG_DESC_CMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+16)
330#define REG_DESC_SMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+20)
331#define REG_DESC_RFD_RRD_RING_SIZE (REG_DESC_BASE_ADDR_HI+24)
332#define DESC_RFD_RING_SIZE_MASK 0x7ff
333#define DESC_RFD_RING_SIZE_SHIFT 0
334#define DESC_RRD_RING_SIZE_MASK 0x7ff
335#define DESC_RRD_RING_SIZE_SHIFT 16
336#define REG_DESC_TPD_RING_SIZE (REG_DESC_BASE_ADDR_HI+28)
337#define DESC_TPD_RING_SIZE_MASK 0x3ff
338#define DESC_TPD_RING_SIZE_SHIFT 0
339
340/* TXQ Control Register */
341#define REG_TXQ_CTRL 0x1580
342#define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
343#define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1f
344#define TXQ_CTRL_EN 0x20
345#define TXQ_CTRL_ENH_MODE 0x40
346#define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
347#define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3f
348#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
349#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
350
351/* Jumbo packet Threshold for task offload */
352#define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
353#define TX_JUMBO_TASK_TH_MASK 0x7ff
354#define TX_JUMBO_TASK_TH_SHIFT 0
355#define TX_TPD_MIN_IPG_MASK 0x1f
356#define TX_TPD_MIN_IPG_SHIFT 16
357
358/* RXQ Control Register */
359#define REG_RXQ_CTRL 0x15a0
360#define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
361#define RXQ_CTRL_RFD_BURST_NUM_MASK 0xff
362#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
363#define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xff
364#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
365#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1f
366#define RXQ_CTRL_CUT_THRU_EN 0x40000000
367#define RXQ_CTRL_EN 0x80000000
368
369/* Rx jumbo packet threshold and rrd retirement timer */
370#define REG_RXQ_JMBOSZ_RRDTIM (REG_RXQ_CTRL+ 4)
371#define RXQ_JMBOSZ_TH_MASK 0x7ff
372#define RXQ_JMBOSZ_TH_SHIFT 0
373#define RXQ_JMBO_LKAH_MASK 0xf
374#define RXQ_JMBO_LKAH_SHIFT 11
375#define RXQ_RRD_TIMER_MASK 0xffff
376#define RXQ_RRD_TIMER_SHIFT 16
377
378/* RFD flow control register */
379#define REG_RXQ_RXF_PAUSE_THRESH (REG_RXQ_CTRL+ 8)
380#define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
381#define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
382#define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
383#define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
384
385/* RRD flow control register */
386#define REG_RXQ_RRD_PAUSE_THRESH (REG_RXQ_CTRL+12)
387#define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
388#define RXQ_RRD_PAUSE_TH_HI_MASK 0xfff
389#define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
390#define RXQ_RRD_PAUSE_TH_LO_MASK 0xfff
391
392/* DMA Engine Control Register */
393#define REG_DMA_CTRL 0x15c0
394#define DMA_CTRL_DMAR_IN_ORDER 0x1
395#define DMA_CTRL_DMAR_ENH_ORDER 0x2
396#define DMA_CTRL_DMAR_OUT_ORDER 0x4
397#define DMA_CTRL_RCB_VALUE 0x8
398#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
399#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
400#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
401#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
402#define DMA_CTRL_DMAR_EN 0x400
403#define DMA_CTRL_DMAW_EN 0x800
404
405/* CMB/SMB Control Register */
406#define REG_CSMB_CTRL 0x15d0
407#define CSMB_CTRL_CMB_NOW 1
408#define CSMB_CTRL_SMB_NOW 2
409#define CSMB_CTRL_CMB_EN 4
410#define CSMB_CTRL_SMB_EN 8
411
412/* CMB DMA Write Threshold Register */
413#define REG_CMB_WRITE_TH (REG_CSMB_CTRL+ 4)
414#define CMB_RRD_TH_SHIFT 0
415#define CMB_RRD_TH_MASK 0x7ff
416#define CMB_TPD_TH_SHIFT 16
417#define CMB_TPD_TH_MASK 0x7ff
418
419/* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
420#define REG_CMB_WRITE_TIMER (REG_CSMB_CTRL+ 8)
421#define CMB_RX_TM_SHIFT 0
422#define CMB_RX_TM_MASK 0xffff
423#define CMB_TX_TM_SHIFT 16
424#define CMB_TX_TM_MASK 0xffff
425
426/* Number of packet received since last CMB write */
427#define REG_CMB_RX_PKT_CNT (REG_CSMB_CTRL+12)
428
429/* Number of packet transmitted since last CMB write */
430#define REG_CMB_TX_PKT_CNT (REG_CSMB_CTRL+16)
431
432/* SMB auto DMA timer register */
433#define REG_SMB_TIMER (REG_CSMB_CTRL+20)
434
435/* Mailbox Register */
436#define REG_MAILBOX 0x15f0
437#define MB_RFD_PROD_INDX_SHIFT 0
438#define MB_RFD_PROD_INDX_MASK 0x7ff
439#define MB_RRD_CONS_INDX_SHIFT 11
440#define MB_RRD_CONS_INDX_MASK 0x7ff
441#define MB_TPD_PROD_INDX_SHIFT 22
442#define MB_TPD_PROD_INDX_MASK 0x3ff
443
444/* Interrupt Status Register */
445#define REG_ISR 0x1600
446#define ISR_SMB 1
447#define ISR_TIMER 2
448#define ISR_MANUAL 4
449#define ISR_RXF_OV 8
450#define ISR_RFD_UNRUN 0x10
451#define ISR_RRD_OV 0x20
452#define ISR_TXF_UNRUN 0x40
453#define ISR_LINK 0x80
454#define ISR_HOST_RFD_UNRUN 0x100
455#define ISR_HOST_RRD_OV 0x200
456#define ISR_DMAR_TO_RST 0x400
457#define ISR_DMAW_TO_RST 0x800
458#define ISR_GPHY 0x1000
459#define ISR_RX_PKT 0x10000
460#define ISR_TX_PKT 0x20000
461#define ISR_TX_DMA 0x40000
462#define ISR_RX_DMA 0x80000
463#define ISR_CMB_RX 0x100000
464#define ISR_CMB_TX 0x200000
465#define ISR_MAC_RX 0x400000
466#define ISR_MAC_TX 0x800000
467#define ISR_UR_DETECTED 0x1000000
468#define ISR_FERR_DETECTED 0x2000000
469#define ISR_NFERR_DETECTED 0x4000000
470#define ISR_CERR_DETECTED 0x8000000
471#define ISR_PHY_LINKDOWN 0x10000000
472#define ISR_DIS_SMB 0x20000000
473#define ISR_DIS_DMA 0x40000000
474#define ISR_DIS_INT 0x80000000
475
476/* Interrupt Mask Register */
477#define REG_IMR 0x1604
478
479/* Normal Interrupt mask */
480#define IMR_NORMAL_MASK (\
481 ISR_SMB |\
482 ISR_GPHY |\
483 ISR_PHY_LINKDOWN|\
484 ISR_DMAR_TO_RST |\
485 ISR_DMAW_TO_RST |\
486 ISR_CMB_TX |\
487 ISR_CMB_RX )
488
489/* Debug Interrupt Mask (enable all interrupt) */
490#define IMR_DEBUG_MASK (\
491 ISR_SMB |\
492 ISR_TIMER |\
493 ISR_MANUAL |\
494 ISR_RXF_OV |\
495 ISR_RFD_UNRUN |\
496 ISR_RRD_OV |\
497 ISR_TXF_UNRUN |\
498 ISR_LINK |\
499 ISR_CMB_TX |\
500 ISR_CMB_RX |\
501 ISR_RX_PKT |\
502 ISR_TX_PKT |\
503 ISR_MAC_RX |\
504 ISR_MAC_TX )
505
506/* Interrupt Status Register */
507#define REG_RFD_RRD_IDX 0x1800
508#define REG_TPD_IDX 0x1804
509
510/* MII definition */
511/* PHY Common Register */
512#define MII_AT001_CR 0x09
513#define MII_AT001_SR 0x0A
514#define MII_AT001_ESR 0x0F
515#define MII_AT001_PSCR 0x10
516#define MII_AT001_PSSR 0x11
517
518/* PHY Control Register */
519#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
520#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
521#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
522#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
523#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
524#define MII_CR_POWER_DOWN 0x0800 /* Power down */
525#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
526#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
527#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
528#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
529#define MII_CR_SPEED_MASK 0x2040
530#define MII_CR_SPEED_1000 0x0040
531#define MII_CR_SPEED_100 0x2000
532#define MII_CR_SPEED_10 0x0000
533
534/* PHY Status Register */
535#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
536#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
537#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
538#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
539#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
540#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
541#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
542#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
543#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
544#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
545#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
546#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
547#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
548#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
549#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
550
551/* Link partner ability register. */
552#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
553#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
554#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
555#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
556#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
557#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
558#define MII_LPA_PAUSE 0x0400 /* PAUSE */
559#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
560#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
561#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
562#define MII_LPA_NPAGE 0x8000 /* Next page bit */
563
564/* Autoneg Advertisement Register */
565#define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
566#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
567#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
568#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
569#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
570#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
571#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
572#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
573#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
574#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
575#define MII_AR_SPEED_MASK 0x01E0
576#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
577
578/* 1000BASE-T Control Register */
579#define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
580#define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
581#define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port, 0=DTE device */
582#define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master, 0=Configure PHY as Slave */
583#define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value, 0=Automatic Master/Slave config */
584#define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
585#define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
586#define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
587#define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
588#define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
589#define MII_AT001_CR_1000T_SPEED_MASK 0x0300
590#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300
591
592/* 1000BASE-T Status Register */
593#define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
594#define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
595#define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
596#define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
597#define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
598#define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
599#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
600#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
601
602/* Extended Status Register */
603#define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
604#define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
605#define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
606#define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
607
608/* AT001 PHY Specific Control Register */
609#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
610#define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
611#define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
612#define MII_AT001_PSCR_MAC_POWERDOWN 0x0008
613#define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 0=CLK125 toggling */
614#define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5, Manual MDI configuration */
615#define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
616#define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
617#define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled all speeds. */
618#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold), 0=Normal 10BASE-T RX Threshold */
619#define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
620#define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
621#define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
622#define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
623#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1
624#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5
625#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
626
627/* AT001 PHY Specific Status Register */
628#define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
629#define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
630#define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
631#define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */
632#define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */
633#define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
634
635/* PCI Command Register Bit Definitions */
636#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
637#define CMD_IO_SPACE 0x0001
638#define CMD_MEMORY_SPACE 0x0002
639#define CMD_BUS_MASTER 0x0004
640
641/* Wake Up Filter Control */
642#define ATL1_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
643#define ATL1_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
644#define ATL1_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
645#define ATL1_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
646#define ATL1_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
647
648/* Error Codes */
649#define ATL1_SUCCESS 0
650#define ATL1_ERR_EEPROM 1
651#define ATL1_ERR_PHY 2
652#define ATL1_ERR_CONFIG 3
653#define ATL1_ERR_PARAM 4
654#define ATL1_ERR_MAC_TYPE 5
655#define ATL1_ERR_PHY_TYPE 6
656#define ATL1_ERR_PHY_SPEED 7
657#define ATL1_ERR_PHY_RES 8
658
659#define SPEED_0 0xffff
660#define SPEED_10 10
661#define SPEED_100 100
662#define SPEED_1000 1000
663#define HALF_DUPLEX 1
664#define FULL_DUPLEX 2
665
666#define MEDIA_TYPE_AUTO_SENSOR 0
667#define MEDIA_TYPE_1000M_FULL 1
668#define MEDIA_TYPE_100M_FULL 2
669#define MEDIA_TYPE_100M_HALF 3
670#define MEDIA_TYPE_10M_FULL 4
671#define MEDIA_TYPE_10M_HALF 5
672
673#define ADVERTISE_10_HALF 0x0001
674#define ADVERTISE_10_FULL 0x0002
675#define ADVERTISE_100_HALF 0x0004
676#define ADVERTISE_100_FULL 0x0008
677#define ADVERTISE_1000_HALF 0x0010
678#define ADVERTISE_1000_FULL 0x0020
679#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
680#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
681#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
682
683/* The size (in bytes) of a ethernet packet */
684#define ENET_HEADER_SIZE 14
685#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* with FCS */
686#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* with FCS */
687#define ETHERNET_FCS_SIZE 4
688#define MAX_JUMBO_FRAME_SIZE 0x2800
689
690#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
691#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
692
693/* For checksumming , the sum of all words in the EEPROM should equal 0xBABA */
694#define EEPROM_SUM 0xBABA
695
696#define ATL1_EEDUMP_LEN 48
697
698/* Statistics counters collected by the MAC */
699struct stats_msg_block {
700 /* rx */
701 u32 rx_ok; /* The number of good packet received. */
702 u32 rx_bcast; /* The number of good broadcast packet received. */
703 u32 rx_mcast; /* The number of good multicast packet received. */
704 u32 rx_pause; /* The number of Pause packet received. */
705 u32 rx_ctrl; /* The number of Control packet received other than Pause frame. */
706 u32 rx_fcs_err; /* The number of packets with bad FCS. */
707 u32 rx_len_err; /* The number of packets with mismatch of length field and actual size. */
708 u32 rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
709 u32 rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
710 u32 rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
711 u32 rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
712 u32 rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
713 u32 rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
714 u32 rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
715 u32 rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
716 u32 rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
717 u32 rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
718 u32 rx_sz_ov; /* The number of good and bad packets received that are more than MTU size šC truncated by Selene. */
719 u32 rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
720 u32 rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
721 u32 rx_align_err; /* Alignment Error */
722 u32 rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
723 u32 rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
724 u32 rx_err_addr; /* The number of packets dropped due to address filtering. */
725
726 /* tx */
727 u32 tx_ok; /* The number of good packet transmitted. */
728 u32 tx_bcast; /* The number of good broadcast packet transmitted. */
729 u32 tx_mcast; /* The number of good multicast packet transmitted. */
730 u32 tx_pause; /* The number of Pause packet transmitted. */
731 u32 tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
732 u32 tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
733 u32 tx_defer; /* The number of packets transmitted that is deferred. */
734 u32 tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
735 u32 tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
736 u32 tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
737 u32 tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
738 u32 tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
739 u32 tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
740 u32 tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
741 u32 tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
742 u32 tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
743 u32 tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
744 u32 tx_late_col; /* The number of packets transmitted with late collisions. */
745 u32 tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
746 u32 tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
747 u32 tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
748 u32 tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
749 u32 tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
750 u32 tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
751 u32 tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
752 u32 smb_updated; /* 1: SMB Updated. This is used by software as the indication of the statistics update.
753 * Software should clear this bit as soon as retrieving the statistics information. */
754};
755
756/* Coalescing Message Block */
757struct coals_msg_block {
758 u32 int_stats; /* interrupt status */
759 u16 rrd_prod_idx; /* TRD Producer Index. */
760 u16 rfd_cons_idx; /* RFD Consumer Index. */
761 u16 update; /* Selene sets this bit every time it DMA the CMB to host memory.
762 * Software supposes to clear this bit when CMB information is processed. */
763 u16 tpd_cons_idx; /* TPD Consumer Index. */
764};
765
766/* RRD descriptor */
767struct rx_return_desc {
768 u8 num_buf; /* Number of RFD buffers used by the received packet */
769 u8 resved;
770 u16 buf_indx; /* RFD Index of the first buffer */
771 union {
772 u32 valid;
773 struct {
774 u16 rx_chksum;
775 u16 pkt_size;
776 } xsum_sz;
777 } xsz;
778
779 u16 pkt_flg; /* Packet flags */
780 u16 err_flg; /* Error flags */
781 u16 resved2;
782 u16 vlan_tag; /* VLAN TAG */
783};
784
785#define PACKET_FLAG_ETH_TYPE 0x0080
786#define PACKET_FLAG_VLAN_INS 0x0100
787#define PACKET_FLAG_ERR 0x0200
788#define PACKET_FLAG_IPV4 0x0400
789#define PACKET_FLAG_UDP 0x0800
790#define PACKET_FLAG_TCP 0x1000
791#define PACKET_FLAG_BCAST 0x2000
792#define PACKET_FLAG_MCAST 0x4000
793#define PACKET_FLAG_PAUSE 0x8000
794
795#define ERR_FLAG_CRC 0x0001
796#define ERR_FLAG_CODE 0x0002
797#define ERR_FLAG_DRIBBLE 0x0004
798#define ERR_FLAG_RUNT 0x0008
799#define ERR_FLAG_OV 0x0010
800#define ERR_FLAG_TRUNC 0x0020
801#define ERR_FLAG_IP_CHKSUM 0x0040
802#define ERR_FLAG_L4_CHKSUM 0x0080
803#define ERR_FLAG_LEN 0x0100
804#define ERR_FLAG_DES_ADDR 0x0200
805
806/* RFD descriptor */
807struct rx_free_desc {
808 __le64 buffer_addr; /* Address of the descriptor's data buffer */
809 __le16 buf_len; /* Size of the receive buffer in host memory, in byte */
810 u16 coalese; /* Update consumer index to host after the reception of this frame */
811 /* __attribute__ ((packed)) is required */
812} __attribute__ ((packed));
813
814/* tsopu defines */
815#define TSO_PARAM_BUFLEN_MASK 0x3FFF
816#define TSO_PARAM_BUFLEN_SHIFT 0
817#define TSO_PARAM_DMAINT_MASK 0x0001
818#define TSO_PARAM_DMAINT_SHIFT 14
819#define TSO_PARAM_PKTNT_MASK 0x0001
820#define TSO_PARAM_PKTINT_SHIFT 15
821#define TSO_PARAM_VLANTAG_MASK 0xFFFF
822#define TSO_PARAM_VLAN_SHIFT 16
823
824/* tsopl defines */
825#define TSO_PARAM_EOP_MASK 0x0001
826#define TSO_PARAM_EOP_SHIFT 0
827#define TSO_PARAM_COALESCE_MASK 0x0001
828#define TSO_PARAM_COALESCE_SHIFT 1
829#define TSO_PARAM_INSVLAG_MASK 0x0001
830#define TSO_PARAM_INSVLAG_SHIFT 2
831#define TSO_PARAM_CUSTOMCKSUM_MASK 0x0001
832#define TSO_PARAM_CUSTOMCKSUM_SHIFT 3
833#define TSO_PARAM_SEGMENT_MASK 0x0001
834#define TSO_PARAM_SEGMENT_SHIFT 4
835#define TSO_PARAM_IPCKSUM_MASK 0x0001
836#define TSO_PARAM_IPCKSUM_SHIFT 5
837#define TSO_PARAM_TCPCKSUM_MASK 0x0001
838#define TSO_PARAM_TCPCKSUM_SHIFT 6
839#define TSO_PARAM_UDPCKSUM_MASK 0x0001
840#define TSO_PARAM_UDPCKSUM_SHIFT 7
841#define TSO_PARAM_VLANTAGGED_MASK 0x0001
842#define TSO_PARAM_VLANTAGGED_SHIFT 8
843#define TSO_PARAM_ETHTYPE_MASK 0x0001
844#define TSO_PARAM_ETHTYPE_SHIFT 9
845#define TSO_PARAM_IPHL_MASK 0x000F
846#define TSO_PARAM_IPHL_SHIFT 10
847#define TSO_PARAM_TCPHDRLEN_MASK 0x000F
848#define TSO_PARAM_TCPHDRLEN_SHIFT 14
849#define TSO_PARAM_HDRFLAG_MASK 0x0001
850#define TSO_PARAM_HDRFLAG_SHIFT 18
851#define TSO_PARAM_MSS_MASK 0x1FFF
852#define TSO_PARAM_MSS_SHIFT 19
853
854/* csumpu defines */
855#define CSUM_PARAM_BUFLEN_MASK 0x3FFF
856#define CSUM_PARAM_BUFLEN_SHIFT 0
857#define CSUM_PARAM_DMAINT_MASK 0x0001
858#define CSUM_PARAM_DMAINT_SHIFT 14
859#define CSUM_PARAM_PKTINT_MASK 0x0001
860#define CSUM_PARAM_PKTINT_SHIFT 15
861#define CSUM_PARAM_VALANTAG_MASK 0xFFFF
862#define CSUM_PARAM_VALAN_SHIFT 16
863
864/* csumpl defines*/
865#define CSUM_PARAM_EOP_MASK 0x0001
866#define CSUM_PARAM_EOP_SHIFT 0
867#define CSUM_PARAM_COALESCE_MASK 0x0001
868#define CSUM_PARAM_COALESCE_SHIFT 1
869#define CSUM_PARAM_INSVLAG_MASK 0x0001
870#define CSUM_PARAM_INSVLAG_SHIFT 2
871#define CSUM_PARAM_CUSTOMCKSUM_MASK 0x0001
872#define CSUM_PARAM_CUSTOMCKSUM_SHIFT 3
873#define CSUM_PARAM_SEGMENT_MASK 0x0001
874#define CSUM_PARAM_SEGMENT_SHIFT 4
875#define CSUM_PARAM_IPCKSUM_MASK 0x0001
876#define CSUM_PARAM_IPCKSUM_SHIFT 5
877#define CSUM_PARAM_TCPCKSUM_MASK 0x0001
878#define CSUM_PARAM_TCPCKSUM_SHIFT 6
879#define CSUM_PARAM_UDPCKSUM_MASK 0x0001
880#define CSUM_PARAM_UDPCKSUM_SHIFT 7
881#define CSUM_PARAM_VLANTAGGED_MASK 0x0001
882#define CSUM_PARAM_VLANTAGGED_SHIFT 8
883#define CSUM_PARAM_ETHTYPE_MASK 0x0001
884#define CSUM_PARAM_ETHTYPE_SHIFT 9
885#define CSUM_PARAM_IPHL_MASK 0x000F
886#define CSUM_PARAM_IPHL_SHIFT 10
887#define CSUM_PARAM_PLOADOFFSET_MASK 0x00FF
888#define CSUM_PARAM_PLOADOFFSET_SHIFT 16
889#define CSUM_PARAM_XSUMOFFSET_MASK 0x00FF
890#define CSUM_PARAM_XSUMOFFSET_SHIFT 24
891
892/* TPD descriptor */
893struct tso_param {
894 /* The order of these declarations is important -- don't change it */
895 u32 tsopu; /* tso_param upper word */
896 u32 tsopl; /* tso_param lower word */
897};
898
899struct csum_param {
900 /* The order of these declarations is important -- don't change it */
901 u32 csumpu; /* csum_param upper word */
902 u32 csumpl; /* csum_param lower word */
903};
904
905union tpd_descr {
906 u64 data;
907 struct csum_param csum;
908 struct tso_param tso;
909};
910
911struct tx_packet_desc {
912 __le64 buffer_addr;
913 union tpd_descr desc;
914};
915
916/* DMA Order Settings */
917enum atl1_dma_order {
918 atl1_dma_ord_in = 1,
919 atl1_dma_ord_enh = 2,
920 atl1_dma_ord_out = 4
921};
922
923enum atl1_dma_rcb {
924 atl1_rcb_64 = 0,
925 atl1_rcb_128 = 1
926};
927
928enum atl1_dma_req_block {
929 atl1_dma_req_128 = 0,
930 atl1_dma_req_256 = 1,
931 atl1_dma_req_512 = 2,
932 atl1_dam_req_1024 = 3,
933 atl1_dam_req_2048 = 4,
934 atl1_dma_req_4096 = 5
935};
936
937struct atl1_spi_flash_dev {
938 const char *manu_name; /* manufacturer id */
939 /* op-code */
940 u8 cmd_wrsr;
941 u8 cmd_read;
942 u8 cmd_program;
943 u8 cmd_wren;
944 u8 cmd_wrdi;
945 u8 cmd_rdsr;
946 u8 cmd_rdid;
947 u8 cmd_sector_erase;
948 u8 cmd_chip_erase;
949};
950
951#endif /* _ATL1_HW_H_ */
diff --git a/drivers/net/atl1/atl1_main.c b/drivers/net/atl1/atl1_main.c
new file mode 100644
index 000000000000..6655640eb4ca
--- /dev/null
+++ b/drivers/net/atl1/atl1_main.c
@@ -0,0 +1,2468 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called COPYING.
25 *
26 * Contact Information:
27 * Xiong Huang <xiong_huang@attansic.com>
28 * Attansic Technology Corp. 3F 147, Xianzheng 9th Road, Zhubei,
29 * Xinzhu 302, TAIWAN, REPUBLIC OF CHINA
30 *
31 * Chris Snook <csnook@redhat.com>
32 * Jay Cliburn <jcliburn@gmail.com>
33 *
34 * This version is adapted from the Attansic reference driver for
35 * inclusion in the Linux kernel. It is currently under heavy development.
36 * A very incomplete list of things that need to be dealt with:
37 *
38 * TODO:
39 * Fix TSO; tx performance is horrible with TSO enabled.
40 * Wake on LAN.
41 * Add more ethtool functions, including set ring parameters.
42 * Fix abstruse irq enable/disable condition described here:
43 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
44 *
45 * NEEDS TESTING:
46 * VLAN
47 * multicast
48 * promiscuous mode
49 * interrupt coalescing
50 * SMP torture testing
51 */
52
53#include <linux/types.h>
54#include <linux/netdevice.h>
55#include <linux/pci.h>
56#include <linux/spinlock.h>
57#include <linux/slab.h>
58#include <linux/string.h>
59#include <linux/skbuff.h>
60#include <linux/etherdevice.h>
61#include <linux/if_vlan.h>
62#include <linux/irqreturn.h>
63#include <linux/workqueue.h>
64#include <linux/timer.h>
65#include <linux/jiffies.h>
66#include <linux/hardirq.h>
67#include <linux/interrupt.h>
68#include <linux/irqflags.h>
69#include <linux/dma-mapping.h>
70#include <linux/net.h>
71#include <linux/pm.h>
72#include <linux/in.h>
73#include <linux/ip.h>
74#include <linux/tcp.h>
75#include <linux/compiler.h>
76#include <linux/delay.h>
77#include <linux/mii.h>
78#include <net/checksum.h>
79
80#include <asm/atomic.h>
81#include <asm/byteorder.h>
82
83#include "atl1.h"
84
85#define RUN_REALTIME 0
86#define DRIVER_VERSION "2.0.6"
87
88char atl1_driver_name[] = "atl1";
89static const char atl1_driver_string[] = "Attansic L1 Ethernet Network Driver";
90static const char atl1_copyright[] = "Copyright(c) 2005-2006 Attansic Corporation.";
91char atl1_driver_version[] = DRIVER_VERSION;
92
93MODULE_AUTHOR
94 ("Attansic Corporation <xiong_huang@attansic.com>, Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>");
95MODULE_DESCRIPTION("Attansic 1000M Ethernet Network Driver");
96MODULE_LICENSE("GPL");
97MODULE_VERSION(DRIVER_VERSION);
98
99/*
100 * atl1_pci_tbl - PCI Device ID Table
101 */
102static const struct pci_device_id atl1_pci_tbl[] = {
103 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, 0x1048)},
104 /* required last entry */
105 {0,}
106};
107
108MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
109
110/*
111 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
112 * @adapter: board private structure to initialize
113 *
114 * atl1_sw_init initializes the Adapter private data structure.
115 * Fields are initialized based on PCI device information and
116 * OS network device settings (MTU size).
117 */
118static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
119{
120 struct atl1_hw *hw = &adapter->hw;
121 struct net_device *netdev = adapter->netdev;
122 struct pci_dev *pdev = adapter->pdev;
123
124 /* PCI config space info */
125 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
126
127 hw->max_frame_size = netdev->mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
128 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
129
130 adapter->wol = 0;
131 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
132 adapter->ict = 50000; /* 100ms */
133 adapter->link_speed = SPEED_0; /* hardware init */
134 adapter->link_duplex = FULL_DUPLEX;
135
136 hw->phy_configured = false;
137 hw->preamble_len = 7;
138 hw->ipgt = 0x60;
139 hw->min_ifg = 0x50;
140 hw->ipgr1 = 0x40;
141 hw->ipgr2 = 0x60;
142 hw->max_retry = 0xf;
143 hw->lcol = 0x37;
144 hw->jam_ipg = 7;
145 hw->rfd_burst = 8;
146 hw->rrd_burst = 8;
147 hw->rfd_fetch_gap = 1;
148 hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
149 hw->rx_jumbo_lkah = 1;
150 hw->rrd_ret_timer = 16;
151 hw->tpd_burst = 4;
152 hw->tpd_fetch_th = 16;
153 hw->txf_burst = 0x100;
154 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
155 hw->tpd_fetch_gap = 1;
156 hw->rcb_value = atl1_rcb_64;
157 hw->dma_ord = atl1_dma_ord_enh;
158 hw->dmar_block = atl1_dma_req_256;
159 hw->dmaw_block = atl1_dma_req_256;
160 hw->cmb_rrd = 4;
161 hw->cmb_tpd = 4;
162 hw->cmb_rx_timer = 1; /* about 2us */
163 hw->cmb_tx_timer = 1; /* about 2us */
164 hw->smb_timer = 100000; /* about 200ms */
165
166 atomic_set(&adapter->irq_sem, 0);
167 spin_lock_init(&adapter->lock);
168 spin_lock_init(&adapter->mb_lock);
169
170 return 0;
171}
172
173/*
174 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
175 * @adapter: board private structure
176 *
177 * Return 0 on success, negative on failure
178 */
179s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
180{
181 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
182 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
183 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
184 struct atl1_ring_header *ring_header = &adapter->ring_header;
185 struct pci_dev *pdev = adapter->pdev;
186 int size;
187 u8 offset = 0;
188
189 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
190 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
191 if (unlikely(!tpd_ring->buffer_info)) {
192 printk(KERN_WARNING "%s: kzalloc failed , size = D%d\n",
193 atl1_driver_name, size);
194 goto err_nomem;
195 }
196 rfd_ring->buffer_info =
197 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
198
199 /* real ring DMA buffer */
200 ring_header->size = size = sizeof(struct tx_packet_desc) *
201 tpd_ring->count
202 + sizeof(struct rx_free_desc) * rfd_ring->count
203 + sizeof(struct rx_return_desc) * rrd_ring->count
204 + sizeof(struct coals_msg_block)
205 + sizeof(struct stats_msg_block)
206 + 40; /* "40: for 8 bytes align" huh? -- CHS */
207
208 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
209 &ring_header->dma);
210 if (unlikely(!ring_header->desc)) {
211 printk(KERN_WARNING
212 "%s: pci_alloc_consistent failed, size = D%d\n",
213 atl1_driver_name, size);
214 goto err_nomem;
215 }
216
217 memset(ring_header->desc, 0, ring_header->size);
218
219 /* init TPD ring */
220 tpd_ring->dma = ring_header->dma;
221 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
222 tpd_ring->dma += offset;
223 tpd_ring->desc = (u8 *) ring_header->desc + offset;
224 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
225 atomic_set(&tpd_ring->next_to_use, 0);
226 atomic_set(&tpd_ring->next_to_clean, 0);
227
228 /* init RFD ring */
229 rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
230 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
231 rfd_ring->dma += offset;
232 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
233 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
234 rfd_ring->next_to_clean = 0;
235 /* rfd_ring->next_to_use = rfd_ring->count - 1; */
236 atomic_set(&rfd_ring->next_to_use, 0);
237
238 /* init RRD ring */
239 rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
240 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
241 rrd_ring->dma += offset;
242 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
243 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
244 rrd_ring->next_to_use = 0;
245 atomic_set(&rrd_ring->next_to_clean, 0);
246
247 /* init CMB */
248 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
249 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
250 adapter->cmb.dma += offset;
251 adapter->cmb.cmb =
252 (struct coals_msg_block *) ((u8 *) rrd_ring->desc +
253 (rrd_ring->size + offset));
254
255 /* init SMB */
256 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
257 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
258 adapter->smb.dma += offset;
259 adapter->smb.smb = (struct stats_msg_block *)
260 ((u8 *) adapter->cmb.cmb + (sizeof(struct coals_msg_block) + offset));
261
262 return ATL1_SUCCESS;
263
264err_nomem:
265 kfree(tpd_ring->buffer_info);
266 return -ENOMEM;
267}
268
269/*
270 * atl1_irq_enable - Enable default interrupt generation settings
271 * @adapter: board private structure
272 */
273static void atl1_irq_enable(struct atl1_adapter *adapter)
274{
275 if (likely(!atomic_dec_and_test(&adapter->irq_sem)))
276 iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
277}
278
279static void atl1_clear_phy_int(struct atl1_adapter *adapter)
280{
281 u16 phy_data;
282 unsigned long flags;
283
284 spin_lock_irqsave(&adapter->lock, flags);
285 atl1_read_phy_reg(&adapter->hw, 19, &phy_data);
286 spin_unlock_irqrestore(&adapter->lock, flags);
287}
288
289static void atl1_inc_smb(struct atl1_adapter *adapter)
290{
291 struct stats_msg_block *smb = adapter->smb.smb;
292
293 /* Fill out the OS statistics structure */
294 adapter->soft_stats.rx_packets += smb->rx_ok;
295 adapter->soft_stats.tx_packets += smb->tx_ok;
296 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
297 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
298 adapter->soft_stats.multicast += smb->rx_mcast;
299 adapter->soft_stats.collisions += (smb->tx_1_col +
300 smb->tx_2_col * 2 +
301 smb->tx_late_col +
302 smb->tx_abort_col *
303 adapter->hw.max_retry);
304
305 /* Rx Errors */
306 adapter->soft_stats.rx_errors += (smb->rx_frag +
307 smb->rx_fcs_err +
308 smb->rx_len_err +
309 smb->rx_sz_ov +
310 smb->rx_rxf_ov +
311 smb->rx_rrd_ov + smb->rx_align_err);
312 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
313 adapter->soft_stats.rx_length_errors += smb->rx_len_err;
314 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
315 adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
316 adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
317 smb->rx_rxf_ov);
318
319 adapter->soft_stats.rx_pause += smb->rx_pause;
320 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
321 adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
322
323 /* Tx Errors */
324 adapter->soft_stats.tx_errors += (smb->tx_late_col +
325 smb->tx_abort_col +
326 smb->tx_underrun + smb->tx_trunc);
327 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
328 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
329 adapter->soft_stats.tx_window_errors += smb->tx_late_col;
330
331 adapter->soft_stats.excecol += smb->tx_abort_col;
332 adapter->soft_stats.deffer += smb->tx_defer;
333 adapter->soft_stats.scc += smb->tx_1_col;
334 adapter->soft_stats.mcc += smb->tx_2_col;
335 adapter->soft_stats.latecol += smb->tx_late_col;
336 adapter->soft_stats.tx_underun += smb->tx_underrun;
337 adapter->soft_stats.tx_trunc += smb->tx_trunc;
338 adapter->soft_stats.tx_pause += smb->tx_pause;
339
340 adapter->net_stats.rx_packets = adapter->soft_stats.rx_packets;
341 adapter->net_stats.tx_packets = adapter->soft_stats.tx_packets;
342 adapter->net_stats.rx_bytes = adapter->soft_stats.rx_bytes;
343 adapter->net_stats.tx_bytes = adapter->soft_stats.tx_bytes;
344 adapter->net_stats.multicast = adapter->soft_stats.multicast;
345 adapter->net_stats.collisions = adapter->soft_stats.collisions;
346 adapter->net_stats.rx_errors = adapter->soft_stats.rx_errors;
347 adapter->net_stats.rx_over_errors =
348 adapter->soft_stats.rx_missed_errors;
349 adapter->net_stats.rx_length_errors =
350 adapter->soft_stats.rx_length_errors;
351 adapter->net_stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
352 adapter->net_stats.rx_frame_errors =
353 adapter->soft_stats.rx_frame_errors;
354 adapter->net_stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
355 adapter->net_stats.rx_missed_errors =
356 adapter->soft_stats.rx_missed_errors;
357 adapter->net_stats.tx_errors = adapter->soft_stats.tx_errors;
358 adapter->net_stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
359 adapter->net_stats.tx_aborted_errors =
360 adapter->soft_stats.tx_aborted_errors;
361 adapter->net_stats.tx_window_errors =
362 adapter->soft_stats.tx_window_errors;
363 adapter->net_stats.tx_carrier_errors =
364 adapter->soft_stats.tx_carrier_errors;
365}
366
367static void atl1_rx_checksum(struct atl1_adapter *adapter,
368 struct rx_return_desc *rrd,
369 struct sk_buff *skb)
370{
371 skb->ip_summed = CHECKSUM_NONE;
372
373 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
374 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
375 ERR_FLAG_CODE | ERR_FLAG_OV)) {
376 adapter->hw_csum_err++;
377 printk(KERN_DEBUG "%s: rx checksum error\n",
378 atl1_driver_name);
379 return;
380 }
381 }
382
383 /* not IPv4 */
384 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
385 /* checksum is invalid, but it's not an IPv4 pkt, so ok */
386 return;
387
388 /* IPv4 packet */
389 if (likely(!(rrd->err_flg &
390 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
391 skb->ip_summed = CHECKSUM_UNNECESSARY;
392 adapter->hw_csum_good++;
393 return;
394 }
395
396 /* IPv4, but hardware thinks its checksum is wrong */
397 printk(KERN_DEBUG "%s: hw csum wrong pkt_flag:%x, err_flag:%x\n",
398 atl1_driver_name, rrd->pkt_flg, rrd->err_flg);
399 skb->ip_summed = CHECKSUM_COMPLETE;
400 skb->csum = htons(rrd->xsz.xsum_sz.rx_chksum);
401 adapter->hw_csum_err++;
402 return;
403}
404
405/*
406 * atl1_alloc_rx_buffers - Replace used receive buffers
407 * @adapter: address of board private structure
408 */
409static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
410{
411 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
412 struct net_device *netdev = adapter->netdev;
413 struct pci_dev *pdev = adapter->pdev;
414 struct page *page;
415 unsigned long offset;
416 struct atl1_buffer *buffer_info, *next_info;
417 struct sk_buff *skb;
418 u16 num_alloc = 0;
419 u16 rfd_next_to_use, next_next;
420 struct rx_free_desc *rfd_desc;
421
422 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
423 if (++next_next == rfd_ring->count)
424 next_next = 0;
425 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
426 next_info = &rfd_ring->buffer_info[next_next];
427
428 while (!buffer_info->alloced && !next_info->alloced) {
429 if (buffer_info->skb) {
430 buffer_info->alloced = 1;
431 goto next;
432 }
433
434 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
435
436 skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN);
437 if (unlikely(!skb)) { /* Better luck next round */
438 adapter->net_stats.rx_dropped++;
439 break;
440 }
441
442 /*
443 * Make buffer alignment 2 beyond a 16 byte boundary
444 * this will result in a 16 byte aligned IP header after
445 * the 14 byte MAC header is removed
446 */
447 skb_reserve(skb, NET_IP_ALIGN);
448 skb->dev = netdev;
449
450 buffer_info->alloced = 1;
451 buffer_info->skb = skb;
452 buffer_info->length = (u16) adapter->rx_buffer_len;
453 page = virt_to_page(skb->data);
454 offset = (unsigned long)skb->data & ~PAGE_MASK;
455 buffer_info->dma = pci_map_page(pdev, page, offset,
456 adapter->rx_buffer_len,
457 PCI_DMA_FROMDEVICE);
458 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
459 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
460 rfd_desc->coalese = 0;
461
462next:
463 rfd_next_to_use = next_next;
464 if (unlikely(++next_next == rfd_ring->count))
465 next_next = 0;
466
467 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
468 next_info = &rfd_ring->buffer_info[next_next];
469 num_alloc++;
470 }
471
472 if (num_alloc) {
473 /*
474 * Force memory writes to complete before letting h/w
475 * know there are new descriptors to fetch. (Only
476 * applicable for weak-ordered memory model archs,
477 * such as IA-64).
478 */
479 wmb();
480 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
481 }
482 return num_alloc;
483}
484
485static void atl1_intr_rx(struct atl1_adapter *adapter)
486{
487 int i, count;
488 u16 length;
489 u16 rrd_next_to_clean;
490 u32 value;
491 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
492 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
493 struct atl1_buffer *buffer_info;
494 struct rx_return_desc *rrd;
495 struct sk_buff *skb;
496
497 count = 0;
498
499 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
500
501 while (1) {
502 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
503 i = 1;
504 if (likely(rrd->xsz.valid)) { /* packet valid */
505chk_rrd:
506 /* check rrd status */
507 if (likely(rrd->num_buf == 1))
508 goto rrd_ok;
509
510 /* rrd seems to be bad */
511 if (unlikely(i-- > 0)) {
512 /* rrd may not be DMAed completely */
513 printk(KERN_DEBUG
514 "%s: RRD may not be DMAed completely\n",
515 atl1_driver_name);
516 udelay(1);
517 goto chk_rrd;
518 }
519 /* bad rrd */
520 printk(KERN_DEBUG "%s: bad RRD\n", atl1_driver_name);
521 /* see if update RFD index */
522 if (rrd->num_buf > 1) {
523 u16 num_buf;
524 num_buf =
525 (rrd->xsz.xsum_sz.pkt_size +
526 adapter->rx_buffer_len -
527 1) / adapter->rx_buffer_len;
528 if (rrd->num_buf == num_buf) {
529 /* clean alloc flag for bad rrd */
530 while (rfd_ring->next_to_clean !=
531 (rrd->buf_indx + num_buf)) {
532 rfd_ring->buffer_info[rfd_ring->
533 next_to_clean].alloced = 0;
534 if (++rfd_ring->next_to_clean ==
535 rfd_ring->count) {
536 rfd_ring->
537 next_to_clean = 0;
538 }
539 }
540 }
541 }
542
543 /* update rrd */
544 rrd->xsz.valid = 0;
545 if (++rrd_next_to_clean == rrd_ring->count)
546 rrd_next_to_clean = 0;
547 count++;
548 continue;
549 } else { /* current rrd still not be updated */
550
551 break;
552 }
553rrd_ok:
554 /* clean alloc flag for bad rrd */
555 while (rfd_ring->next_to_clean != rrd->buf_indx) {
556 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced =
557 0;
558 if (++rfd_ring->next_to_clean == rfd_ring->count)
559 rfd_ring->next_to_clean = 0;
560 }
561
562 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
563 if (++rfd_ring->next_to_clean == rfd_ring->count)
564 rfd_ring->next_to_clean = 0;
565
566 /* update rrd next to clean */
567 if (++rrd_next_to_clean == rrd_ring->count)
568 rrd_next_to_clean = 0;
569 count++;
570
571 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
572 if (!(rrd->err_flg &
573 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
574 | ERR_FLAG_LEN))) {
575 /* packet error, don't need upstream */
576 buffer_info->alloced = 0;
577 rrd->xsz.valid = 0;
578 continue;
579 }
580 }
581
582 /* Good Receive */
583 pci_unmap_page(adapter->pdev, buffer_info->dma,
584 buffer_info->length, PCI_DMA_FROMDEVICE);
585 skb = buffer_info->skb;
586 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
587
588 skb_put(skb, length - ETHERNET_FCS_SIZE);
589
590 /* Receive Checksum Offload */
591 atl1_rx_checksum(adapter, rrd, skb);
592 skb->protocol = eth_type_trans(skb, adapter->netdev);
593
594 if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) {
595 u16 vlan_tag = (rrd->vlan_tag >> 4) |
596 ((rrd->vlan_tag & 7) << 13) |
597 ((rrd->vlan_tag & 8) << 9);
598 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
599 } else
600 netif_rx(skb);
601
602 /* let protocol layer free skb */
603 buffer_info->skb = NULL;
604 buffer_info->alloced = 0;
605 rrd->xsz.valid = 0;
606
607 adapter->netdev->last_rx = jiffies;
608 }
609
610 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
611
612 atl1_alloc_rx_buffers(adapter);
613
614 /* update mailbox ? */
615 if (count) {
616 u32 tpd_next_to_use;
617 u32 rfd_next_to_use;
618 u32 rrd_next_to_clean;
619
620 spin_lock(&adapter->mb_lock);
621
622 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
623 rfd_next_to_use =
624 atomic_read(&adapter->rfd_ring.next_to_use);
625 rrd_next_to_clean =
626 atomic_read(&adapter->rrd_ring.next_to_clean);
627 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
628 MB_RFD_PROD_INDX_SHIFT) |
629 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
630 MB_RRD_CONS_INDX_SHIFT) |
631 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
632 MB_TPD_PROD_INDX_SHIFT);
633 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
634 spin_unlock(&adapter->mb_lock);
635 }
636}
637
638static void atl1_intr_tx(struct atl1_adapter *adapter)
639{
640 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
641 struct atl1_buffer *buffer_info;
642 u16 sw_tpd_next_to_clean;
643 u16 cmb_tpd_next_to_clean;
644 u8 update = 0;
645
646 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
647 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
648
649 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
650 struct tx_packet_desc *tpd;
651 update = 1;
652 tpd = ATL1_TPD_DESC(tpd_ring, sw_tpd_next_to_clean);
653 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
654 if (buffer_info->dma) {
655 pci_unmap_page(adapter->pdev, buffer_info->dma,
656 buffer_info->length, PCI_DMA_TODEVICE);
657 buffer_info->dma = 0;
658 }
659
660 if (buffer_info->skb) {
661 dev_kfree_skb_irq(buffer_info->skb);
662 buffer_info->skb = NULL;
663 }
664 tpd->buffer_addr = 0;
665 tpd->desc.data = 0;
666
667 if (++sw_tpd_next_to_clean == tpd_ring->count)
668 sw_tpd_next_to_clean = 0;
669 }
670 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
671
672 if (netif_queue_stopped(adapter->netdev)
673 && netif_carrier_ok(adapter->netdev))
674 netif_wake_queue(adapter->netdev);
675}
676
677static void atl1_check_for_link(struct atl1_adapter *adapter)
678{
679 struct net_device *netdev = adapter->netdev;
680 u16 phy_data = 0;
681
682 spin_lock(&adapter->lock);
683 adapter->phy_timer_pending = false;
684 atl1_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
685 atl1_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
686 spin_unlock(&adapter->lock);
687
688 /* notify upper layer link down ASAP */
689 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
690 if (netif_carrier_ok(netdev)) { /* old link state: Up */
691 printk(KERN_INFO "%s: %s link is down\n",
692 atl1_driver_name, netdev->name);
693 adapter->link_speed = SPEED_0;
694 netif_carrier_off(netdev);
695 netif_stop_queue(netdev);
696 }
697 }
698 schedule_work(&adapter->link_chg_task);
699}
700
701/*
702 * atl1_intr - Interrupt Handler
703 * @irq: interrupt number
704 * @data: pointer to a network interface device structure
705 * @pt_regs: CPU registers structure
706 */
707static irqreturn_t atl1_intr(int irq, void *data)
708{
709 /*struct atl1_adapter *adapter = ((struct net_device *)data)->priv;*/
710 struct atl1_adapter *adapter = netdev_priv(data);
711 u32 status;
712 u8 update_rx;
713 int max_ints = 10;
714
715 status = adapter->cmb.cmb->int_stats;
716 if (!status)
717 return IRQ_NONE;
718
719 update_rx = 0;
720
721 do {
722 /* clear CMB interrupt status at once */
723 adapter->cmb.cmb->int_stats = 0;
724
725 if (status & ISR_GPHY) /* clear phy status */
726 atl1_clear_phy_int(adapter);
727
728 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
729 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
730
731 /* check if SMB intr */
732 if (status & ISR_SMB)
733 atl1_inc_smb(adapter);
734
735 /* check if PCIE PHY Link down */
736 if (status & ISR_PHY_LINKDOWN) {
737 printk(KERN_DEBUG "%s: pcie phy link down %x\n",
738 atl1_driver_name, status);
739 if (netif_running(adapter->netdev)) { /* reset MAC */
740 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
741 schedule_work(&adapter->pcie_dma_to_rst_task);
742 return IRQ_HANDLED;
743 }
744 }
745
746 /* check if DMA read/write error ? */
747 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
748 printk(KERN_DEBUG
749 "%s: pcie DMA r/w error (status = 0x%x)\n",
750 atl1_driver_name, status);
751 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
752 schedule_work(&adapter->pcie_dma_to_rst_task);
753 return IRQ_HANDLED;
754 }
755
756 /* link event */
757 if (status & ISR_GPHY) {
758 adapter->soft_stats.tx_carrier_errors++;
759 atl1_check_for_link(adapter);
760 }
761
762 /* transmit event */
763 if (status & ISR_CMB_TX)
764 atl1_intr_tx(adapter);
765
766 /* rx exception */
767 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
768 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
769 ISR_HOST_RRD_OV | ISR_CMB_RX))) {
770 if (status &
771 (ISR_RXF_OV | ISR_RFD_UNRUN | ISR_RRD_OV |
772 ISR_HOST_RFD_UNRUN | ISR_HOST_RRD_OV))
773 printk(KERN_INFO
774 "%s: rx exception: status = 0x%x\n",
775 atl1_driver_name, status);
776 atl1_intr_rx(adapter);
777 }
778
779 if (--max_ints < 0)
780 break;
781
782 } while ((status = adapter->cmb.cmb->int_stats));
783
784 /* re-enable Interrupt */
785 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
786 return IRQ_HANDLED;
787}
788
789/*
790 * atl1_set_multi - Multicast and Promiscuous mode set
791 * @netdev: network interface device structure
792 *
793 * The set_multi entry point is called whenever the multicast address
794 * list or the network interface flags are updated. This routine is
795 * responsible for configuring the hardware for proper multicast,
796 * promiscuous mode, and all-multi behavior.
797 */
798static void atl1_set_multi(struct net_device *netdev)
799{
800 struct atl1_adapter *adapter = netdev_priv(netdev);
801 struct atl1_hw *hw = &adapter->hw;
802 struct dev_mc_list *mc_ptr;
803 u32 rctl;
804 u32 hash_value;
805
806 /* Check for Promiscuous and All Multicast modes */
807 rctl = ioread32(hw->hw_addr + REG_MAC_CTRL);
808 if (netdev->flags & IFF_PROMISC)
809 rctl |= MAC_CTRL_PROMIS_EN;
810 else if (netdev->flags & IFF_ALLMULTI) {
811 rctl |= MAC_CTRL_MC_ALL_EN;
812 rctl &= ~MAC_CTRL_PROMIS_EN;
813 } else
814 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
815
816 iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL);
817
818 /* clear the old settings from the multicast hash table */
819 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
820 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
821
822 /* compute mc addresses' hash value ,and put it into hash table */
823 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
824 hash_value = atl1_hash_mc_addr(hw, mc_ptr->dmi_addr);
825 atl1_hash_set(hw, hash_value);
826 }
827}
828
829static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
830{
831 u32 value;
832 struct atl1_hw *hw = &adapter->hw;
833 struct net_device *netdev = adapter->netdev;
834 /* Config MAC CTRL Register */
835 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
836 /* duplex */
837 if (FULL_DUPLEX == adapter->link_duplex)
838 value |= MAC_CTRL_DUPLX;
839 /* speed */
840 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
841 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
842 MAC_CTRL_SPEED_SHIFT);
843 /* flow control */
844 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
845 /* PAD & CRC */
846 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
847 /* preamble length */
848 value |= (((u32) adapter->hw.preamble_len
849 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
850 /* vlan */
851 if (adapter->vlgrp)
852 value |= MAC_CTRL_RMV_VLAN;
853 /* rx checksum
854 if (adapter->rx_csum)
855 value |= MAC_CTRL_RX_CHKSUM_EN;
856 */
857 /* filter mode */
858 value |= MAC_CTRL_BC_EN;
859 if (netdev->flags & IFF_PROMISC)
860 value |= MAC_CTRL_PROMIS_EN;
861 else if (netdev->flags & IFF_ALLMULTI)
862 value |= MAC_CTRL_MC_ALL_EN;
863 /* value |= MAC_CTRL_LOOPBACK; */
864 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
865}
866
867static u32 atl1_check_link(struct atl1_adapter *adapter)
868{
869 struct atl1_hw *hw = &adapter->hw;
870 struct net_device *netdev = adapter->netdev;
871 u32 ret_val;
872 u16 speed, duplex, phy_data;
873 int reconfig = 0;
874
875 /* MII_BMSR must read twice */
876 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
877 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
878 if (!(phy_data & BMSR_LSTATUS)) { /* link down */
879 if (netif_carrier_ok(netdev)) { /* old link state: Up */
880 printk(KERN_INFO "%s: link is down\n",
881 atl1_driver_name);
882 adapter->link_speed = SPEED_0;
883 netif_carrier_off(netdev);
884 netif_stop_queue(netdev);
885 }
886 return ATL1_SUCCESS;
887 }
888
889 /* Link Up */
890 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
891 if (ret_val)
892 return ret_val;
893
894 switch (hw->media_type) {
895 case MEDIA_TYPE_1000M_FULL:
896 if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
897 reconfig = 1;
898 break;
899 case MEDIA_TYPE_100M_FULL:
900 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
901 reconfig = 1;
902 break;
903 case MEDIA_TYPE_100M_HALF:
904 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
905 reconfig = 1;
906 break;
907 case MEDIA_TYPE_10M_FULL:
908 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
909 reconfig = 1;
910 break;
911 case MEDIA_TYPE_10M_HALF:
912 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
913 reconfig = 1;
914 break;
915 }
916
917 /* link result is our setting */
918 if (!reconfig) {
919 if (adapter->link_speed != speed
920 || adapter->link_duplex != duplex) {
921 adapter->link_speed = speed;
922 adapter->link_duplex = duplex;
923 atl1_setup_mac_ctrl(adapter);
924 printk(KERN_INFO "%s: %s link is up %d Mbps %s\n",
925 atl1_driver_name, netdev->name,
926 adapter->link_speed,
927 adapter->link_duplex ==
928 FULL_DUPLEX ? "full duplex" : "half duplex");
929 }
930 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
931 netif_carrier_on(netdev);
932 netif_wake_queue(netdev);
933 }
934 return ATL1_SUCCESS;
935 }
936
937 /* change orignal link status */
938 if (netif_carrier_ok(netdev)) {
939 adapter->link_speed = SPEED_0;
940 netif_carrier_off(netdev);
941 netif_stop_queue(netdev);
942 }
943
944 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
945 hw->media_type != MEDIA_TYPE_1000M_FULL) {
946 switch (hw->media_type) {
947 case MEDIA_TYPE_100M_FULL:
948 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
949 MII_CR_RESET;
950 break;
951 case MEDIA_TYPE_100M_HALF:
952 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
953 break;
954 case MEDIA_TYPE_10M_FULL:
955 phy_data =
956 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
957 break;
958 default: /* MEDIA_TYPE_10M_HALF: */
959 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
960 break;
961 }
962 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
963 return ATL1_SUCCESS;
964 }
965
966 /* auto-neg, insert timer to re-config phy */
967 if (!adapter->phy_timer_pending) {
968 adapter->phy_timer_pending = true;
969 mod_timer(&adapter->phy_config_timer, jiffies + 3 * HZ);
970 }
971
972 return ATL1_SUCCESS;
973}
974
975static void set_flow_ctrl_old(struct atl1_adapter *adapter)
976{
977 u32 hi, lo, value;
978
979 /* RFD Flow Control */
980 value = adapter->rfd_ring.count;
981 hi = value / 16;
982 if (hi < 2)
983 hi = 2;
984 lo = value * 7 / 8;
985
986 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
987 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
988 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
989
990 /* RRD Flow Control */
991 value = adapter->rrd_ring.count;
992 lo = value / 16;
993 hi = value * 7 / 8;
994 if (lo < 2)
995 lo = 2;
996 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
997 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
998 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
999}
1000
1001static void set_flow_ctrl_new(struct atl1_hw *hw)
1002{
1003 u32 hi, lo, value;
1004
1005 /* RXF Flow Control */
1006 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1007 lo = value / 16;
1008 if (lo < 192)
1009 lo = 192;
1010 hi = value * 7 / 8;
1011 if (hi < lo)
1012 hi = lo + 16;
1013 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1014 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1015 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1016
1017 /* RRD Flow Control */
1018 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1019 lo = value / 8;
1020 hi = value * 7 / 8;
1021 if (lo < 2)
1022 lo = 2;
1023 if (hi < lo)
1024 hi = lo + 3;
1025 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1026 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1027 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1028}
1029
1030/*
1031 * atl1_configure - Configure Transmit&Receive Unit after Reset
1032 * @adapter: board private structure
1033 *
1034 * Configure the Tx /Rx unit of the MAC after a reset.
1035 */
1036static u32 atl1_configure(struct atl1_adapter *adapter)
1037{
1038 struct atl1_hw *hw = &adapter->hw;
1039 u32 value;
1040
1041 /* clear interrupt status */
1042 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1043
1044 /* set MAC Address */
1045 value = (((u32) hw->mac_addr[2]) << 24) |
1046 (((u32) hw->mac_addr[3]) << 16) |
1047 (((u32) hw->mac_addr[4]) << 8) |
1048 (((u32) hw->mac_addr[5]));
1049 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1050 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1051 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1052
1053 /* tx / rx ring */
1054
1055 /* HI base address */
1056 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
1057 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1058 /* LO base address */
1059 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
1060 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1061 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
1062 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1063 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
1064 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1065 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
1066 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1067 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
1068 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
1069
1070 /* element count */
1071 value = adapter->rrd_ring.count;
1072 value <<= 16;
1073 value += adapter->rfd_ring.count;
1074 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1075 iowrite32(adapter->tpd_ring.count, hw->hw_addr + REG_DESC_TPD_RING_SIZE);
1076
1077 /* Load Ptr */
1078 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
1079
1080 /* config Mailbox */
1081 value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1082 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
1083 ((atomic_read(&adapter->rrd_ring.next_to_clean)
1084 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
1085 ((atomic_read(&adapter->rfd_ring.next_to_use)
1086 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
1087 iowrite32(value, hw->hw_addr + REG_MAILBOX);
1088
1089 /* config IPG/IFG */
1090 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1091 << MAC_IPG_IFG_IPGT_SHIFT) |
1092 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1093 << MAC_IPG_IFG_MIFG_SHIFT) |
1094 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1095 << MAC_IPG_IFG_IPGR1_SHIFT) |
1096 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1097 << MAC_IPG_IFG_IPGR2_SHIFT);
1098 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
1099
1100 /* config Half-Duplex Control */
1101 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1102 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1103 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
1104 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
1105 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
1106 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1107 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
1108 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
1109
1110 /* set Interrupt Moderator Timer */
1111 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1112 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
1113
1114 /* set Interrupt Clear Timer */
1115 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
1116
1117 /* set MTU, 4 : VLAN */
1118 iowrite32(hw->max_frame_size + 4, hw->hw_addr + REG_MTU);
1119
1120 /* jumbo size & rrd retirement timer */
1121 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1122 << RXQ_JMBOSZ_TH_SHIFT) |
1123 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1124 << RXQ_JMBO_LKAH_SHIFT) |
1125 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1126 << RXQ_RRD_TIMER_SHIFT);
1127 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
1128
1129 /* Flow Control */
1130 switch (hw->dev_rev) {
1131 case 0x8001:
1132 case 0x9001:
1133 case 0x9002:
1134 case 0x9003:
1135 set_flow_ctrl_old(adapter);
1136 break;
1137 default:
1138 set_flow_ctrl_new(hw);
1139 break;
1140 }
1141
1142 /* config TXQ */
1143 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1144 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
1145 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1146 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
1147 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1148 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE | TXQ_CTRL_EN;
1149 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
1150
1151 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1152 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1153 << TX_JUMBO_TASK_TH_SHIFT) |
1154 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1155 << TX_TPD_MIN_IPG_SHIFT);
1156 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
1157
1158 /* config RXQ */
1159 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1160 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
1161 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1162 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
1163 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1164 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) |
1165 RXQ_CTRL_CUT_THRU_EN | RXQ_CTRL_EN;
1166 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
1167
1168 /* config DMA Engine */
1169 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1170 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
1171 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1172 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
1173 DMA_CTRL_DMAR_EN | DMA_CTRL_DMAW_EN;
1174 value |= (u32) hw->dma_ord;
1175 if (atl1_rcb_128 == hw->rcb_value)
1176 value |= DMA_CTRL_RCB_VALUE;
1177 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
1178
1179 /* config CMB / SMB */
1180 value = hw->cmb_rrd | ((u32) hw->cmb_tpd << 16);
1181 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1182 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1183 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1184 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
1185
1186 /* --- enable CMB / SMB */
1187 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1188 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
1189
1190 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1191 if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1192 value = 1; /* config failed */
1193 else
1194 value = 0;
1195
1196 /* clear all interrupt status */
1197 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1198 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1199 return value;
1200}
1201
1202/*
1203 * atl1_irq_disable - Mask off interrupt generation on the NIC
1204 * @adapter: board private structure
1205 */
1206static void atl1_irq_disable(struct atl1_adapter *adapter)
1207{
1208 atomic_inc(&adapter->irq_sem);
1209 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
1210 ioread32(adapter->hw.hw_addr + REG_IMR);
1211 synchronize_irq(adapter->pdev->irq);
1212}
1213
1214static void atl1_vlan_rx_register(struct net_device *netdev,
1215 struct vlan_group *grp)
1216{
1217 struct atl1_adapter *adapter = netdev_priv(netdev);
1218 unsigned long flags;
1219 u32 ctrl;
1220
1221 spin_lock_irqsave(&adapter->lock, flags);
1222 /* atl1_irq_disable(adapter); */
1223 adapter->vlgrp = grp;
1224
1225 if (grp) {
1226 /* enable VLAN tag insert/strip */
1227 ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
1228 ctrl |= MAC_CTRL_RMV_VLAN;
1229 iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
1230 } else {
1231 /* disable VLAN tag insert/strip */
1232 ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
1233 ctrl &= ~MAC_CTRL_RMV_VLAN;
1234 iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
1235 }
1236
1237 /* atl1_irq_enable(adapter); */
1238 spin_unlock_irqrestore(&adapter->lock, flags);
1239}
1240
1241/* FIXME: justify or remove -- CHS */
1242static void atl1_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1243{
1244 /* We don't do Vlan filtering */
1245 return;
1246}
1247
1248/* FIXME: this looks wrong too -- CHS */
1249static void atl1_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1250{
1251 struct atl1_adapter *adapter = netdev_priv(netdev);
1252 unsigned long flags;
1253
1254 spin_lock_irqsave(&adapter->lock, flags);
1255 /* atl1_irq_disable(adapter); */
1256 if (adapter->vlgrp)
1257 adapter->vlgrp->vlan_devices[vid] = NULL;
1258 /* atl1_irq_enable(adapter); */
1259 spin_unlock_irqrestore(&adapter->lock, flags);
1260 /* We don't do Vlan filtering */
1261 return;
1262}
1263
1264static void atl1_restore_vlan(struct atl1_adapter *adapter)
1265{
1266 atl1_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1267 if (adapter->vlgrp) {
1268 u16 vid;
1269 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1270 if (!adapter->vlgrp->vlan_devices[vid])
1271 continue;
1272 atl1_vlan_rx_add_vid(adapter->netdev, vid);
1273 }
1274 }
1275}
1276
1277static u16 tpd_avail(struct atl1_tpd_ring *tpd_ring)
1278{
1279 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
1280 u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
1281 return ((next_to_clean >
1282 next_to_use) ? next_to_clean - next_to_use -
1283 1 : tpd_ring->count + next_to_clean - next_to_use - 1);
1284}
1285
1286static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
1287 struct tso_param *tso)
1288{
1289 /* We enter this function holding a spinlock. */
1290 u8 ipofst;
1291 int err;
1292
1293 if (skb_shinfo(skb)->gso_size) {
1294 if (skb_header_cloned(skb)) {
1295 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1296 if (unlikely(err))
1297 return err;
1298 }
1299
1300 if (skb->protocol == ntohs(ETH_P_IP)) {
1301 skb->nh.iph->tot_len = 0;
1302 skb->nh.iph->check = 0;
1303 skb->h.th->check =
1304 ~csum_tcpudp_magic(skb->nh.iph->saddr,
1305 skb->nh.iph->daddr, 0,
1306 IPPROTO_TCP, 0);
1307 ipofst = skb->nh.raw - skb->data;
1308 if (ipofst != ENET_HEADER_SIZE) /* 802.3 frame */
1309 tso->tsopl |= 1 << TSO_PARAM_ETHTYPE_SHIFT;
1310
1311 tso->tsopl |= (skb->nh.iph->ihl &
1312 CSUM_PARAM_IPHL_MASK) << CSUM_PARAM_IPHL_SHIFT;
1313 tso->tsopl |= ((skb->h.th->doff << 2) &
1314 TSO_PARAM_TCPHDRLEN_MASK) << TSO_PARAM_TCPHDRLEN_SHIFT;
1315 tso->tsopl |= (skb_shinfo(skb)->gso_size &
1316 TSO_PARAM_MSS_MASK) << TSO_PARAM_MSS_SHIFT;
1317 tso->tsopl |= 1 << TSO_PARAM_IPCKSUM_SHIFT;
1318 tso->tsopl |= 1 << TSO_PARAM_TCPCKSUM_SHIFT;
1319 tso->tsopl |= 1 << TSO_PARAM_SEGMENT_SHIFT;
1320 return true;
1321 }
1322 }
1323 return false;
1324}
1325
1326static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
1327 struct csum_param *csum)
1328{
1329 u8 css, cso;
1330
1331 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1332 cso = skb->h.raw - skb->data;
1333 css = (skb->h.raw + skb->csum) - skb->data;
1334 if (unlikely(cso & 0x1)) {
1335 printk(KERN_DEBUG "%s: payload offset != even number\n",
1336 atl1_driver_name);
1337 return -1;
1338 }
1339 csum->csumpl |= (cso & CSUM_PARAM_PLOADOFFSET_MASK) <<
1340 CSUM_PARAM_PLOADOFFSET_SHIFT;
1341 csum->csumpl |= (css & CSUM_PARAM_XSUMOFFSET_MASK) <<
1342 CSUM_PARAM_XSUMOFFSET_SHIFT;
1343 csum->csumpl |= 1 << CSUM_PARAM_CUSTOMCKSUM_SHIFT;
1344 return true;
1345 }
1346
1347 return true;
1348}
1349
1350static void atl1_tx_map(struct atl1_adapter *adapter,
1351 struct sk_buff *skb, bool tcp_seg)
1352{
1353 /* We enter this function holding a spinlock. */
1354 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1355 struct atl1_buffer *buffer_info;
1356 struct page *page;
1357 int first_buf_len = skb->len;
1358 unsigned long offset;
1359 unsigned int nr_frags;
1360 unsigned int f;
1361 u16 tpd_next_to_use;
1362 u16 proto_hdr_len;
1363 u16 i, m, len12;
1364
1365 first_buf_len -= skb->data_len;
1366 nr_frags = skb_shinfo(skb)->nr_frags;
1367 tpd_next_to_use = atomic_read(&tpd_ring->next_to_use);
1368 buffer_info = &tpd_ring->buffer_info[tpd_next_to_use];
1369 if (unlikely(buffer_info->skb))
1370 BUG();
1371 buffer_info->skb = NULL; /* put skb in last TPD */
1372
1373 if (tcp_seg) {
1374 /* TSO/GSO */
1375 proto_hdr_len =
1376 ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
1377 buffer_info->length = proto_hdr_len;
1378 page = virt_to_page(skb->data);
1379 offset = (unsigned long)skb->data & ~PAGE_MASK;
1380 buffer_info->dma = pci_map_page(adapter->pdev, page,
1381 offset, proto_hdr_len,
1382 PCI_DMA_TODEVICE);
1383
1384 if (++tpd_next_to_use == tpd_ring->count)
1385 tpd_next_to_use = 0;
1386
1387 if (first_buf_len > proto_hdr_len) {
1388 len12 = first_buf_len - proto_hdr_len;
1389 m = (len12 + MAX_TX_BUF_LEN - 1) / MAX_TX_BUF_LEN;
1390 for (i = 0; i < m; i++) {
1391 buffer_info =
1392 &tpd_ring->buffer_info[tpd_next_to_use];
1393 buffer_info->skb = NULL;
1394 buffer_info->length =
1395 (MAX_TX_BUF_LEN >=
1396 len12) ? MAX_TX_BUF_LEN : len12;
1397 len12 -= buffer_info->length;
1398 page = virt_to_page(skb->data +
1399 (proto_hdr_len +
1400 i * MAX_TX_BUF_LEN));
1401 offset = (unsigned long)(skb->data +
1402 (proto_hdr_len +
1403 i * MAX_TX_BUF_LEN)) &
1404 ~PAGE_MASK;
1405 buffer_info->dma =
1406 pci_map_page(adapter->pdev, page, offset,
1407 buffer_info->length,
1408 PCI_DMA_TODEVICE);
1409 if (++tpd_next_to_use == tpd_ring->count)
1410 tpd_next_to_use = 0;
1411 }
1412 }
1413 } else {
1414 /* not TSO/GSO */
1415 buffer_info->length = first_buf_len;
1416 page = virt_to_page(skb->data);
1417 offset = (unsigned long)skb->data & ~PAGE_MASK;
1418 buffer_info->dma = pci_map_page(adapter->pdev, page,
1419 offset, first_buf_len,
1420 PCI_DMA_TODEVICE);
1421 if (++tpd_next_to_use == tpd_ring->count)
1422 tpd_next_to_use = 0;
1423 }
1424
1425 for (f = 0; f < nr_frags; f++) {
1426 struct skb_frag_struct *frag;
1427 u16 lenf, i, m;
1428
1429 frag = &skb_shinfo(skb)->frags[f];
1430 lenf = frag->size;
1431
1432 m = (lenf + MAX_TX_BUF_LEN - 1) / MAX_TX_BUF_LEN;
1433 for (i = 0; i < m; i++) {
1434 buffer_info = &tpd_ring->buffer_info[tpd_next_to_use];
1435 if (unlikely(buffer_info->skb))
1436 BUG();
1437 buffer_info->skb = NULL;
1438 buffer_info->length =
1439 (lenf > MAX_TX_BUF_LEN) ? MAX_TX_BUF_LEN : lenf;
1440 lenf -= buffer_info->length;
1441 buffer_info->dma =
1442 pci_map_page(adapter->pdev, frag->page,
1443 frag->page_offset + i * MAX_TX_BUF_LEN,
1444 buffer_info->length, PCI_DMA_TODEVICE);
1445
1446 if (++tpd_next_to_use == tpd_ring->count)
1447 tpd_next_to_use = 0;
1448 }
1449 }
1450
1451 /* last tpd's buffer-info */
1452 buffer_info->skb = skb;
1453}
1454
1455static void atl1_tx_queue(struct atl1_adapter *adapter, int count,
1456 union tpd_descr *descr)
1457{
1458 /* We enter this function holding a spinlock. */
1459 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1460 int j;
1461 u32 val;
1462 struct atl1_buffer *buffer_info;
1463 struct tx_packet_desc *tpd;
1464 u16 tpd_next_to_use = atomic_read(&tpd_ring->next_to_use);
1465
1466 for (j = 0; j < count; j++) {
1467 buffer_info = &tpd_ring->buffer_info[tpd_next_to_use];
1468 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, tpd_next_to_use);
1469 tpd->desc.csum.csumpu = descr->csum.csumpu;
1470 tpd->desc.csum.csumpl = descr->csum.csumpl;
1471 tpd->desc.tso.tsopu = descr->tso.tsopu;
1472 tpd->desc.tso.tsopl = descr->tso.tsopl;
1473 tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
1474 tpd->desc.data = descr->data;
1475 tpd->desc.csum.csumpu |= (cpu_to_le16(buffer_info->length) &
1476 CSUM_PARAM_BUFLEN_MASK) << CSUM_PARAM_BUFLEN_SHIFT;
1477
1478 val = (descr->tso.tsopl >> TSO_PARAM_SEGMENT_SHIFT) &
1479 TSO_PARAM_SEGMENT_MASK;
1480 if (val && !j)
1481 tpd->desc.tso.tsopl |= 1 << TSO_PARAM_HDRFLAG_SHIFT;
1482
1483 if (j == (count - 1))
1484 tpd->desc.csum.csumpl |= 1 << CSUM_PARAM_EOP_SHIFT;
1485
1486 if (++tpd_next_to_use == tpd_ring->count)
1487 tpd_next_to_use = 0;
1488 }
1489 /*
1490 * Force memory writes to complete before letting h/w
1491 * know there are new descriptors to fetch. (Only
1492 * applicable for weak-ordered memory model archs,
1493 * such as IA-64).
1494 */
1495 wmb();
1496
1497 atomic_set(&tpd_ring->next_to_use, (int)tpd_next_to_use);
1498}
1499
1500static void atl1_update_mailbox(struct atl1_adapter *adapter)
1501{
1502 unsigned long flags;
1503 u32 tpd_next_to_use;
1504 u32 rfd_next_to_use;
1505 u32 rrd_next_to_clean;
1506 u32 value;
1507
1508 spin_lock_irqsave(&adapter->mb_lock, flags);
1509
1510 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1511 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1512 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
1513
1514 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1515 MB_RFD_PROD_INDX_SHIFT) |
1516 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1517 MB_RRD_CONS_INDX_SHIFT) |
1518 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1519 MB_TPD_PROD_INDX_SHIFT);
1520 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1521
1522 spin_unlock_irqrestore(&adapter->mb_lock, flags);
1523}
1524
1525static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1526{
1527 struct atl1_adapter *adapter = netdev_priv(netdev);
1528 int len = skb->len;
1529 int tso;
1530 int count = 1;
1531 int ret_val;
1532 u32 val;
1533 union tpd_descr param;
1534 u16 frag_size;
1535 u16 vlan_tag;
1536 unsigned long flags;
1537 unsigned int nr_frags = 0;
1538 unsigned int mss = 0;
1539 unsigned int f;
1540 unsigned int proto_hdr_len;
1541
1542 len -= skb->data_len;
1543
1544 if (unlikely(skb->len == 0)) {
1545 dev_kfree_skb_any(skb);
1546 return NETDEV_TX_OK;
1547 }
1548
1549 param.data = 0;
1550 param.tso.tsopu = 0;
1551 param.tso.tsopl = 0;
1552 param.csum.csumpu = 0;
1553 param.csum.csumpl = 0;
1554
1555 /* nr_frags will be nonzero if we're doing scatter/gather (SG) */
1556 nr_frags = skb_shinfo(skb)->nr_frags;
1557 for (f = 0; f < nr_frags; f++) {
1558 frag_size = skb_shinfo(skb)->frags[f].size;
1559 if (frag_size)
1560 count +=
1561 (frag_size + MAX_TX_BUF_LEN - 1) / MAX_TX_BUF_LEN;
1562 }
1563
1564 /* mss will be nonzero if we're doing segment offload (TSO/GSO) */
1565 mss = skb_shinfo(skb)->gso_size;
1566 if (mss) {
1567 if (skb->protocol == ntohs(ETH_P_IP)) {
1568 proto_hdr_len = ((skb->h.raw - skb->data) +
1569 (skb->h.th->doff << 2));
1570 if (unlikely(proto_hdr_len > len)) {
1571 dev_kfree_skb_any(skb);
1572 return NETDEV_TX_OK;
1573 }
1574 /* need additional TPD ? */
1575 if (proto_hdr_len != len)
1576 count += (len - proto_hdr_len +
1577 MAX_TX_BUF_LEN - 1) / MAX_TX_BUF_LEN;
1578 }
1579 }
1580
1581 local_irq_save(flags);
1582 if (!spin_trylock(&adapter->lock)) {
1583 /* Can't get lock - tell upper layer to requeue */
1584 local_irq_restore(flags);
1585 printk(KERN_DEBUG "%s: TX locked\n", atl1_driver_name);
1586 return NETDEV_TX_LOCKED;
1587 }
1588
1589 if (tpd_avail(&adapter->tpd_ring) < count) {
1590 /* not enough descriptors */
1591 netif_stop_queue(netdev);
1592 spin_unlock_irqrestore(&adapter->lock, flags);
1593 printk(KERN_DEBUG "%s: TX busy\n", atl1_driver_name);
1594 return NETDEV_TX_BUSY;
1595 }
1596
1597 param.data = 0;
1598
1599 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
1600 vlan_tag = vlan_tx_tag_get(skb);
1601 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
1602 ((vlan_tag >> 9) & 0x8);
1603 param.csum.csumpl |= 1 << CSUM_PARAM_INSVLAG_SHIFT;
1604 param.csum.csumpu |= (vlan_tag & CSUM_PARAM_VALANTAG_MASK) <<
1605 CSUM_PARAM_VALAN_SHIFT;
1606 }
1607
1608 tso = atl1_tso(adapter, skb, &param.tso);
1609 if (tso < 0) {
1610 spin_unlock_irqrestore(&adapter->lock, flags);
1611 dev_kfree_skb_any(skb);
1612 return NETDEV_TX_OK;
1613 }
1614
1615 if (!tso) {
1616 ret_val = atl1_tx_csum(adapter, skb, &param.csum);
1617 if (ret_val < 0) {
1618 spin_unlock_irqrestore(&adapter->lock, flags);
1619 dev_kfree_skb_any(skb);
1620 return NETDEV_TX_OK;
1621 }
1622 }
1623
1624 val = (param.csum.csumpl >> CSUM_PARAM_SEGMENT_SHIFT) &
1625 CSUM_PARAM_SEGMENT_MASK;
1626 atl1_tx_map(adapter, skb, 1 == val);
1627 atl1_tx_queue(adapter, count, &param);
1628 netdev->trans_start = jiffies;
1629 spin_unlock_irqrestore(&adapter->lock, flags);
1630 atl1_update_mailbox(adapter);
1631 return NETDEV_TX_OK;
1632}
1633
1634/*
1635 * atl1_get_stats - Get System Network Statistics
1636 * @netdev: network interface device structure
1637 *
1638 * Returns the address of the device statistics structure.
1639 * The statistics are actually updated from the timer callback.
1640 */
1641static struct net_device_stats *atl1_get_stats(struct net_device *netdev)
1642{
1643 struct atl1_adapter *adapter = netdev_priv(netdev);
1644 return &adapter->net_stats;
1645}
1646
1647/*
1648 * atl1_clean_rx_ring - Free RFD Buffers
1649 * @adapter: board private structure
1650 */
1651static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
1652{
1653 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1654 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1655 struct atl1_buffer *buffer_info;
1656 struct pci_dev *pdev = adapter->pdev;
1657 unsigned long size;
1658 unsigned int i;
1659
1660 /* Free all the Rx ring sk_buffs */
1661 for (i = 0; i < rfd_ring->count; i++) {
1662 buffer_info = &rfd_ring->buffer_info[i];
1663 if (buffer_info->dma) {
1664 pci_unmap_page(pdev,
1665 buffer_info->dma,
1666 buffer_info->length,
1667 PCI_DMA_FROMDEVICE);
1668 buffer_info->dma = 0;
1669 }
1670 if (buffer_info->skb) {
1671 dev_kfree_skb(buffer_info->skb);
1672 buffer_info->skb = NULL;
1673 }
1674 }
1675
1676 size = sizeof(struct atl1_buffer) * rfd_ring->count;
1677 memset(rfd_ring->buffer_info, 0, size);
1678
1679 /* Zero out the descriptor ring */
1680 memset(rfd_ring->desc, 0, rfd_ring->size);
1681
1682 rfd_ring->next_to_clean = 0;
1683 atomic_set(&rfd_ring->next_to_use, 0);
1684
1685 rrd_ring->next_to_use = 0;
1686 atomic_set(&rrd_ring->next_to_clean, 0);
1687}
1688
1689/*
1690 * atl1_clean_tx_ring - Free Tx Buffers
1691 * @adapter: board private structure
1692 */
1693static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
1694{
1695 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1696 struct atl1_buffer *buffer_info;
1697 struct pci_dev *pdev = adapter->pdev;
1698 unsigned long size;
1699 unsigned int i;
1700
1701 /* Free all the Tx ring sk_buffs */
1702 for (i = 0; i < tpd_ring->count; i++) {
1703 buffer_info = &tpd_ring->buffer_info[i];
1704 if (buffer_info->dma) {
1705 pci_unmap_page(pdev, buffer_info->dma,
1706 buffer_info->length, PCI_DMA_TODEVICE);
1707 buffer_info->dma = 0;
1708 }
1709 }
1710
1711 for (i = 0; i < tpd_ring->count; i++) {
1712 buffer_info = &tpd_ring->buffer_info[i];
1713 if (buffer_info->skb) {
1714 dev_kfree_skb_any(buffer_info->skb);
1715 buffer_info->skb = NULL;
1716 }
1717 }
1718
1719 size = sizeof(struct atl1_buffer) * tpd_ring->count;
1720 memset(tpd_ring->buffer_info, 0, size);
1721
1722 /* Zero out the descriptor ring */
1723 memset(tpd_ring->desc, 0, tpd_ring->size);
1724
1725 atomic_set(&tpd_ring->next_to_use, 0);
1726 atomic_set(&tpd_ring->next_to_clean, 0);
1727}
1728
1729/*
1730 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1731 * @adapter: board private structure
1732 *
1733 * Free all transmit software resources
1734 */
1735void atl1_free_ring_resources(struct atl1_adapter *adapter)
1736{
1737 struct pci_dev *pdev = adapter->pdev;
1738 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1739 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1740 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1741 struct atl1_ring_header *ring_header = &adapter->ring_header;
1742
1743 atl1_clean_tx_ring(adapter);
1744 atl1_clean_rx_ring(adapter);
1745
1746 kfree(tpd_ring->buffer_info);
1747 pci_free_consistent(pdev, ring_header->size, ring_header->desc,
1748 ring_header->dma);
1749
1750 tpd_ring->buffer_info = NULL;
1751 tpd_ring->desc = NULL;
1752 tpd_ring->dma = 0;
1753
1754 rfd_ring->buffer_info = NULL;
1755 rfd_ring->desc = NULL;
1756 rfd_ring->dma = 0;
1757
1758 rrd_ring->desc = NULL;
1759 rrd_ring->dma = 0;
1760}
1761
1762s32 atl1_up(struct atl1_adapter *adapter)
1763{
1764 struct net_device *netdev = adapter->netdev;
1765 int err;
1766 int irq_flags = IRQF_SAMPLE_RANDOM;
1767
1768 /* hardware has been reset, we need to reload some things */
1769 atl1_set_multi(netdev);
1770 atl1_restore_vlan(adapter);
1771 err = atl1_alloc_rx_buffers(adapter);
1772 if (unlikely(!err)) /* no RX BUFFER allocated */
1773 return -ENOMEM;
1774
1775 if (unlikely(atl1_configure(adapter))) {
1776 err = -EIO;
1777 goto err_up;
1778 }
1779
1780 err = pci_enable_msi(adapter->pdev);
1781 if (err) {
1782 dev_info(&adapter->pdev->dev,
1783 "Unable to enable MSI: %d\n", err);
1784 irq_flags |= IRQF_SHARED;
1785 }
1786
1787 err = request_irq(adapter->pdev->irq, &atl1_intr, irq_flags,
1788 netdev->name, netdev);
1789 if (unlikely(err))
1790 goto err_up;
1791
1792 mod_timer(&adapter->watchdog_timer, jiffies);
1793 atl1_irq_enable(adapter);
1794 atl1_check_link(adapter);
1795 return 0;
1796
1797 /* FIXME: unreachable code! -- CHS */
1798 /* free irq disable any interrupt */
1799 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
1800 free_irq(adapter->pdev->irq, netdev);
1801
1802err_up:
1803 pci_disable_msi(adapter->pdev);
1804 /* free rx_buffers */
1805 atl1_clean_rx_ring(adapter);
1806 return err;
1807}
1808
1809void atl1_down(struct atl1_adapter *adapter)
1810{
1811 struct net_device *netdev = adapter->netdev;
1812
1813 del_timer_sync(&adapter->watchdog_timer);
1814 del_timer_sync(&adapter->phy_config_timer);
1815 adapter->phy_timer_pending = false;
1816
1817 atl1_irq_disable(adapter);
1818 free_irq(adapter->pdev->irq, netdev);
1819 pci_disable_msi(adapter->pdev);
1820 atl1_reset_hw(&adapter->hw);
1821 adapter->cmb.cmb->int_stats = 0;
1822
1823 adapter->link_speed = SPEED_0;
1824 adapter->link_duplex = -1;
1825 netif_carrier_off(netdev);
1826 netif_stop_queue(netdev);
1827
1828 atl1_clean_tx_ring(adapter);
1829 atl1_clean_rx_ring(adapter);
1830}
1831
1832/*
1833 * atl1_change_mtu - Change the Maximum Transfer Unit
1834 * @netdev: network interface device structure
1835 * @new_mtu: new value for maximum frame size
1836 *
1837 * Returns 0 on success, negative on failure
1838 */
1839static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
1840{
1841 struct atl1_adapter *adapter = netdev_priv(netdev);
1842 int old_mtu = netdev->mtu;
1843 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
1844
1845 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
1846 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
1847 printk(KERN_WARNING "%s: invalid MTU setting\n",
1848 atl1_driver_name);
1849 return -EINVAL;
1850 }
1851
1852 adapter->hw.max_frame_size = max_frame;
1853 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
1854 adapter->rx_buffer_len = (max_frame + 7) & ~7;
1855 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
1856
1857 netdev->mtu = new_mtu;
1858 if ((old_mtu != new_mtu) && netif_running(netdev)) {
1859 atl1_down(adapter);
1860 atl1_up(adapter);
1861 }
1862
1863 return 0;
1864}
1865
1866/*
1867 * atl1_set_mac - Change the Ethernet Address of the NIC
1868 * @netdev: network interface device structure
1869 * @p: pointer to an address structure
1870 *
1871 * Returns 0 on success, negative on failure
1872 */
1873static int atl1_set_mac(struct net_device *netdev, void *p)
1874{
1875 struct atl1_adapter *adapter = netdev_priv(netdev);
1876 struct sockaddr *addr = p;
1877
1878 if (netif_running(netdev))
1879 return -EBUSY;
1880
1881 if (!is_valid_ether_addr(addr->sa_data))
1882 return -EADDRNOTAVAIL;
1883
1884 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1885 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
1886
1887 atl1_set_mac_addr(&adapter->hw);
1888 return 0;
1889}
1890
1891/*
1892 * atl1_watchdog - Timer Call-back
1893 * @data: pointer to netdev cast into an unsigned long
1894 */
1895static void atl1_watchdog(unsigned long data)
1896{
1897 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
1898
1899 /* Reset the timer */
1900 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
1901}
1902
1903static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
1904{
1905 struct atl1_adapter *adapter = netdev_priv(netdev);
1906 u16 result;
1907
1908 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
1909
1910 return result;
1911}
1912
1913static void mdio_write(struct net_device *netdev, int phy_id, int reg_num, int val)
1914{
1915 struct atl1_adapter *adapter = netdev_priv(netdev);
1916
1917 atl1_write_phy_reg(&adapter->hw, reg_num, val);
1918}
1919
1920/*
1921 * atl1_mii_ioctl -
1922 * @netdev:
1923 * @ifreq:
1924 * @cmd:
1925 */
1926static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1927{
1928 struct atl1_adapter *adapter = netdev_priv(netdev);
1929 unsigned long flags;
1930 int retval;
1931
1932 if (!netif_running(netdev))
1933 return -EINVAL;
1934
1935 spin_lock_irqsave(&adapter->lock, flags);
1936 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
1937 spin_unlock_irqrestore(&adapter->lock, flags);
1938
1939 return retval;
1940}
1941
1942/*
1943 * atl1_ioctl -
1944 * @netdev:
1945 * @ifreq:
1946 * @cmd:
1947 */
1948static int atl1_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1949{
1950 switch (cmd) {
1951 case SIOCGMIIPHY:
1952 case SIOCGMIIREG:
1953 case SIOCSMIIREG:
1954 return atl1_mii_ioctl(netdev, ifr, cmd);
1955 default:
1956 return -EOPNOTSUPP;
1957 }
1958}
1959
1960/*
1961 * atl1_tx_timeout - Respond to a Tx Hang
1962 * @netdev: network interface device structure
1963 */
1964static void atl1_tx_timeout(struct net_device *netdev)
1965{
1966 struct atl1_adapter *adapter = netdev_priv(netdev);
1967 /* Do the reset outside of interrupt context */
1968 schedule_work(&adapter->tx_timeout_task);
1969}
1970
1971/*
1972 * atl1_phy_config - Timer Call-back
1973 * @data: pointer to netdev cast into an unsigned long
1974 */
1975static void atl1_phy_config(unsigned long data)
1976{
1977 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
1978 struct atl1_hw *hw = &adapter->hw;
1979 unsigned long flags;
1980
1981 spin_lock_irqsave(&adapter->lock, flags);
1982 adapter->phy_timer_pending = false;
1983 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1984 atl1_write_phy_reg(hw, MII_AT001_CR, hw->mii_1000t_ctrl_reg);
1985 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
1986 spin_unlock_irqrestore(&adapter->lock, flags);
1987}
1988
1989int atl1_reset(struct atl1_adapter *adapter)
1990{
1991 int ret;
1992
1993 ret = atl1_reset_hw(&adapter->hw);
1994 if (ret != ATL1_SUCCESS)
1995 return ret;
1996 return atl1_init_hw(&adapter->hw);
1997}
1998
1999/*
2000 * atl1_open - Called when a network interface is made active
2001 * @netdev: network interface device structure
2002 *
2003 * Returns 0 on success, negative value on failure
2004 *
2005 * The open entry point is called when a network interface is made
2006 * active by the system (IFF_UP). At this point all resources needed
2007 * for transmit and receive operations are allocated, the interrupt
2008 * handler is registered with the OS, the watchdog timer is started,
2009 * and the stack is notified that the interface is ready.
2010 */
2011static int atl1_open(struct net_device *netdev)
2012{
2013 struct atl1_adapter *adapter = netdev_priv(netdev);
2014 int err;
2015
2016 /* allocate transmit descriptors */
2017 err = atl1_setup_ring_resources(adapter);
2018 if (err)
2019 return err;
2020
2021 err = atl1_up(adapter);
2022 if (err)
2023 goto err_up;
2024
2025 return 0;
2026
2027err_up:
2028 atl1_reset(adapter);
2029 return err;
2030}
2031
2032/*
2033 * atl1_close - Disables a network interface
2034 * @netdev: network interface device structure
2035 *
2036 * Returns 0, this is not allowed to fail
2037 *
2038 * The close entry point is called when an interface is de-activated
2039 * by the OS. The hardware is still under the drivers control, but
2040 * needs to be disabled. A global MAC reset is issued to stop the
2041 * hardware, and all transmit and receive resources are freed.
2042 */
2043static int atl1_close(struct net_device *netdev)
2044{
2045 struct atl1_adapter *adapter = netdev_priv(netdev);
2046 atl1_down(adapter);
2047 atl1_free_ring_resources(adapter);
2048 return 0;
2049}
2050
2051/*
2052 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
2053 * will assert. We do soft reset <0x1400=1> according
2054 * with the SPEC. BUT, it seemes that PCIE or DMA
2055 * state-machine will not be reset. DMAR_TO_INT will
2056 * assert again and again.
2057 */
2058static void atl1_tx_timeout_task(struct work_struct *work)
2059{
2060 struct atl1_adapter *adapter =
2061 container_of(work, struct atl1_adapter, tx_timeout_task);
2062 struct net_device *netdev = adapter->netdev;
2063
2064 netif_device_detach(netdev);
2065 atl1_down(adapter);
2066 atl1_up(adapter);
2067 netif_device_attach(netdev);
2068}
2069
2070/*
2071 * atl1_link_chg_task - deal with link change event Out of interrupt context
2072 */
2073static void atl1_link_chg_task(struct work_struct *work)
2074{
2075 struct atl1_adapter *adapter =
2076 container_of(work, struct atl1_adapter, link_chg_task);
2077 unsigned long flags;
2078
2079 spin_lock_irqsave(&adapter->lock, flags);
2080 atl1_check_link(adapter);
2081 spin_unlock_irqrestore(&adapter->lock, flags);
2082}
2083
2084/*
2085 * atl1_pcie_patch - Patch for PCIE module
2086 */
2087static void atl1_pcie_patch(struct atl1_adapter *adapter)
2088{
2089 u32 value;
2090 value = 0x6500;
2091 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
2092 /* pcie flow control mode change */
2093 value = ioread32(adapter->hw.hw_addr + 0x1008);
2094 value |= 0x8000;
2095 iowrite32(value, adapter->hw.hw_addr + 0x1008);
2096}
2097
2098/*
2099 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
2100 * on PCI Command register is disable.
2101 * The function enable this bit.
2102 * Brackett, 2006/03/15
2103 */
2104static void atl1_via_workaround(struct atl1_adapter *adapter)
2105{
2106 unsigned long value;
2107
2108 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
2109 if (value & PCI_COMMAND_INTX_DISABLE)
2110 value &= ~PCI_COMMAND_INTX_DISABLE;
2111 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
2112}
2113
2114/*
2115 * atl1_probe - Device Initialization Routine
2116 * @pdev: PCI device information struct
2117 * @ent: entry in atl1_pci_tbl
2118 *
2119 * Returns 0 on success, negative on failure
2120 *
2121 * atl1_probe initializes an adapter identified by a pci_dev structure.
2122 * The OS initialization, configuring of the adapter private structure,
2123 * and a hardware reset occur.
2124 */
2125static int __devinit atl1_probe(struct pci_dev *pdev,
2126 const struct pci_device_id *ent)
2127{
2128 struct net_device *netdev;
2129 struct atl1_adapter *adapter;
2130 static int cards_found = 0;
2131 bool pci_using_64 = true;
2132 int err;
2133
2134 err = pci_enable_device(pdev);
2135 if (err)
2136 return err;
2137
2138 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2139 if (err) {
2140 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2141 if (err) {
2142 printk(KERN_DEBUG
2143 "%s: no usable DMA configuration, aborting\n",
2144 atl1_driver_name);
2145 goto err_dma;
2146 }
2147 pci_using_64 = false;
2148 }
2149 /* Mark all PCI regions associated with PCI device
2150 * pdev as being reserved by owner atl1_driver_name
2151 */
2152 err = pci_request_regions(pdev, atl1_driver_name);
2153 if (err)
2154 goto err_request_regions;
2155
2156 /* Enables bus-mastering on the device and calls
2157 * pcibios_set_master to do the needed arch specific settings
2158 */
2159 pci_set_master(pdev);
2160
2161 netdev = alloc_etherdev(sizeof(struct atl1_adapter));
2162 if (!netdev) {
2163 err = -ENOMEM;
2164 goto err_alloc_etherdev;
2165 }
2166 SET_MODULE_OWNER(netdev);
2167 SET_NETDEV_DEV(netdev, &pdev->dev);
2168
2169 pci_set_drvdata(pdev, netdev);
2170 adapter = netdev_priv(netdev);
2171 adapter->netdev = netdev;
2172 adapter->pdev = pdev;
2173 adapter->hw.back = adapter;
2174
2175 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2176 if (!adapter->hw.hw_addr) {
2177 err = -EIO;
2178 goto err_pci_iomap;
2179 }
2180 /* get device revision number */
2181 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr + (REG_MASTER_CTRL + 2));
2182
2183 /* set default ring resource counts */
2184 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
2185 adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
2186
2187 adapter->mii.dev = netdev;
2188 adapter->mii.mdio_read = mdio_read;
2189 adapter->mii.mdio_write = mdio_write;
2190 adapter->mii.phy_id_mask = 0x1f;
2191 adapter->mii.reg_num_mask = 0x1f;
2192
2193 netdev->open = &atl1_open;
2194 netdev->stop = &atl1_close;
2195 netdev->hard_start_xmit = &atl1_xmit_frame;
2196 netdev->get_stats = &atl1_get_stats;
2197 netdev->set_multicast_list = &atl1_set_multi;
2198 netdev->set_mac_address = &atl1_set_mac;
2199 netdev->change_mtu = &atl1_change_mtu;
2200 netdev->do_ioctl = &atl1_ioctl;
2201 netdev->tx_timeout = &atl1_tx_timeout;
2202 netdev->watchdog_timeo = 5 * HZ;
2203 netdev->vlan_rx_register = atl1_vlan_rx_register;
2204 netdev->vlan_rx_add_vid = atl1_vlan_rx_add_vid;
2205 netdev->vlan_rx_kill_vid = atl1_vlan_rx_kill_vid;
2206 netdev->ethtool_ops = &atl1_ethtool_ops;
2207 adapter->bd_number = cards_found;
2208 adapter->pci_using_64 = pci_using_64;
2209
2210 /* setup the private structure */
2211 err = atl1_sw_init(adapter);
2212 if (err)
2213 goto err_common;
2214
2215 netdev->features = NETIF_F_HW_CSUM;
2216 netdev->features |= NETIF_F_SG;
2217 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
2218
2219 /*
2220 * FIXME - Until tso performance gets fixed, disable the feature.
2221 * Enable it with ethtool -K if desired.
2222 */
2223 /* netdev->features |= NETIF_F_TSO; */
2224
2225 if (pci_using_64)
2226 netdev->features |= NETIF_F_HIGHDMA;
2227
2228 netdev->features |= NETIF_F_LLTX;
2229
2230 /*
2231 * patch for some L1 of old version,
2232 * the final version of L1 may not need these
2233 * patches
2234 */
2235 /* atl1_pcie_patch(adapter); */
2236
2237 /* really reset GPHY core */
2238 iowrite16(0, adapter->hw.hw_addr + REG_GPHY_ENABLE);
2239
2240 /*
2241 * reset the controller to
2242 * put the device in a known good starting state
2243 */
2244 if (atl1_reset_hw(&adapter->hw)) {
2245 err = -EIO;
2246 goto err_common;
2247 }
2248
2249 /* copy the MAC address out of the EEPROM */
2250 atl1_read_mac_addr(&adapter->hw);
2251 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2252
2253 if (!is_valid_ether_addr(netdev->dev_addr)) {
2254 err = -EIO;
2255 goto err_common;
2256 }
2257
2258 atl1_check_options(adapter);
2259
2260 /* pre-init the MAC, and setup link */
2261 err = atl1_init_hw(&adapter->hw);
2262 if (err) {
2263 err = -EIO;
2264 goto err_common;
2265 }
2266
2267 atl1_pcie_patch(adapter);
2268 /* assume we have no link for now */
2269 netif_carrier_off(netdev);
2270 netif_stop_queue(netdev);
2271
2272 init_timer(&adapter->watchdog_timer);
2273 adapter->watchdog_timer.function = &atl1_watchdog;
2274 adapter->watchdog_timer.data = (unsigned long)adapter;
2275
2276 init_timer(&adapter->phy_config_timer);
2277 adapter->phy_config_timer.function = &atl1_phy_config;
2278 adapter->phy_config_timer.data = (unsigned long)adapter;
2279 adapter->phy_timer_pending = false;
2280
2281 INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
2282
2283 INIT_WORK(&adapter->link_chg_task, atl1_link_chg_task);
2284
2285 INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
2286
2287 err = register_netdev(netdev);
2288 if (err)
2289 goto err_common;
2290
2291 cards_found++;
2292 atl1_via_workaround(adapter);
2293 return 0;
2294
2295err_common:
2296 pci_iounmap(pdev, adapter->hw.hw_addr);
2297err_pci_iomap:
2298 free_netdev(netdev);
2299err_alloc_etherdev:
2300 pci_release_regions(pdev);
2301err_dma:
2302err_request_regions:
2303 pci_disable_device(pdev);
2304 return err;
2305}
2306
2307/*
2308 * atl1_remove - Device Removal Routine
2309 * @pdev: PCI device information struct
2310 *
2311 * atl1_remove is called by the PCI subsystem to alert the driver
2312 * that it should release a PCI device. The could be caused by a
2313 * Hot-Plug event, or because the driver is going to be removed from
2314 * memory.
2315 */
2316static void __devexit atl1_remove(struct pci_dev *pdev)
2317{
2318 struct net_device *netdev = pci_get_drvdata(pdev);
2319 struct atl1_adapter *adapter;
2320 /* Device not available. Return. */
2321 if (!netdev)
2322 return;
2323
2324 adapter = netdev_priv(netdev);
2325 iowrite16(0, adapter->hw.hw_addr + REG_GPHY_ENABLE);
2326 unregister_netdev(netdev);
2327 pci_iounmap(pdev, adapter->hw.hw_addr);
2328 pci_release_regions(pdev);
2329 free_netdev(netdev);
2330 pci_disable_device(pdev);
2331}
2332
2333#ifdef CONFIG_PM
2334static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
2335{
2336 struct net_device *netdev = pci_get_drvdata(pdev);
2337 struct atl1_adapter *adapter = netdev_priv(netdev);
2338 struct atl1_hw *hw = &adapter->hw;
2339 u32 ctrl = 0;
2340 u32 wufc = adapter->wol;
2341
2342 netif_device_detach(netdev);
2343 if (netif_running(netdev))
2344 atl1_down(adapter);
2345
2346 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2347 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2348 if (ctrl & BMSR_LSTATUS)
2349 wufc &= ~ATL1_WUFC_LNKC;
2350
2351 /* reduce speed to 10/100M */
2352 if (wufc) {
2353 atl1_phy_enter_power_saving(hw);
2354 /* if resume, let driver to re- setup link */
2355 hw->phy_configured = false;
2356 atl1_set_mac_addr(hw);
2357 atl1_set_multi(netdev);
2358
2359 ctrl = 0;
2360 /* turn on magic packet wol */
2361 if (wufc & ATL1_WUFC_MAG)
2362 ctrl = WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
2363
2364 /* turn on Link change WOL */
2365 if (wufc & ATL1_WUFC_LNKC)
2366 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2367 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2368
2369 /* turn on all-multi mode if wake on multicast is enabled */
2370 ctrl = ioread32(hw->hw_addr + REG_MAC_CTRL);
2371 ctrl &= ~MAC_CTRL_DBG;
2372 ctrl &= ~MAC_CTRL_PROMIS_EN;
2373 if (wufc & ATL1_WUFC_MC)
2374 ctrl |= MAC_CTRL_MC_ALL_EN;
2375 else
2376 ctrl &= ~MAC_CTRL_MC_ALL_EN;
2377
2378 /* turn on broadcast mode if wake on-BC is enabled */
2379 if (wufc & ATL1_WUFC_BC)
2380 ctrl |= MAC_CTRL_BC_EN;
2381 else
2382 ctrl &= ~MAC_CTRL_BC_EN;
2383
2384 /* enable RX */
2385 ctrl |= MAC_CTRL_RX_EN;
2386 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
2387 pci_enable_wake(pdev, PCI_D3hot, 1);
2388 pci_enable_wake(pdev, PCI_D3cold, 1); /* 4 == D3 cold */
2389 } else {
2390 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2391 pci_enable_wake(pdev, PCI_D3hot, 0);
2392 pci_enable_wake(pdev, PCI_D3cold, 0); /* 4 == D3 cold */
2393 }
2394
2395 pci_save_state(pdev);
2396 pci_disable_device(pdev);
2397
2398 pci_set_power_state(pdev, PCI_D3hot);
2399
2400 return 0;
2401}
2402
2403static int atl1_resume(struct pci_dev *pdev)
2404{
2405 struct net_device *netdev = pci_get_drvdata(pdev);
2406 struct atl1_adapter *adapter = netdev_priv(netdev);
2407 u32 ret_val;
2408
2409 pci_set_power_state(pdev, 0);
2410 pci_restore_state(pdev);
2411
2412 ret_val = pci_enable_device(pdev);
2413 pci_enable_wake(pdev, PCI_D3hot, 0);
2414 pci_enable_wake(pdev, PCI_D3cold, 0);
2415
2416 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
2417 atl1_reset(adapter);
2418
2419 if (netif_running(netdev))
2420 atl1_up(adapter);
2421 netif_device_attach(netdev);
2422
2423 atl1_via_workaround(adapter);
2424
2425 return 0;
2426}
2427#else
2428#define atl1_suspend NULL
2429#define atl1_resume NULL
2430#endif
2431
2432static struct pci_driver atl1_driver = {
2433 .name = atl1_driver_name,
2434 .id_table = atl1_pci_tbl,
2435 .probe = atl1_probe,
2436 .remove = __devexit_p(atl1_remove),
2437 /* Power Managment Hooks */
2438 /* probably broken right now -- CHS */
2439 .suspend = atl1_suspend,
2440 .resume = atl1_resume
2441};
2442
2443/*
2444 * atl1_exit_module - Driver Exit Cleanup Routine
2445 *
2446 * atl1_exit_module is called just before the driver is removed
2447 * from memory.
2448 */
2449static void __exit atl1_exit_module(void)
2450{
2451 pci_unregister_driver(&atl1_driver);
2452}
2453
2454/*
2455 * atl1_init_module - Driver Registration Routine
2456 *
2457 * atl1_init_module is the first routine called when the driver is
2458 * loaded. All it does is register with the PCI subsystem.
2459 */
2460static int __init atl1_init_module(void)
2461{
2462 printk(KERN_INFO "%s - version %s\n", atl1_driver_string, DRIVER_VERSION);
2463 printk(KERN_INFO "%s\n", atl1_copyright);
2464 return pci_register_driver(&atl1_driver);
2465}
2466
2467module_init(atl1_init_module);
2468module_exit(atl1_exit_module);
diff --git a/drivers/net/atl1/atl1_param.c b/drivers/net/atl1/atl1_param.c
new file mode 100644
index 000000000000..c407214339f6
--- /dev/null
+++ b/drivers/net/atl1/atl1_param.c
@@ -0,0 +1,206 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#include <linux/types.h>
25#include <linux/pci.h>
26#include <linux/moduleparam.h>
27#include "atl1.h"
28
29/*
30 * This is the only thing that needs to be changed to adjust the
31 * maximum number of ports that the driver can manage.
32 */
33#define ATL1_MAX_NIC 4
34
35#define OPTION_UNSET -1
36#define OPTION_DISABLED 0
37#define OPTION_ENABLED 1
38
39#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
40
41/*
42 * Interrupt Moderate Timer in units of 2 us
43 *
44 * Valid Range: 10-65535
45 *
46 * Default Value: 100 (200us)
47 */
48static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
49static int num_int_mod_timer = 0;
50module_param_array_named(int_mod_timer, int_mod_timer, int, &num_int_mod_timer, 0);
51MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
52
53/*
54 * flash_vendor
55 *
56 * Valid Range: 0-2
57 *
58 * 0 - Atmel
59 * 1 - SST
60 * 2 - ST
61 *
62 * Default Value: 0
63 */
64static int __devinitdata flash_vendor[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
65static int num_flash_vendor = 0;
66module_param_array_named(flash_vendor, flash_vendor, int, &num_flash_vendor, 0);
67MODULE_PARM_DESC(flash_vendor, "SPI flash vendor");
68
69#define DEFAULT_INT_MOD_CNT 100 /* 200us */
70#define MAX_INT_MOD_CNT 65000
71#define MIN_INT_MOD_CNT 50
72
73#define FLASH_VENDOR_DEFAULT 0
74#define FLASH_VENDOR_MIN 0
75#define FLASH_VENDOR_MAX 2
76
77struct atl1_option {
78 enum { enable_option, range_option, list_option } type;
79 char *name;
80 char *err;
81 int def;
82 union {
83 struct { /* range_option info */
84 int min;
85 int max;
86 } r;
87 struct { /* list_option info */
88 int nr;
89 struct atl1_opt_list {
90 int i;
91 char *str;
92 } *p;
93 } l;
94 } arg;
95};
96
97static int __devinit atl1_validate_option(int *value, struct atl1_option *opt)
98{
99 if (*value == OPTION_UNSET) {
100 *value = opt->def;
101 return 0;
102 }
103
104 switch (opt->type) {
105 case enable_option:
106 switch (*value) {
107 case OPTION_ENABLED:
108 printk(KERN_INFO "%s: %s Enabled\n", atl1_driver_name,
109 opt->name);
110 return 0;
111 case OPTION_DISABLED:
112 printk(KERN_INFO "%s: %s Disabled\n", atl1_driver_name,
113 opt->name);
114 return 0;
115 }
116 break;
117 case range_option:
118 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
119 printk(KERN_INFO "%s: %s set to %i\n",
120 atl1_driver_name, opt->name, *value);
121 return 0;
122 }
123 break;
124 case list_option:{
125 int i;
126 struct atl1_opt_list *ent;
127
128 for (i = 0; i < opt->arg.l.nr; i++) {
129 ent = &opt->arg.l.p[i];
130 if (*value == ent->i) {
131 if (ent->str[0] != '\0')
132 printk(KERN_INFO "%s: %s\n",
133 atl1_driver_name, ent->str);
134 return 0;
135 }
136 }
137 }
138 break;
139
140 default:
141 break;
142 }
143
144 printk(KERN_INFO "%s: invalid %s specified (%i) %s\n",
145 atl1_driver_name, opt->name, *value, opt->err);
146 *value = opt->def;
147 return -1;
148}
149
150/*
151 * atl1_check_options - Range Checking for Command Line Parameters
152 * @adapter: board private structure
153 *
154 * This routine checks all command line parameters for valid user
155 * input. If an invalid value is given, or if no user specified
156 * value exists, a default value is used. The final value is stored
157 * in a variable in the adapter structure.
158 */
159void __devinit atl1_check_options(struct atl1_adapter *adapter)
160{
161 int bd = adapter->bd_number;
162 if (bd >= ATL1_MAX_NIC) {
163 printk(KERN_NOTICE "%s: warning: no configuration for board #%i\n",
164 atl1_driver_name, bd);
165 printk(KERN_NOTICE "%s: using defaults for all values\n",
166 atl1_driver_name);
167 }
168 { /* Interrupt Moderate Timer */
169 struct atl1_option opt = {
170 .type = range_option,
171 .name = "Interrupt Moderator Timer",
172 .err = "using default of "
173 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
174 .def = DEFAULT_INT_MOD_CNT,
175 .arg = {.r =
176 {.min = MIN_INT_MOD_CNT,.max = MAX_INT_MOD_CNT}}
177 };
178 int val;
179 if (num_int_mod_timer > bd) {
180 val = int_mod_timer[bd];
181 atl1_validate_option(&val, &opt);
182 adapter->imt = (u16) val;
183 } else
184 adapter->imt = (u16) (opt.def);
185 }
186
187 { /* Flash Vendor */
188 struct atl1_option opt = {
189 .type = range_option,
190 .name = "SPI Flash Vendor",
191 .err = "using default of "
192 __MODULE_STRING(FLASH_VENDOR_DEFAULT),
193 .def = DEFAULT_INT_MOD_CNT,
194 .arg = {.r =
195 {.min = FLASH_VENDOR_MIN,.max =
196 FLASH_VENDOR_MAX}}
197 };
198 int val;
199 if (num_flash_vendor > bd) {
200 val = flash_vendor[bd];
201 atl1_validate_option(&val, &opt);
202 adapter->hw.flash_vendor = (u8) val;
203 } else
204 adapter->hw.flash_vendor = (u8) (opt.def);
205 }
206}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 21:06:16 -0500