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authorLinus Torvalds <torvalds@linux-foundation.org>2014-08-07 11:47:00 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-08-07 11:47:00 -0400
commite669830526a0abaf301bf408df69cde33901ac63 (patch)
tree0b6043375006d1754bbd1ab2370b0a0536546cc9 /drivers/mtd
parentebb067d2f4e2db59b076f9c9cba0375a8ad1e07c (diff)
parent475d5928b79bb78326a645863d46ff95c5e25e5a (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "This is the main pull request for 3.17. It contains: - misc Cavium Octeon, BCM47xx, BCM63xx and Alchemy updates - MIPS ptrace updates and cleanups - various fixes that will also go to -stable - a number of cleanups and small non-critical fixes. - NUMA support for the Loongson 3. - more support for MSA - support for MAAR - various FP enhancements and fixes" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) MIPS: jz4740: remove unnecessary null test before debugfs_remove MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursive MIPS: ZBOOT: implement stack protector in compressed boot phase MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT MIPS: Bonito64: remove a duplicate define MIPS: Malta: initialise MAARs MIPS: Initialise MAARs MIPS: detect presence of MAARs MIPS: define MAAR register accessors & bits MIPS: mark MSA experimental MIPS: Don't build MSA support unless it can be used MIPS: consistently clear MSA flags when starting & copying threads MIPS: 16 byte align MSA vector context MIPS: disable preemption whilst initialising MSA MIPS: ensure MSA gets disabled during boot MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains MIPS: fix MSA context for tasks which don't use FP first MIPS: init upper 64b of vector registers when MSA is first used MIPS: save/disable MSA in lose_fpu MIPS: preserve scalar FP CSR when switching vector context ...
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/au1550nd.c29
1 files changed, 13 insertions, 16 deletions
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index bc5c518828d2..77d6c17b38c2 100644
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -41,7 +41,7 @@ static u_char au_read_byte(struct mtd_info *mtd)
41{ 41{
42 struct nand_chip *this = mtd->priv; 42 struct nand_chip *this = mtd->priv;
43 u_char ret = readb(this->IO_ADDR_R); 43 u_char ret = readb(this->IO_ADDR_R);
44 au_sync(); 44 wmb(); /* drain writebuffer */
45 return ret; 45 return ret;
46} 46}
47 47
@@ -56,7 +56,7 @@ static void au_write_byte(struct mtd_info *mtd, u_char byte)
56{ 56{
57 struct nand_chip *this = mtd->priv; 57 struct nand_chip *this = mtd->priv;
58 writeb(byte, this->IO_ADDR_W); 58 writeb(byte, this->IO_ADDR_W);
59 au_sync(); 59 wmb(); /* drain writebuffer */
60} 60}
61 61
62/** 62/**
@@ -69,7 +69,7 @@ static u_char au_read_byte16(struct mtd_info *mtd)
69{ 69{
70 struct nand_chip *this = mtd->priv; 70 struct nand_chip *this = mtd->priv;
71 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R)); 71 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
72 au_sync(); 72 wmb(); /* drain writebuffer */
73 return ret; 73 return ret;
74} 74}
75 75
@@ -84,7 +84,7 @@ static void au_write_byte16(struct mtd_info *mtd, u_char byte)
84{ 84{
85 struct nand_chip *this = mtd->priv; 85 struct nand_chip *this = mtd->priv;
86 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W); 86 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
87 au_sync(); 87 wmb(); /* drain writebuffer */
88} 88}
89 89
90/** 90/**
@@ -97,7 +97,7 @@ static u16 au_read_word(struct mtd_info *mtd)
97{ 97{
98 struct nand_chip *this = mtd->priv; 98 struct nand_chip *this = mtd->priv;
99 u16 ret = readw(this->IO_ADDR_R); 99 u16 ret = readw(this->IO_ADDR_R);
100 au_sync(); 100 wmb(); /* drain writebuffer */
101 return ret; 101 return ret;
102} 102}
103 103
@@ -116,7 +116,7 @@ static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
116 116
117 for (i = 0; i < len; i++) { 117 for (i = 0; i < len; i++) {
118 writeb(buf[i], this->IO_ADDR_W); 118 writeb(buf[i], this->IO_ADDR_W);
119 au_sync(); 119 wmb(); /* drain writebuffer */
120 } 120 }
121} 121}
122 122
@@ -135,7 +135,7 @@ static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
135 135
136 for (i = 0; i < len; i++) { 136 for (i = 0; i < len; i++) {
137 buf[i] = readb(this->IO_ADDR_R); 137 buf[i] = readb(this->IO_ADDR_R);
138 au_sync(); 138 wmb(); /* drain writebuffer */
139 } 139 }
140} 140}
141 141
@@ -156,7 +156,7 @@ static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
156 156
157 for (i = 0; i < len; i++) { 157 for (i = 0; i < len; i++) {
158 writew(p[i], this->IO_ADDR_W); 158 writew(p[i], this->IO_ADDR_W);
159 au_sync(); 159 wmb(); /* drain writebuffer */
160 } 160 }
161 161
162} 162}
@@ -178,7 +178,7 @@ static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
178 178
179 for (i = 0; i < len; i++) { 179 for (i = 0; i < len; i++) {
180 p[i] = readw(this->IO_ADDR_R); 180 p[i] = readw(this->IO_ADDR_R);
181 au_sync(); 181 wmb(); /* drain writebuffer */
182 } 182 }
183} 183}
184 184
@@ -223,26 +223,23 @@ static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
223 223
224 case NAND_CTL_SETNCE: 224 case NAND_CTL_SETNCE:
225 /* assert (force assert) chip enable */ 225 /* assert (force assert) chip enable */
226 au_writel((1 << (4 + ctx->cs)), MEM_STNDCTL); 226 alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
227 break; 227 break;
228 228
229 case NAND_CTL_CLRNCE: 229 case NAND_CTL_CLRNCE:
230 /* deassert chip enable */ 230 /* deassert chip enable */
231 au_writel(0, MEM_STNDCTL); 231 alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
232 break; 232 break;
233 } 233 }
234 234
235 this->IO_ADDR_R = this->IO_ADDR_W; 235 this->IO_ADDR_R = this->IO_ADDR_W;
236 236
237 /* Drain the writebuffer */ 237 wmb(); /* Drain the writebuffer */
238 au_sync();
239} 238}
240 239
241int au1550_device_ready(struct mtd_info *mtd) 240int au1550_device_ready(struct mtd_info *mtd)
242{ 241{
243 int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0; 242 return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
244 au_sync();
245 return ret;
246} 243}
247 244
248/** 245/**
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