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authorManuel Lauss <manuel.lauss@gmail.com>2014-07-23 10:36:25 -0400
committerRalf Baechle <ralf@linux-mips.org>2014-07-30 07:53:52 -0400
commit9cf12167e909a86fbc4b39cf4cffef4cba40f1b3 (patch)
tree034c96710ea6f4fb1de8c47d0132c585c8013693 /drivers/mtd
parent1d09de7dc76ef96a9a2c7c0244e20f12d68e6ef8 (diff)
MIPS: Alchemy: add helpers to access static memory ctrl registers.
This patch changes the static memory controller registers to offsets from base, prefixes them with AU1000_ to avoid silent failures due to changed addresses and introduces helpers to access them. No functional changes, comparing assembly of a few select functions shows no differences. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7463/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/au1550nd.c8
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index bc5c518828d2..6cece6e7ee6b 100644
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -223,12 +223,12 @@ static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
223 223
224 case NAND_CTL_SETNCE: 224 case NAND_CTL_SETNCE:
225 /* assert (force assert) chip enable */ 225 /* assert (force assert) chip enable */
226 au_writel((1 << (4 + ctx->cs)), MEM_STNDCTL); 226 alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
227 break; 227 break;
228 228
229 case NAND_CTL_CLRNCE: 229 case NAND_CTL_CLRNCE:
230 /* deassert chip enable */ 230 /* deassert chip enable */
231 au_writel(0, MEM_STNDCTL); 231 alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
232 break; 232 break;
233 } 233 }
234 234
@@ -240,9 +240,7 @@ static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
240 240
241int au1550_device_ready(struct mtd_info *mtd) 241int au1550_device_ready(struct mtd_info *mtd)
242{ 242{
243 int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0; 243 return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
244 au_sync();
245 return ret;
246} 244}
247 245
248/** 246/**