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authorArtem Bityutskiy <artem.bityutskiy@linux.intel.com>2013-03-04 06:39:30 -0500
committerDavid Woodhouse <David.Woodhouse@intel.com>2013-04-05 06:58:52 -0400
commit7d321ec171a74cfb1f54e568dc02997d98b6f9d6 (patch)
tree22f74ffc1532218461bb94b8285d4151612d25e0 /drivers/mtd
parent5dc63fa2c2e149dd3e8128e54c9ca251d0558ea0 (diff)
mtd: nand_ids: minor clean-ups
Clean-up the code a little bit: * clean-up commentaries. * move macro definitions to the top of the file. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/nand_ids.c34
1 files changed, 15 insertions, 19 deletions
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 9c612388e5de..c44e89fbbf79 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -10,21 +10,21 @@
10 */ 10 */
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/mtd/nand.h> 12#include <linux/mtd/nand.h>
13/* 13
14* Chip ID list 14#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS
15* 15#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
16* Name. ID code, pagesize, chipsize in MegaByte, eraseblock size, 16
17* options
18*
19* Pagesize; 0, 256, 512
20* 0 get this information from the extended chip ID
21+ 256 256 Byte page size
22* 512 512 Byte page size
23*/
24struct nand_flash_dev nand_flash_ids[] = {
25#define SP_OPTIONS NAND_NEED_READRDY 17#define SP_OPTIONS NAND_NEED_READRDY
26#define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16) 18#define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16)
27 19
20/*
21 * The chip ID list:
22 * name, device ID, page size, chip size in MiB, eraseblock size, options
23 *
24 * If page size and eraseblock size are 0, the sizes are taken from the
25 * extended chip ID.
26 */
27struct nand_flash_dev nand_flash_ids[] = {
28#ifdef CONFIG_MTD_NAND_MUSEUM_IDS 28#ifdef CONFIG_MTD_NAND_MUSEUM_IDS
29 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, SP_OPTIONS}, 29 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, SP_OPTIONS},
30 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, SP_OPTIONS}, 30 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, SP_OPTIONS},
@@ -69,11 +69,9 @@ struct nand_flash_dev nand_flash_ids[] = {
69 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, SP_OPTIONS}, 69 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, SP_OPTIONS},
70 70
71 /* 71 /*
72 * These are the new chips with large page size. The pagesize and the 72 * These are the new chips with large page size. Their page size and
73 * erasesize is determined from the extended id bytes 73 * eraseblock size are determined from the extended ID bytes.
74 */ 74 */
75#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS
76#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
77 75
78 /* 512 Megabit */ 76 /* 512 Megabit */
79 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS}, 77 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
@@ -164,9 +162,7 @@ struct nand_flash_dev nand_flash_ids[] = {
164 {NULL,} 162 {NULL,}
165}; 163};
166 164
167/* 165/* Manufacturer IDs */
168* Manufacturer ID list
169*/
170struct nand_manufacturers nand_manuf_ids[] = { 166struct nand_manufacturers nand_manuf_ids[] = {
171 {NAND_MFR_TOSHIBA, "Toshiba"}, 167 {NAND_MFR_TOSHIBA, "Toshiba"},
172 {NAND_MFR_SAMSUNG, "Samsung"}, 168 {NAND_MFR_SAMSUNG, "Samsung"},