diff options
author | Elie De Brauwer <eliedebrauwer@gmail.com> | 2013-09-17 13:48:22 -0400 |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2013-09-27 06:56:22 -0400 |
commit | 2b468ef0e7959b703626b64c4d264ef822c9267a (patch) | |
tree | 7f8c4471558965162b2a8626f4fb288441462600 /drivers/mtd | |
parent | 5cb1327172281cadb7ee8c5fa294d7ac8e09b8db (diff) |
mtd: m25p80: Fix 4 byte addressing mode for Micron devices.
According to the datasheet for Micron n25q256a (N25Q256A13ESF40F) 4-byte
addressing mode should be entered as follows:
<quote>
To enter or exit the 4-byte address mode, the WRITE ENABLE command
must be executed to set the write enable latch bit to 1. (Note: The
WRITE ENABLE command must NOT be executed on the N25Q256A83ESF40x and
N25Q256A83E1240x devices.) S# must be driven LOW. The effect of the
command is immediate; after the command has been executed, the write
enable latch bit is cleared to 0.
</quote>
Micron's portable way to perform this for all types of Micron flash
is to first issue a write enable, then switch the addressing mode
followed by a write disable to avoid leaving the flash in a write-
able state.
Signed-off-by: Elie De Brauwer <eliedebrauwer@email.com>
[Brian: reworked a bit]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r-- | drivers/mtd/devices/m25p80.c | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index 26b14f9fcac6..6bc9618af094 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c | |||
@@ -168,12 +168,25 @@ static inline int write_disable(struct m25p *flash) | |||
168 | */ | 168 | */ |
169 | static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable) | 169 | static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable) |
170 | { | 170 | { |
171 | int status; | ||
172 | bool need_wren = false; | ||
173 | |||
171 | switch (JEDEC_MFR(jedec_id)) { | 174 | switch (JEDEC_MFR(jedec_id)) { |
172 | case CFI_MFR_MACRONIX: | ||
173 | case CFI_MFR_ST: /* Micron, actually */ | 175 | case CFI_MFR_ST: /* Micron, actually */ |
176 | /* Some Micron need WREN command; all will accept it */ | ||
177 | need_wren = true; | ||
178 | case CFI_MFR_MACRONIX: | ||
174 | case 0xEF /* winbond */: | 179 | case 0xEF /* winbond */: |
180 | if (need_wren) | ||
181 | write_enable(flash); | ||
182 | |||
175 | flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B; | 183 | flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B; |
176 | return spi_write(flash->spi, flash->command, 1); | 184 | status = spi_write(flash->spi, flash->command, 1); |
185 | |||
186 | if (need_wren) | ||
187 | write_disable(flash); | ||
188 | |||
189 | return status; | ||
177 | default: | 190 | default: |
178 | /* Spansion style */ | 191 | /* Spansion style */ |
179 | flash->command[0] = OPCODE_BRWR; | 192 | flash->command[0] = OPCODE_BRWR; |