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authorHuang Shijie <b32955@freescale.com>2013-08-27 05:29:04 -0400
committerBrian Norris <computersforpeace@gmail.com>2013-11-07 02:33:01 -0500
commitd159d8b7074181b154643aa15347d65a36b7ab59 (patch)
tree45d0fa0deaf29969b0178b08862d5df22d195acc /drivers/mtd/nand
parent4af9874916b14db407bee18590fe1847f541c2e2 (diff)
mtd: gpmi: decouple the chip select from the DMA channel
Decouple the chip select from the DMA channel, we use the DMA channel 0 to accecc all the nand devices. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/mtd/nand')
-rw-r--r--drivers/mtd/nand/gpmi-nand/gpmi-lib.c6
-rw-r--r--drivers/mtd/nand/gpmi-nand/gpmi-regs.h3
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 4f8857fa48a7..7d56d87599c0 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -187,6 +187,12 @@ int gpmi_init(struct gpmi_nand_data *this)
187 /* Select BCH ECC. */ 187 /* Select BCH ECC. */
188 writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET); 188 writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
189 189
190 /*
191 * Decouple the chip select from dma channel. We use dma0 for all
192 * the chips.
193 */
194 writel(BM_GPMI_CTRL1_DECOUPLE_CS, r->gpmi_regs + HW_GPMI_CTRL1_SET);
195
190 gpmi_disable_clk(this); 196 gpmi_disable_clk(this);
191 return 0; 197 return 0;
192err_out: 198err_out:
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
index 53397cc290fc..82114cdc8330 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
@@ -108,6 +108,9 @@
108#define HW_GPMI_CTRL1_CLR 0x00000068 108#define HW_GPMI_CTRL1_CLR 0x00000068
109#define HW_GPMI_CTRL1_TOG 0x0000006c 109#define HW_GPMI_CTRL1_TOG 0x0000006c
110 110
111#define BP_GPMI_CTRL1_DECOUPLE_CS 24
112#define BM_GPMI_CTRL1_DECOUPLE_CS (1 << BP_GPMI_CTRL1_DECOUPLE_CS)
113
111#define BP_GPMI_CTRL1_WRN_DLY_SEL 22 114#define BP_GPMI_CTRL1_WRN_DLY_SEL 22
112#define BM_GPMI_CTRL1_WRN_DLY_SEL (0x3 << BP_GPMI_CTRL1_WRN_DLY_SEL) 115#define BM_GPMI_CTRL1_WRN_DLY_SEL (0x3 << BP_GPMI_CTRL1_WRN_DLY_SEL)
113#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \ 116#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \