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authorLinus Torvalds <torvalds@linux-foundation.org>2012-03-30 20:31:56 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-03-30 20:31:56 -0400
commit623ff7739e7c00fa3d55dbfd42a492a68298fd7a (patch)
tree0b7461753a1b13b27ea2958a7d48c6efb47bba54 /drivers/mtd/nand
parentc39e8ede284f469971589f2e04af78216e1a771d (diff)
parent7b0e67f604e1829e5292e1ad7743eb18dc42ea7c (diff)
Merge tag 'for-linus-3.4' of git://git.infradead.org/mtd-2.6
Pull MTD changes from David Woodhouse: - Artem's cleanup of the MTD API continues apace. - Fixes and improvements for ST FSMC and SuperH FLCTL NAND, amongst others. - More work on DiskOnChip G3, new driver for DiskOnChip G4. - Clean up debug/warning printks in JFFS2 to use pr_<level>. Fix up various trivial conflicts, largely due to changes in calling conventions for things like dmaengine_prep_slave_sg() (new inline wrapper to hide new parameter, clashing with rewrite of previously last parameter that used to be an 'append' flag, and is now a bitmap of 'unsigned long flags'). (Also some header file fallout - like so many merges this merge window - and silly conflicts with sparse fixes) * tag 'for-linus-3.4' of git://git.infradead.org/mtd-2.6: (120 commits) mtd: docg3 add protection against concurrency mtd: docg3 refactor cascade floors structure mtd: docg3 increase write/erase timeout mtd: docg3 fix inbound calculations mtd: nand: gpmi: fix function annotations mtd: phram: fix section mismatch for phram_setup mtd: unify initialization of erase_info->fail_addr mtd: support ONFI multi lun NAND mtd: sm_ftl: fix typo in major number. mtd: add device-tree support to spear_smi mtd: spear_smi: Remove default partition information from driver mtd: Add device-tree support to fsmc_nand mtd: fix section mismatch for doc_probe_device mtd: nand/fsmc: Remove sparse warnings and errors mtd: nand/fsmc: Add DMA support mtd: nand/fsmc: Access the NAND device word by word whenever possible mtd: nand/fsmc: Use dev_err to report error scenario mtd: nand/fsmc: Use devm routines mtd: nand/fsmc: Modify fsmc driver to accept nand timing parameters via platform mtd: fsmc_nand: add pm callbacks to support hibernation ...
Diffstat (limited to 'drivers/mtd/nand')
-rw-r--r--drivers/mtd/nand/Kconfig21
-rw-r--r--drivers/mtd/nand/Makefile1
-rw-r--r--drivers/mtd/nand/alauda.c9
-rw-r--r--drivers/mtd/nand/atmel_nand.c1
-rw-r--r--drivers/mtd/nand/bcm_umi_nand.c10
-rw-r--r--drivers/mtd/nand/bf5xx_nand.c2
-rw-r--r--drivers/mtd/nand/cafe_nand.c3
-rw-r--r--drivers/mtd/nand/cmx270_nand.c2
-rw-r--r--drivers/mtd/nand/cs553x_nand.c4
-rw-r--r--drivers/mtd/nand/davinci_nand.c5
-rw-r--r--drivers/mtd/nand/denali.c3
-rw-r--r--drivers/mtd/nand/diskonchip.c1
-rw-r--r--drivers/mtd/nand/docg4.c1377
-rw-r--r--drivers/mtd/nand/fsl_elbc_nand.c6
-rw-r--r--drivers/mtd/nand/fsmc_nand.c924
-rw-r--r--drivers/mtd/nand/gpmi-nand/gpmi-lib.c26
-rw-r--r--drivers/mtd/nand/gpmi-nand/gpmi-nand.c14
-rw-r--r--drivers/mtd/nand/gpmi-nand/gpmi-nand.h2
-rw-r--r--drivers/mtd/nand/h1910.c4
-rw-r--r--drivers/mtd/nand/jz4740_nand.c11
-rw-r--r--drivers/mtd/nand/mxc_nand.c11
-rw-r--r--drivers/mtd/nand/nand_base.c194
-rw-r--r--drivers/mtd/nand/ndfc.c1
-rw-r--r--drivers/mtd/nand/omap2.c5
-rw-r--r--drivers/mtd/nand/orion_nand.c4
-rw-r--r--drivers/mtd/nand/plat_nand.c5
-rw-r--r--drivers/mtd/nand/ppchameleonevb.c18
-rw-r--r--drivers/mtd/nand/pxa3xx_nand.c6
-rw-r--r--drivers/mtd/nand/r852.c1
-rw-r--r--drivers/mtd/nand/rtc_from4.c1
-rw-r--r--drivers/mtd/nand/s3c2410.c5
-rw-r--r--drivers/mtd/nand/sh_flctl.c106
-rw-r--r--drivers/mtd/nand/sharpsl.c5
-rw-r--r--drivers/mtd/nand/tmio_nand.c7
-rw-r--r--drivers/mtd/nand/txx9ndfmc.c3
35 files changed, 2366 insertions, 432 deletions
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index a3c4de551ebe..7d17cecad69d 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -314,6 +314,26 @@ config MTD_NAND_DISKONCHIP_BBTWRITE
314 load time (assuming you build diskonchip as a module) with the module 314 load time (assuming you build diskonchip as a module) with the module
315 parameter "inftl_bbt_write=1". 315 parameter "inftl_bbt_write=1".
316 316
317config MTD_NAND_DOCG4
318 tristate "Support for DiskOnChip G4 (EXPERIMENTAL)"
319 depends on EXPERIMENTAL
320 select BCH
321 select BITREVERSE
322 help
323 Support for diskonchip G4 nand flash, found in various smartphones and
324 PDAs, among them the Palm Treo680, HTC Prophet and Wizard, Toshiba
325 Portege G900, Asus P526, and O2 XDA Zinc.
326
327 With this driver you will be able to use UBI and create a ubifs on the
328 device, so you may wish to consider enabling UBI and UBIFS as well.
329
330 These devices ship with the Mys/Sandisk SAFTL formatting, for which
331 there is currently no mtd parser, so you may want to use command line
332 partitioning to segregate write-protected blocks. On the Treo680, the
333 first five erase blocks (256KiB each) are write-protected, followed
334 by the block containing the saftl partition table. This is probably
335 typical.
336
317config MTD_NAND_SHARPSL 337config MTD_NAND_SHARPSL
318 tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)" 338 tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)"
319 depends on ARCH_PXA 339 depends on ARCH_PXA
@@ -421,7 +441,6 @@ config MTD_NAND_NANDSIM
421config MTD_NAND_GPMI_NAND 441config MTD_NAND_GPMI_NAND
422 bool "GPMI NAND Flash Controller driver" 442 bool "GPMI NAND Flash Controller driver"
423 depends on MTD_NAND && (SOC_IMX23 || SOC_IMX28) 443 depends on MTD_NAND && (SOC_IMX23 || SOC_IMX28)
424 select MTD_CMDLINE_PARTS
425 help 444 help
426 Enables NAND Flash support for IMX23 or IMX28. 445 Enables NAND Flash support for IMX23 or IMX28.
427 The GPMI controller is very powerful, with the help of BCH 446 The GPMI controller is very powerful, with the help of BCH
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 19bc8cb1d187..d4b4d8739bd8 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB) += ppchameleonevb.o
19obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o 19obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
20obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o 20obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o
21obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o 21obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o
22obj-$(CONFIG_MTD_NAND_DOCG4) += docg4.o
22obj-$(CONFIG_MTD_NAND_FSMC) += fsmc_nand.o 23obj-$(CONFIG_MTD_NAND_FSMC) += fsmc_nand.o
23obj-$(CONFIG_MTD_NAND_H1900) += h1910.o 24obj-$(CONFIG_MTD_NAND_H1900) += h1910.o
24obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o 25obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o
diff --git a/drivers/mtd/nand/alauda.c b/drivers/mtd/nand/alauda.c
index 6a5ff64a139e..4f20e1d8bef1 100644
--- a/drivers/mtd/nand/alauda.c
+++ b/drivers/mtd/nand/alauda.c
@@ -585,12 +585,13 @@ static int alauda_init_media(struct alauda *al)
585 mtd->writesize = 1<<card->pageshift; 585 mtd->writesize = 1<<card->pageshift;
586 mtd->type = MTD_NANDFLASH; 586 mtd->type = MTD_NANDFLASH;
587 mtd->flags = MTD_CAP_NANDFLASH; 587 mtd->flags = MTD_CAP_NANDFLASH;
588 mtd->read = alauda_read; 588 mtd->_read = alauda_read;
589 mtd->write = alauda_write; 589 mtd->_write = alauda_write;
590 mtd->erase = alauda_erase; 590 mtd->_erase = alauda_erase;
591 mtd->block_isbad = alauda_isbad; 591 mtd->_block_isbad = alauda_isbad;
592 mtd->priv = al; 592 mtd->priv = al;
593 mtd->owner = THIS_MODULE; 593 mtd->owner = THIS_MODULE;
594 mtd->ecc_strength = 1;
594 595
595 err = mtd_device_register(mtd, NULL, 0); 596 err = mtd_device_register(mtd, NULL, 0);
596 if (err) { 597 if (err) {
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index ae7e37d9ac17..2165576a1c67 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -603,6 +603,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
603 nand_chip->ecc.hwctl = atmel_nand_hwctl; 603 nand_chip->ecc.hwctl = atmel_nand_hwctl;
604 nand_chip->ecc.read_page = atmel_nand_read_page; 604 nand_chip->ecc.read_page = atmel_nand_read_page;
605 nand_chip->ecc.bytes = 4; 605 nand_chip->ecc.bytes = 4;
606 nand_chip->ecc.strength = 1;
606 } 607 }
607 608
608 nand_chip->chip_delay = 20; /* 20us command delay time */ 609 nand_chip->chip_delay = 20; /* 20us command delay time */
diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c
index 64c9cbaf86a1..6908cdde3065 100644
--- a/drivers/mtd/nand/bcm_umi_nand.c
+++ b/drivers/mtd/nand/bcm_umi_nand.c
@@ -475,6 +475,14 @@ static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
475 largepage_bbt.options = NAND_BBT_SCAN2NDPAGE; 475 largepage_bbt.options = NAND_BBT_SCAN2NDPAGE;
476 this->badblock_pattern = &largepage_bbt; 476 this->badblock_pattern = &largepage_bbt;
477 } 477 }
478
479 /*
480 * FIXME: ecc strength value of 6 bits per 512 bytes of data is a
481 * conservative guess, given 13 ecc bytes and using bch alg.
482 * (Assume Galois field order m=15 to allow a margin of error.)
483 */
484 this->ecc.strength = 6;
485
478#endif 486#endif
479 487
480 /* Now finish off the scan, now that ecc.layout has been initialized. */ 488 /* Now finish off the scan, now that ecc.layout has been initialized. */
@@ -487,7 +495,7 @@ static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
487 495
488 /* Register the partitions */ 496 /* Register the partitions */
489 board_mtd->name = "bcm_umi-nand"; 497 board_mtd->name = "bcm_umi-nand";
490 mtd_device_parse_register(board_mtd, NULL, 0, NULL, 0); 498 mtd_device_parse_register(board_mtd, NULL, NULL, NULL, 0);
491 499
492 /* Return happy */ 500 /* Return happy */
493 return 0; 501 return 0;
diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c
index dd899cb5d366..d7b86b925de5 100644
--- a/drivers/mtd/nand/bf5xx_nand.c
+++ b/drivers/mtd/nand/bf5xx_nand.c
@@ -702,9 +702,11 @@ static int bf5xx_nand_scan(struct mtd_info *mtd)
702 if (likely(mtd->writesize >= 512)) { 702 if (likely(mtd->writesize >= 512)) {
703 chip->ecc.size = 512; 703 chip->ecc.size = 512;
704 chip->ecc.bytes = 6; 704 chip->ecc.bytes = 6;
705 chip->ecc.strength = 2;
705 } else { 706 } else {
706 chip->ecc.size = 256; 707 chip->ecc.size = 256;
707 chip->ecc.bytes = 3; 708 chip->ecc.bytes = 3;
709 chip->ecc.strength = 1;
708 bfin_write_NFC_CTL(bfin_read_NFC_CTL() & ~(1 << NFC_PG_SIZE_OFFSET)); 710 bfin_write_NFC_CTL(bfin_read_NFC_CTL() & ~(1 << NFC_PG_SIZE_OFFSET));
709 SSYNC(); 711 SSYNC();
710 } 712 }
diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c
index 72d3f23490c5..2a96e1a12062 100644
--- a/drivers/mtd/nand/cafe_nand.c
+++ b/drivers/mtd/nand/cafe_nand.c
@@ -783,6 +783,7 @@ static int __devinit cafe_nand_probe(struct pci_dev *pdev,
783 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME; 783 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
784 cafe->nand.ecc.size = mtd->writesize; 784 cafe->nand.ecc.size = mtd->writesize;
785 cafe->nand.ecc.bytes = 14; 785 cafe->nand.ecc.bytes = 14;
786 cafe->nand.ecc.strength = 4;
786 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug; 787 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
787 cafe->nand.ecc.calculate = (void *)cafe_nand_bug; 788 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
788 cafe->nand.ecc.correct = (void *)cafe_nand_bug; 789 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
@@ -799,7 +800,7 @@ static int __devinit cafe_nand_probe(struct pci_dev *pdev,
799 pci_set_drvdata(pdev, mtd); 800 pci_set_drvdata(pdev, mtd);
800 801
801 mtd->name = "cafe_nand"; 802 mtd->name = "cafe_nand";
802 mtd_device_parse_register(mtd, part_probes, 0, NULL, 0); 803 mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
803 804
804 goto out; 805 goto out;
805 806
diff --git a/drivers/mtd/nand/cmx270_nand.c b/drivers/mtd/nand/cmx270_nand.c
index 737ef9a04fdb..1024bfc05c86 100644
--- a/drivers/mtd/nand/cmx270_nand.c
+++ b/drivers/mtd/nand/cmx270_nand.c
@@ -219,7 +219,7 @@ static int __init cmx270_init(void)
219 } 219 }
220 220
221 /* Register the partitions */ 221 /* Register the partitions */
222 ret = mtd_device_parse_register(cmx270_nand_mtd, NULL, 0, 222 ret = mtd_device_parse_register(cmx270_nand_mtd, NULL, NULL,
223 partition_info, NUM_PARTITIONS); 223 partition_info, NUM_PARTITIONS);
224 if (ret) 224 if (ret)
225 goto err_scan; 225 goto err_scan;
diff --git a/drivers/mtd/nand/cs553x_nand.c b/drivers/mtd/nand/cs553x_nand.c
index 414afa793563..821c34c62500 100644
--- a/drivers/mtd/nand/cs553x_nand.c
+++ b/drivers/mtd/nand/cs553x_nand.c
@@ -248,6 +248,8 @@ static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
248 goto out_ior; 248 goto out_ior;
249 } 249 }
250 250
251 this->ecc.strength = 1;
252
251 new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs); 253 new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs);
252 254
253 cs553x_mtd[cs] = new_mtd; 255 cs553x_mtd[cs] = new_mtd;
@@ -313,7 +315,7 @@ static int __init cs553x_init(void)
313 for (i = 0; i < NR_CS553X_CONTROLLERS; i++) { 315 for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
314 if (cs553x_mtd[i]) { 316 if (cs553x_mtd[i]) {
315 /* If any devices registered, return success. Else the last error. */ 317 /* If any devices registered, return success. Else the last error. */
316 mtd_device_parse_register(cs553x_mtd[i], NULL, 0, 318 mtd_device_parse_register(cs553x_mtd[i], NULL, NULL,
317 NULL, 0); 319 NULL, 0);
318 err = 0; 320 err = 0;
319 } 321 }
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 6e566156956f..d94b03c207af 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -641,6 +641,7 @@ static int __init nand_davinci_probe(struct platform_device *pdev)
641 info->chip.ecc.bytes = 3; 641 info->chip.ecc.bytes = 3;
642 } 642 }
643 info->chip.ecc.size = 512; 643 info->chip.ecc.size = 512;
644 info->chip.ecc.strength = pdata->ecc_bits;
644 break; 645 break;
645 default: 646 default:
646 ret = -EINVAL; 647 ret = -EINVAL;
@@ -752,8 +753,8 @@ syndrome_done:
752 if (ret < 0) 753 if (ret < 0)
753 goto err_scan; 754 goto err_scan;
754 755
755 ret = mtd_device_parse_register(&info->mtd, NULL, 0, 756 ret = mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts,
756 pdata->parts, pdata->nr_parts); 757 pdata->nr_parts);
757 758
758 if (ret < 0) 759 if (ret < 0)
759 goto err_scan; 760 goto err_scan;
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 3984d488f9ab..a9e57d686297 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -1590,6 +1590,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1590 ECC_15BITS * (denali->mtd.writesize / 1590 ECC_15BITS * (denali->mtd.writesize /
1591 ECC_SECTOR_SIZE)))) { 1591 ECC_SECTOR_SIZE)))) {
1592 /* if MLC OOB size is large enough, use 15bit ECC*/ 1592 /* if MLC OOB size is large enough, use 15bit ECC*/
1593 denali->nand.ecc.strength = 15;
1593 denali->nand.ecc.layout = &nand_15bit_oob; 1594 denali->nand.ecc.layout = &nand_15bit_oob;
1594 denali->nand.ecc.bytes = ECC_15BITS; 1595 denali->nand.ecc.bytes = ECC_15BITS;
1595 iowrite32(15, denali->flash_reg + ECC_CORRECTION); 1596 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
@@ -1600,12 +1601,14 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1600 " contain 8bit ECC correction codes"); 1601 " contain 8bit ECC correction codes");
1601 goto failed_req_irq; 1602 goto failed_req_irq;
1602 } else { 1603 } else {
1604 denali->nand.ecc.strength = 8;
1603 denali->nand.ecc.layout = &nand_8bit_oob; 1605 denali->nand.ecc.layout = &nand_8bit_oob;
1604 denali->nand.ecc.bytes = ECC_8BITS; 1606 denali->nand.ecc.bytes = ECC_8BITS;
1605 iowrite32(8, denali->flash_reg + ECC_CORRECTION); 1607 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
1606 } 1608 }
1607 1609
1608 denali->nand.ecc.bytes *= denali->devnum; 1610 denali->nand.ecc.bytes *= denali->devnum;
1611 denali->nand.ecc.strength *= denali->devnum;
1609 denali->nand.ecc.layout->eccbytes *= 1612 denali->nand.ecc.layout->eccbytes *=
1610 denali->mtd.writesize / ECC_SECTOR_SIZE; 1613 denali->mtd.writesize / ECC_SECTOR_SIZE;
1611 denali->nand.ecc.layout->oobfree[0].offset = 1614 denali->nand.ecc.layout->oobfree[0].offset =
diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c
index df921e7a496c..e2ca067631cf 100644
--- a/drivers/mtd/nand/diskonchip.c
+++ b/drivers/mtd/nand/diskonchip.c
@@ -1653,6 +1653,7 @@ static int __init doc_probe(unsigned long physadr)
1653 nand->ecc.mode = NAND_ECC_HW_SYNDROME; 1653 nand->ecc.mode = NAND_ECC_HW_SYNDROME;
1654 nand->ecc.size = 512; 1654 nand->ecc.size = 512;
1655 nand->ecc.bytes = 6; 1655 nand->ecc.bytes = 6;
1656 nand->ecc.strength = 2;
1656 nand->bbt_options = NAND_BBT_USE_FLASH; 1657 nand->bbt_options = NAND_BBT_USE_FLASH;
1657 1658
1658 doc->physadr = physadr; 1659 doc->physadr = physadr;
diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c
new file mode 100644
index 000000000000..b08202664543
--- /dev/null
+++ b/drivers/mtd/nand/docg4.c
@@ -0,0 +1,1377 @@
1/*
2 * Copyright © 2012 Mike Dunn <mikedunn@newsguy.com>
3 *
4 * mtd nand driver for M-Systems DiskOnChip G4
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * Tested on the Palm Treo 680. The G4 is also present on Toshiba Portege, Asus
12 * P526, some HTC smartphones (Wizard, Prophet, ...), O2 XDA Zinc, maybe others.
13 * Should work on these as well. Let me know!
14 *
15 * TODO:
16 *
17 * Mechanism for management of password-protected areas
18 *
19 * Hamming ecc when reading oob only
20 *
21 * According to the M-Sys documentation, this device is also available in a
22 * "dual-die" configuration having a 256MB capacity, but no mechanism for
23 * detecting this variant is documented. Currently this driver assumes 128MB
24 * capacity.
25 *
26 * Support for multiple cascaded devices ("floors"). Not sure which gadgets
27 * contain multiple G4s in a cascaded configuration, if any.
28 *
29 */
30
31#include <linux/kernel.h>
32#include <linux/slab.h>
33#include <linux/init.h>
34#include <linux/string.h>
35#include <linux/sched.h>
36#include <linux/delay.h>
37#include <linux/module.h>
38#include <linux/export.h>
39#include <linux/platform_device.h>
40#include <linux/io.h>
41#include <linux/bitops.h>
42#include <linux/mtd/partitions.h>
43#include <linux/mtd/mtd.h>
44#include <linux/mtd/nand.h>
45#include <linux/bch.h>
46#include <linux/bitrev.h>
47
48/*
49 * You'll want to ignore badblocks if you're reading a partition that contains
50 * data written by the TrueFFS library (i.e., by PalmOS, Windows, etc), since
51 * it does not use mtd nand's method for marking bad blocks (using oob area).
52 * This will also skip the check of the "page written" flag.
53 */
54static bool ignore_badblocks;
55module_param(ignore_badblocks, bool, 0);
56MODULE_PARM_DESC(ignore_badblocks, "no badblock checking performed");
57
58struct docg4_priv {
59 struct mtd_info *mtd;
60 struct device *dev;
61 void __iomem *virtadr;
62 int status;
63 struct {
64 unsigned int command;
65 int column;
66 int page;
67 } last_command;
68 uint8_t oob_buf[16];
69 uint8_t ecc_buf[7];
70 int oob_page;
71 struct bch_control *bch;
72};
73
74/*
75 * Defines prefixed with DOCG4 are unique to the diskonchip G4. All others are
76 * shared with other diskonchip devices (P3, G3 at least).
77 *
78 * Functions with names prefixed with docg4_ are mtd / nand interface functions
79 * (though they may also be called internally). All others are internal.
80 */
81
82#define DOC_IOSPACE_DATA 0x0800
83
84/* register offsets */
85#define DOC_CHIPID 0x1000
86#define DOC_DEVICESELECT 0x100a
87#define DOC_ASICMODE 0x100c
88#define DOC_DATAEND 0x101e
89#define DOC_NOP 0x103e
90
91#define DOC_FLASHSEQUENCE 0x1032
92#define DOC_FLASHCOMMAND 0x1034
93#define DOC_FLASHADDRESS 0x1036
94#define DOC_FLASHCONTROL 0x1038
95#define DOC_ECCCONF0 0x1040
96#define DOC_ECCCONF1 0x1042
97#define DOC_HAMMINGPARITY 0x1046
98#define DOC_BCH_SYNDROM(idx) (0x1048 + idx)
99
100#define DOC_ASICMODECONFIRM 0x1072
101#define DOC_CHIPID_INV 0x1074
102#define DOC_POWERMODE 0x107c
103
104#define DOCG4_MYSTERY_REG 0x1050
105
106/* apparently used only to write oob bytes 6 and 7 */
107#define DOCG4_OOB_6_7 0x1052
108
109/* DOC_FLASHSEQUENCE register commands */
110#define DOC_SEQ_RESET 0x00
111#define DOCG4_SEQ_PAGE_READ 0x03
112#define DOCG4_SEQ_FLUSH 0x29
113#define DOCG4_SEQ_PAGEWRITE 0x16
114#define DOCG4_SEQ_PAGEPROG 0x1e
115#define DOCG4_SEQ_BLOCKERASE 0x24
116
117/* DOC_FLASHCOMMAND register commands */
118#define DOCG4_CMD_PAGE_READ 0x00
119#define DOC_CMD_ERASECYCLE2 0xd0
120#define DOCG4_CMD_FLUSH 0x70
121#define DOCG4_CMD_READ2 0x30
122#define DOC_CMD_PROG_BLOCK_ADDR 0x60
123#define DOCG4_CMD_PAGEWRITE 0x80
124#define DOC_CMD_PROG_CYCLE2 0x10
125#define DOC_CMD_RESET 0xff
126
127/* DOC_POWERMODE register bits */
128#define DOC_POWERDOWN_READY 0x80
129
130/* DOC_FLASHCONTROL register bits */
131#define DOC_CTRL_CE 0x10
132#define DOC_CTRL_UNKNOWN 0x40
133#define DOC_CTRL_FLASHREADY 0x01
134
135/* DOC_ECCCONF0 register bits */
136#define DOC_ECCCONF0_READ_MODE 0x8000
137#define DOC_ECCCONF0_UNKNOWN 0x2000
138#define DOC_ECCCONF0_ECC_ENABLE 0x1000
139#define DOC_ECCCONF0_DATA_BYTES_MASK 0x07ff
140
141/* DOC_ECCCONF1 register bits */
142#define DOC_ECCCONF1_BCH_SYNDROM_ERR 0x80
143#define DOC_ECCCONF1_ECC_ENABLE 0x07
144#define DOC_ECCCONF1_PAGE_IS_WRITTEN 0x20
145
146/* DOC_ASICMODE register bits */
147#define DOC_ASICMODE_RESET 0x00
148#define DOC_ASICMODE_NORMAL 0x01
149#define DOC_ASICMODE_POWERDOWN 0x02
150#define DOC_ASICMODE_MDWREN 0x04
151#define DOC_ASICMODE_BDETCT_RESET 0x08
152#define DOC_ASICMODE_RSTIN_RESET 0x10
153#define DOC_ASICMODE_RAM_WE 0x20
154
155/* good status values read after read/write/erase operations */
156#define DOCG4_PROGSTATUS_GOOD 0x51
157#define DOCG4_PROGSTATUS_GOOD_2 0xe0
158
159/*
160 * On read operations (page and oob-only), the first byte read from I/O reg is a
161 * status. On error, it reads 0x73; otherwise, it reads either 0x71 (first read
162 * after reset only) or 0x51, so bit 1 is presumed to be an error indicator.
163 */
164#define DOCG4_READ_ERROR 0x02 /* bit 1 indicates read error */
165
166/* anatomy of the device */
167#define DOCG4_CHIP_SIZE 0x8000000
168#define DOCG4_PAGE_SIZE 0x200
169#define DOCG4_PAGES_PER_BLOCK 0x200
170#define DOCG4_BLOCK_SIZE (DOCG4_PAGES_PER_BLOCK * DOCG4_PAGE_SIZE)
171#define DOCG4_NUMBLOCKS (DOCG4_CHIP_SIZE / DOCG4_BLOCK_SIZE)
172#define DOCG4_OOB_SIZE 0x10
173#define DOCG4_CHIP_SHIFT 27 /* log_2(DOCG4_CHIP_SIZE) */
174#define DOCG4_PAGE_SHIFT 9 /* log_2(DOCG4_PAGE_SIZE) */
175#define DOCG4_ERASE_SHIFT 18 /* log_2(DOCG4_BLOCK_SIZE) */
176
177/* all but the last byte is included in ecc calculation */
178#define DOCG4_BCH_SIZE (DOCG4_PAGE_SIZE + DOCG4_OOB_SIZE - 1)
179
180#define DOCG4_USERDATA_LEN 520 /* 512 byte page plus 8 oob avail to user */
181
182/* expected values from the ID registers */
183#define DOCG4_IDREG1_VALUE 0x0400
184#define DOCG4_IDREG2_VALUE 0xfbff
185
186/* primitive polynomial used to build the Galois field used by hw ecc gen */
187#define DOCG4_PRIMITIVE_POLY 0x4443
188
189#define DOCG4_M 14 /* Galois field is of order 2^14 */
190#define DOCG4_T 4 /* BCH alg corrects up to 4 bit errors */
191
192#define DOCG4_FACTORY_BBT_PAGE 16 /* page where read-only factory bbt lives */
193
194/*
195 * Oob bytes 0 - 6 are available to the user.
196 * Byte 7 is hamming ecc for first 7 bytes. Bytes 8 - 14 are hw-generated ecc.
197 * Byte 15 (the last) is used by the driver as a "page written" flag.
198 */
199static struct nand_ecclayout docg4_oobinfo = {
200 .eccbytes = 9,
201 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
202 .oobavail = 7,
203 .oobfree = { {0, 7} }
204};
205
206/*
207 * The device has a nop register which M-Sys claims is for the purpose of
208 * inserting precise delays. But beware; at least some operations fail if the
209 * nop writes are replaced with a generic delay!
210 */
211static inline void write_nop(void __iomem *docptr)
212{
213 writew(0, docptr + DOC_NOP);
214}
215
216static void docg4_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
217{
218 int i;
219 struct nand_chip *nand = mtd->priv;
220 uint16_t *p = (uint16_t *) buf;
221 len >>= 1;
222
223 for (i = 0; i < len; i++)
224 p[i] = readw(nand->IO_ADDR_R);
225}
226
227static void docg4_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
228{
229 int i;
230 struct nand_chip *nand = mtd->priv;
231 uint16_t *p = (uint16_t *) buf;
232 len >>= 1;
233
234 for (i = 0; i < len; i++)
235 writew(p[i], nand->IO_ADDR_W);
236}
237
238static int poll_status(struct docg4_priv *doc)
239{
240 /*
241 * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
242 * register. Operations known to take a long time (e.g., block erase)
243 * should sleep for a while before calling this.
244 */
245
246 uint16_t flash_status;
247 unsigned int timeo;
248 void __iomem *docptr = doc->virtadr;
249
250 dev_dbg(doc->dev, "%s...\n", __func__);
251
252 /* hardware quirk requires reading twice initially */
253 flash_status = readw(docptr + DOC_FLASHCONTROL);
254
255 timeo = 1000;
256 do {
257 cpu_relax();
258 flash_status = readb(docptr + DOC_FLASHCONTROL);
259 } while (!(flash_status & DOC_CTRL_FLASHREADY) && --timeo);
260
261
262 if (!timeo) {
263 dev_err(doc->dev, "%s: timed out!\n", __func__);
264 return NAND_STATUS_FAIL;
265 }
266
267 if (unlikely(timeo < 50))
268 dev_warn(doc->dev, "%s: nearly timed out; %d remaining\n",
269 __func__, timeo);
270
271 return 0;
272}
273
274
275static int docg4_wait(struct mtd_info *mtd, struct nand_chip *nand)
276{
277
278 struct docg4_priv *doc = nand->priv;
279 int status = NAND_STATUS_WP; /* inverse logic?? */
280 dev_dbg(doc->dev, "%s...\n", __func__);
281
282 /* report any previously unreported error */
283 if (doc->status) {
284 status |= doc->status;
285 doc->status = 0;
286 return status;
287 }
288
289 status |= poll_status(doc);
290 return status;
291}
292
293static void docg4_select_chip(struct mtd_info *mtd, int chip)
294{
295 /*
296 * Select among multiple cascaded chips ("floors"). Multiple floors are
297 * not yet supported, so the only valid non-negative value is 0.
298 */
299 struct nand_chip *nand = mtd->priv;
300 struct docg4_priv *doc = nand->priv;
301 void __iomem *docptr = doc->virtadr;
302
303 dev_dbg(doc->dev, "%s: chip %d\n", __func__, chip);
304
305 if (chip < 0)
306 return; /* deselected */
307
308 if (chip > 0)
309 dev_warn(doc->dev, "multiple floors currently unsupported\n");
310
311 writew(0, docptr + DOC_DEVICESELECT);
312}
313
314static void reset(struct mtd_info *mtd)
315{
316 /* full device reset */
317
318 struct nand_chip *nand = mtd->priv;
319 struct docg4_priv *doc = nand->priv;
320 void __iomem *docptr = doc->virtadr;
321
322 writew(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN,
323 docptr + DOC_ASICMODE);
324 writew(~(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN),
325 docptr + DOC_ASICMODECONFIRM);
326 write_nop(docptr);
327
328 writew(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN,
329 docptr + DOC_ASICMODE);
330 writew(~(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN),
331 docptr + DOC_ASICMODECONFIRM);
332
333 writew(DOC_ECCCONF1_ECC_ENABLE, docptr + DOC_ECCCONF1);
334
335 poll_status(doc);
336}
337
338static void read_hw_ecc(void __iomem *docptr, uint8_t *ecc_buf)
339{
340 /* read the 7 hw-generated ecc bytes */
341
342 int i;
343 for (i = 0; i < 7; i++) { /* hw quirk; read twice */
344 ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
345 ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
346 }
347}
348
349static int correct_data(struct mtd_info *mtd, uint8_t *buf, int page)
350{
351 /*
352 * Called after a page read when hardware reports bitflips.
353 * Up to four bitflips can be corrected.
354 */
355
356 struct nand_chip *nand = mtd->priv;
357 struct docg4_priv *doc = nand->priv;
358 void __iomem *docptr = doc->virtadr;
359 int i, numerrs, errpos[4];
360 const uint8_t blank_read_hwecc[8] = {
361 0xcf, 0x72, 0xfc, 0x1b, 0xa9, 0xc7, 0xb9, 0 };
362
363 read_hw_ecc(docptr, doc->ecc_buf); /* read 7 hw-generated ecc bytes */
364
365 /* check if read error is due to a blank page */
366 if (!memcmp(doc->ecc_buf, blank_read_hwecc, 7))
367 return 0; /* yes */
368
369 /* skip additional check of "written flag" if ignore_badblocks */
370 if (ignore_badblocks == false) {
371
372 /*
373 * If the hw ecc bytes are not those of a blank page, there's
374 * still a chance that the page is blank, but was read with
375 * errors. Check the "written flag" in last oob byte, which
376 * is set to zero when a page is written. If more than half
377 * the bits are set, assume a blank page. Unfortunately, the
378 * bit flips(s) are not reported in stats.
379 */
380
381 if (doc->oob_buf[15]) {
382 int bit, numsetbits = 0;
383 unsigned long written_flag = doc->oob_buf[15];
384 for_each_set_bit(bit, &written_flag, 8)
385 numsetbits++;
386 if (numsetbits > 4) { /* assume blank */
387 dev_warn(doc->dev,
388 "error(s) in blank page "
389 "at offset %08x\n",
390 page * DOCG4_PAGE_SIZE);
391 return 0;
392 }
393 }
394 }
395
396 /*
397 * The hardware ecc unit produces oob_ecc ^ calc_ecc. The kernel's bch
398 * algorithm is used to decode this. However the hw operates on page
399 * data in a bit order that is the reverse of that of the bch alg,
400 * requiring that the bits be reversed on the result. Thanks to Ivan
401 * Djelic for his analysis!
402 */
403 for (i = 0; i < 7; i++)
404 doc->ecc_buf[i] = bitrev8(doc->ecc_buf[i]);
405
406 numerrs = decode_bch(doc->bch, NULL, DOCG4_USERDATA_LEN, NULL,
407 doc->ecc_buf, NULL, errpos);
408
409 if (numerrs == -EBADMSG) {
410 dev_warn(doc->dev, "uncorrectable errors at offset %08x\n",
411 page * DOCG4_PAGE_SIZE);
412 return -EBADMSG;
413 }
414
415 BUG_ON(numerrs < 0); /* -EINVAL, or anything other than -EBADMSG */
416
417 /* undo last step in BCH alg (modulo mirroring not needed) */
418 for (i = 0; i < numerrs; i++)
419 errpos[i] = (errpos[i] & ~7)|(7-(errpos[i] & 7));
420
421 /* fix the errors */
422 for (i = 0; i < numerrs; i++) {
423
424 /* ignore if error within oob ecc bytes */
425 if (errpos[i] > DOCG4_USERDATA_LEN * 8)
426 continue;
427
428 /* if error within oob area preceeding ecc bytes... */
429 if (errpos[i] > DOCG4_PAGE_SIZE * 8)
430 change_bit(errpos[i] - DOCG4_PAGE_SIZE * 8,
431 (unsigned long *)doc->oob_buf);
432
433 else /* error in page data */
434 change_bit(errpos[i], (unsigned long *)buf);
435 }
436
437 dev_notice(doc->dev, "%d error(s) corrected at offset %08x\n",
438 numerrs, page * DOCG4_PAGE_SIZE);
439
440 return numerrs;
441}
442
443static uint8_t docg4_read_byte(struct mtd_info *mtd)
444{
445 struct nand_chip *nand = mtd->priv;
446 struct docg4_priv *doc = nand->priv;
447
448 dev_dbg(doc->dev, "%s\n", __func__);
449
450 if (doc->last_command.command == NAND_CMD_STATUS) {
451 int status;
452
453 /*
454 * Previous nand command was status request, so nand
455 * infrastructure code expects to read the status here. If an
456 * error occurred in a previous operation, report it.
457 */
458 doc->last_command.command = 0;
459
460 if (doc->status) {
461 status = doc->status;
462 doc->status = 0;
463 }
464
465 /* why is NAND_STATUS_WP inverse logic?? */
466 else
467 status = NAND_STATUS_WP | NAND_STATUS_READY;
468
469 return status;
470 }
471
472 dev_warn(doc->dev, "unexpectd call to read_byte()\n");
473
474 return 0;
475}
476
477static void write_addr(struct docg4_priv *doc, uint32_t docg4_addr)
478{
479 /* write the four address bytes packed in docg4_addr to the device */
480
481 void __iomem *docptr = doc->virtadr;
482 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
483 docg4_addr >>= 8;
484 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
485 docg4_addr >>= 8;
486 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
487 docg4_addr >>= 8;
488 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
489}
490
491static int read_progstatus(struct docg4_priv *doc)
492{
493 /*
494 * This apparently checks the status of programming. Done after an
495 * erasure, and after page data is written. On error, the status is
496 * saved, to be later retrieved by the nand infrastructure code.
497 */
498 void __iomem *docptr = doc->virtadr;
499
500 /* status is read from the I/O reg */
501 uint16_t status1 = readw(docptr + DOC_IOSPACE_DATA);
502 uint16_t status2 = readw(docptr + DOC_IOSPACE_DATA);
503 uint16_t status3 = readw(docptr + DOCG4_MYSTERY_REG);
504
505 dev_dbg(doc->dev, "docg4: %s: %02x %02x %02x\n",
506 __func__, status1, status2, status3);
507
508 if (status1 != DOCG4_PROGSTATUS_GOOD
509 || status2 != DOCG4_PROGSTATUS_GOOD_2
510 || status3 != DOCG4_PROGSTATUS_GOOD_2) {
511 doc->status = NAND_STATUS_FAIL;
512 dev_warn(doc->dev, "read_progstatus failed: "
513 "%02x, %02x, %02x\n", status1, status2, status3);
514 return -EIO;
515 }
516 return 0;
517}
518
519static int pageprog(struct mtd_info *mtd)
520{
521 /*
522 * Final step in writing a page. Writes the contents of its
523 * internal buffer out to the flash array, or some such.
524 */
525
526 struct nand_chip *nand = mtd->priv;
527 struct docg4_priv *doc = nand->priv;
528 void __iomem *docptr = doc->virtadr;
529 int retval = 0;
530
531 dev_dbg(doc->dev, "docg4: %s\n", __func__);
532
533 writew(DOCG4_SEQ_PAGEPROG, docptr + DOC_FLASHSEQUENCE);
534 writew(DOC_CMD_PROG_CYCLE2, docptr + DOC_FLASHCOMMAND);
535 write_nop(docptr);
536 write_nop(docptr);
537
538 /* Just busy-wait; usleep_range() slows things down noticeably. */
539 poll_status(doc);
540
541 writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
542 writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
543 writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
544 write_nop(docptr);
545 write_nop(docptr);
546 write_nop(docptr);
547 write_nop(docptr);
548 write_nop(docptr);
549
550 retval = read_progstatus(doc);
551 writew(0, docptr + DOC_DATAEND);
552 write_nop(docptr);
553 poll_status(doc);
554 write_nop(docptr);
555
556 return retval;
557}
558
559static void sequence_reset(struct mtd_info *mtd)
560{
561 /* common starting sequence for all operations */
562
563 struct nand_chip *nand = mtd->priv;
564 struct docg4_priv *doc = nand->priv;
565 void __iomem *docptr = doc->virtadr;
566
567 writew(DOC_CTRL_UNKNOWN | DOC_CTRL_CE, docptr + DOC_FLASHCONTROL);
568 writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
569 writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
570 write_nop(docptr);
571 write_nop(docptr);
572 poll_status(doc);
573 write_nop(docptr);
574}
575
576static void read_page_prologue(struct mtd_info *mtd, uint32_t docg4_addr)
577{
578 /* first step in reading a page */
579
580 struct nand_chip *nand = mtd->priv;
581 struct docg4_priv *doc = nand->priv;
582 void __iomem *docptr = doc->virtadr;
583
584 dev_dbg(doc->dev,
585 "docg4: %s: g4 page %08x\n", __func__, docg4_addr);
586
587 sequence_reset(mtd);
588
589 writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
590 writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
591 write_nop(docptr);
592
593 write_addr(doc, docg4_addr);
594
595 write_nop(docptr);
596 writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
597 write_nop(docptr);
598 write_nop(docptr);
599
600 poll_status(doc);
601}
602
603static void write_page_prologue(struct mtd_info *mtd, uint32_t docg4_addr)
604{
605 /* first step in writing a page */
606
607 struct nand_chip *nand = mtd->priv;
608 struct docg4_priv *doc = nand->priv;
609 void __iomem *docptr = doc->virtadr;
610
611 dev_dbg(doc->dev,
612 "docg4: %s: g4 addr: %x\n", __func__, docg4_addr);
613 sequence_reset(mtd);
614 writew(DOCG4_SEQ_PAGEWRITE, docptr + DOC_FLASHSEQUENCE);
615 writew(DOCG4_CMD_PAGEWRITE, docptr + DOC_FLASHCOMMAND);
616 write_nop(docptr);
617 write_addr(doc, docg4_addr);
618 write_nop(docptr);
619 write_nop(docptr);
620 poll_status(doc);
621}
622
623static uint32_t mtd_to_docg4_address(int page, int column)
624{
625 /*
626 * Convert mtd address to format used by the device, 32 bit packed.
627 *
628 * Some notes on G4 addressing... The M-Sys documentation on this device
629 * claims that pages are 2K in length, and indeed, the format of the
630 * address used by the device reflects that. But within each page are
631 * four 512 byte "sub-pages", each with its own oob data that is
632 * read/written immediately after the 512 bytes of page data. This oob
633 * data contains the ecc bytes for the preceeding 512 bytes.
634 *
635 * Rather than tell the mtd nand infrastructure that page size is 2k,
636 * with four sub-pages each, we engage in a little subterfuge and tell
637 * the infrastructure code that pages are 512 bytes in size. This is
638 * done because during the course of reverse-engineering the device, I
639 * never observed an instance where an entire 2K "page" was read or
640 * written as a unit. Each "sub-page" is always addressed individually,
641 * its data read/written, and ecc handled before the next "sub-page" is
642 * addressed.
643 *
644 * This requires us to convert addresses passed by the mtd nand
645 * infrastructure code to those used by the device.
646 *
647 * The address that is written to the device consists of four bytes: the
648 * first two are the 2k page number, and the second is the index into
649 * the page. The index is in terms of 16-bit half-words and includes
650 * the preceeding oob data, so e.g., the index into the second
651 * "sub-page" is 0x108, and the full device address of the start of mtd
652 * page 0x201 is 0x00800108.
653 */
654 int g4_page = page / 4; /* device's 2K page */
655 int g4_index = (page % 4) * 0x108 + column/2; /* offset into page */
656 return (g4_page << 16) | g4_index; /* pack */
657}
658
659static void docg4_command(struct mtd_info *mtd, unsigned command, int column,
660 int page_addr)
661{
662 /* handle standard nand commands */
663
664 struct nand_chip *nand = mtd->priv;
665 struct docg4_priv *doc = nand->priv;
666 uint32_t g4_addr = mtd_to_docg4_address(page_addr, column);
667
668 dev_dbg(doc->dev, "%s %x, page_addr=%x, column=%x\n",
669 __func__, command, page_addr, column);
670
671 /*
672 * Save the command and its arguments. This enables emulation of
673 * standard flash devices, and also some optimizations.
674 */
675 doc->last_command.command = command;
676 doc->last_command.column = column;
677 doc->last_command.page = page_addr;
678
679 switch (command) {
680
681 case NAND_CMD_RESET:
682 reset(mtd);
683 break;
684
685 case NAND_CMD_READ0:
686 read_page_prologue(mtd, g4_addr);
687 break;
688
689 case NAND_CMD_STATUS:
690 /* next call to read_byte() will expect a status */
691 break;
692
693 case NAND_CMD_SEQIN:
694 write_page_prologue(mtd, g4_addr);
695
696 /* hack for deferred write of oob bytes */
697 if (doc->oob_page == page_addr)
698 memcpy(nand->oob_poi, doc->oob_buf, 16);
699 break;
700
701 case NAND_CMD_PAGEPROG:
702 pageprog(mtd);
703 break;
704
705 /* we don't expect these, based on review of nand_base.c */
706 case NAND_CMD_READOOB:
707 case NAND_CMD_READID:
708 case NAND_CMD_ERASE1:
709 case NAND_CMD_ERASE2:
710 dev_warn(doc->dev, "docg4_command: "
711 "unexpected nand command 0x%x\n", command);
712 break;
713
714 }
715}
716
717static int read_page(struct mtd_info *mtd, struct nand_chip *nand,
718 uint8_t *buf, int page, bool use_ecc)
719{
720 struct docg4_priv *doc = nand->priv;
721 void __iomem *docptr = doc->virtadr;
722 uint16_t status, edc_err, *buf16;
723
724 dev_dbg(doc->dev, "%s: page %08x\n", __func__, page);
725
726 writew(DOC_ECCCONF0_READ_MODE |
727 DOC_ECCCONF0_ECC_ENABLE |
728 DOC_ECCCONF0_UNKNOWN |
729 DOCG4_BCH_SIZE,
730 docptr + DOC_ECCCONF0);
731 write_nop(docptr);
732 write_nop(docptr);
733 write_nop(docptr);
734 write_nop(docptr);
735 write_nop(docptr);
736
737 /* the 1st byte from the I/O reg is a status; the rest is page data */
738 status = readw(docptr + DOC_IOSPACE_DATA);
739 if (status & DOCG4_READ_ERROR) {
740 dev_err(doc->dev,
741 "docg4_read_page: bad status: 0x%02x\n", status);
742 writew(0, docptr + DOC_DATAEND);
743 return -EIO;
744 }
745
746 dev_dbg(doc->dev, "%s: status = 0x%x\n", __func__, status);
747
748 docg4_read_buf(mtd, buf, DOCG4_PAGE_SIZE); /* read the page data */
749
750 /*
751 * Diskonchips read oob immediately after a page read. Mtd
752 * infrastructure issues a separate command for reading oob after the
753 * page is read. So we save the oob bytes in a local buffer and just
754 * copy it if the next command reads oob from the same page.
755 */
756
757 /* first 14 oob bytes read from I/O reg */
758 docg4_read_buf(mtd, doc->oob_buf, 14);
759
760 /* last 2 read from another reg */
761 buf16 = (uint16_t *)(doc->oob_buf + 14);
762 *buf16 = readw(docptr + DOCG4_MYSTERY_REG);
763
764 write_nop(docptr);
765
766 if (likely(use_ecc == true)) {
767
768 /* read the register that tells us if bitflip(s) detected */
769 edc_err = readw(docptr + DOC_ECCCONF1);
770 edc_err = readw(docptr + DOC_ECCCONF1);
771 dev_dbg(doc->dev, "%s: edc_err = 0x%02x\n", __func__, edc_err);
772
773 /* If bitflips are reported, attempt to correct with ecc */
774 if (edc_err & DOC_ECCCONF1_BCH_SYNDROM_ERR) {
775 int bits_corrected = correct_data(mtd, buf, page);
776 if (bits_corrected == -EBADMSG)
777 mtd->ecc_stats.failed++;
778 else
779 mtd->ecc_stats.corrected += bits_corrected;
780 }
781 }
782
783 writew(0, docptr + DOC_DATAEND);
784 return 0;
785}
786
787
788static int docg4_read_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
789 uint8_t *buf, int page)
790{
791 return read_page(mtd, nand, buf, page, false);
792}
793
794static int docg4_read_page(struct mtd_info *mtd, struct nand_chip *nand,
795 uint8_t *buf, int page)
796{
797 return read_page(mtd, nand, buf, page, true);
798}
799
800static int docg4_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
801 int page, int sndcmd)
802{
803 struct docg4_priv *doc = nand->priv;
804 void __iomem *docptr = doc->virtadr;
805 uint16_t status;
806
807 dev_dbg(doc->dev, "%s: page %x\n", __func__, page);
808
809 /*
810 * Oob bytes are read as part of a normal page read. If the previous
811 * nand command was a read of the page whose oob is now being read, just
812 * copy the oob bytes that we saved in a local buffer and avoid a
813 * separate oob read.
814 */
815 if (doc->last_command.command == NAND_CMD_READ0 &&
816 doc->last_command.page == page) {
817 memcpy(nand->oob_poi, doc->oob_buf, 16);
818 return 0;
819 }
820
821 /*
822 * Separate read of oob data only.
823 */
824 docg4_command(mtd, NAND_CMD_READ0, nand->ecc.size, page);
825
826 writew(DOC_ECCCONF0_READ_MODE | DOCG4_OOB_SIZE, docptr + DOC_ECCCONF0);
827 write_nop(docptr);
828 write_nop(docptr);
829 write_nop(docptr);
830 write_nop(docptr);
831 write_nop(docptr);
832
833 /* the 1st byte from the I/O reg is a status; the rest is oob data */
834 status = readw(docptr + DOC_IOSPACE_DATA);
835 if (status & DOCG4_READ_ERROR) {
836 dev_warn(doc->dev,
837 "docg4_read_oob failed: status = 0x%02x\n", status);
838 return -EIO;
839 }
840
841 dev_dbg(doc->dev, "%s: status = 0x%x\n", __func__, status);
842
843 docg4_read_buf(mtd, nand->oob_poi, 16);
844
845 write_nop(docptr);
846 write_nop(docptr);
847 write_nop(docptr);
848 writew(0, docptr + DOC_DATAEND);
849 write_nop(docptr);
850
851 return 0;
852}
853
854static void docg4_erase_block(struct mtd_info *mtd, int page)
855{
856 struct nand_chip *nand = mtd->priv;
857 struct docg4_priv *doc = nand->priv;
858 void __iomem *docptr = doc->virtadr;
859 uint16_t g4_page;
860
861 dev_dbg(doc->dev, "%s: page %04x\n", __func__, page);
862
863 sequence_reset(mtd);
864
865 writew(DOCG4_SEQ_BLOCKERASE, docptr + DOC_FLASHSEQUENCE);
866 writew(DOC_CMD_PROG_BLOCK_ADDR, docptr + DOC_FLASHCOMMAND);
867 write_nop(docptr);
868
869 /* only 2 bytes of address are written to specify erase block */
870 g4_page = (uint16_t)(page / 4); /* to g4's 2k page addressing */
871 writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
872 g4_page >>= 8;
873 writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
874 write_nop(docptr);
875
876 /* start the erasure */
877 writew(DOC_CMD_ERASECYCLE2, docptr + DOC_FLASHCOMMAND);
878 write_nop(docptr);
879 write_nop(docptr);
880
881 usleep_range(500, 1000); /* erasure is long; take a snooze */
882 poll_status(doc);
883 writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
884 writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
885 writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
886 write_nop(docptr);
887 write_nop(docptr);
888 write_nop(docptr);
889 write_nop(docptr);
890 write_nop(docptr);
891
892 read_progstatus(doc);
893
894 writew(0, docptr + DOC_DATAEND);
895 write_nop(docptr);
896 poll_status(doc);
897 write_nop(docptr);
898}
899
900static void write_page(struct mtd_info *mtd, struct nand_chip *nand,
901 const uint8_t *buf, bool use_ecc)
902{
903 struct docg4_priv *doc = nand->priv;
904 void __iomem *docptr = doc->virtadr;
905 uint8_t ecc_buf[8];
906
907 dev_dbg(doc->dev, "%s...\n", __func__);
908
909 writew(DOC_ECCCONF0_ECC_ENABLE |
910 DOC_ECCCONF0_UNKNOWN |
911 DOCG4_BCH_SIZE,
912 docptr + DOC_ECCCONF0);
913 write_nop(docptr);
914
915 /* write the page data */
916 docg4_write_buf16(mtd, buf, DOCG4_PAGE_SIZE);
917
918 /* oob bytes 0 through 5 are written to I/O reg */
919 docg4_write_buf16(mtd, nand->oob_poi, 6);
920
921 /* oob byte 6 written to a separate reg */
922 writew(nand->oob_poi[6], docptr + DOCG4_OOB_6_7);
923
924 write_nop(docptr);
925 write_nop(docptr);
926
927 /* write hw-generated ecc bytes to oob */
928 if (likely(use_ecc == true)) {
929 /* oob byte 7 is hamming code */
930 uint8_t hamming = readb(docptr + DOC_HAMMINGPARITY);
931 hamming = readb(docptr + DOC_HAMMINGPARITY); /* 2nd read */
932 writew(hamming, docptr + DOCG4_OOB_6_7);
933 write_nop(docptr);
934
935 /* read the 7 bch bytes from ecc regs */
936 read_hw_ecc(docptr, ecc_buf);
937 ecc_buf[7] = 0; /* clear the "page written" flag */
938 }
939
940 /* write user-supplied bytes to oob */
941 else {
942 writew(nand->oob_poi[7], docptr + DOCG4_OOB_6_7);
943 write_nop(docptr);
944 memcpy(ecc_buf, &nand->oob_poi[8], 8);
945 }
946
947 docg4_write_buf16(mtd, ecc_buf, 8);
948 write_nop(docptr);
949 write_nop(docptr);
950 writew(0, docptr + DOC_DATAEND);
951 write_nop(docptr);
952}
953
954static void docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
955 const uint8_t *buf)
956{
957 return write_page(mtd, nand, buf, false);
958}
959
960static void docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand,
961 const uint8_t *buf)
962{
963 return write_page(mtd, nand, buf, true);
964}
965
966static int docg4_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
967 int page)
968{
969 /*
970 * Writing oob-only is not really supported, because MLC nand must write
971 * oob bytes at the same time as page data. Nonetheless, we save the
972 * oob buffer contents here, and then write it along with the page data
973 * if the same page is subsequently written. This allows user space
974 * utilities that write the oob data prior to the page data to work
975 * (e.g., nandwrite). The disdvantage is that, if the intention was to
976 * write oob only, the operation is quietly ignored. Also, oob can get
977 * corrupted if two concurrent processes are running nandwrite.
978 */
979
980 /* note that bytes 7..14 are hw generated hamming/ecc and overwritten */
981 struct docg4_priv *doc = nand->priv;
982 doc->oob_page = page;
983 memcpy(doc->oob_buf, nand->oob_poi, 16);
984 return 0;
985}
986
987static int __init read_factory_bbt(struct mtd_info *mtd)
988{
989 /*
990 * The device contains a read-only factory bad block table. Read it and
991 * update the memory-based bbt accordingly.
992 */
993
994 struct nand_chip *nand = mtd->priv;
995 struct docg4_priv *doc = nand->priv;
996 uint32_t g4_addr = mtd_to_docg4_address(DOCG4_FACTORY_BBT_PAGE, 0);
997 uint8_t *buf;
998 int i, block, status;
999
1000 buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
1001 if (buf == NULL)
1002 return -ENOMEM;
1003
1004 read_page_prologue(mtd, g4_addr);
1005 status = docg4_read_page(mtd, nand, buf, DOCG4_FACTORY_BBT_PAGE);
1006 if (status)
1007 goto exit;
1008
1009 /*
1010 * If no memory-based bbt was created, exit. This will happen if module
1011 * parameter ignore_badblocks is set. Then why even call this function?
1012 * For an unknown reason, block erase always fails if it's the first
1013 * operation after device power-up. The above read ensures it never is.
1014 * Ugly, I know.
1015 */
1016 if (nand->bbt == NULL) /* no memory-based bbt */
1017 goto exit;
1018
1019 /*
1020 * Parse factory bbt and update memory-based bbt. Factory bbt format is
1021 * simple: one bit per block, block numbers increase left to right (msb
1022 * to lsb). Bit clear means bad block.
1023 */
1024 for (i = block = 0; block < DOCG4_NUMBLOCKS; block += 8, i++) {
1025 int bitnum;
1026 unsigned long bits = ~buf[i];
1027 for_each_set_bit(bitnum, &bits, 8) {
1028 int badblock = block + 7 - bitnum;
1029 nand->bbt[badblock / 4] |=
1030 0x03 << ((badblock % 4) * 2);
1031 mtd->ecc_stats.badblocks++;
1032 dev_notice(doc->dev, "factory-marked bad block: %d\n",
1033 badblock);
1034 }
1035 }
1036 exit:
1037 kfree(buf);
1038 return status;
1039}
1040
1041static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs)
1042{
1043 /*
1044 * Mark a block as bad. Bad blocks are marked in the oob area of the
1045 * first page of the block. The default scan_bbt() in the nand
1046 * infrastructure code works fine for building the memory-based bbt
1047 * during initialization, as does the nand infrastructure function that
1048 * checks if a block is bad by reading the bbt. This function replaces
1049 * the nand default because writes to oob-only are not supported.
1050 */
1051
1052 int ret, i;
1053 uint8_t *buf;
1054 struct nand_chip *nand = mtd->priv;
1055 struct docg4_priv *doc = nand->priv;
1056 struct nand_bbt_descr *bbtd = nand->badblock_pattern;
1057 int block = (int)(ofs >> nand->bbt_erase_shift);
1058 int page = (int)(ofs >> nand->page_shift);
1059 uint32_t g4_addr = mtd_to_docg4_address(page, 0);
1060
1061 dev_dbg(doc->dev, "%s: %08llx\n", __func__, ofs);
1062
1063 if (unlikely(ofs & (DOCG4_BLOCK_SIZE - 1)))
1064 dev_warn(doc->dev, "%s: ofs %llx not start of block!\n",
1065 __func__, ofs);
1066
1067 /* allocate blank buffer for page data */
1068 buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
1069 if (buf == NULL)
1070 return -ENOMEM;
1071
1072 /* update bbt in memory */
1073 nand->bbt[block / 4] |= 0x01 << ((block & 0x03) * 2);
1074
1075 /* write bit-wise negation of pattern to oob buffer */
1076 memset(nand->oob_poi, 0xff, mtd->oobsize);
1077 for (i = 0; i < bbtd->len; i++)
1078 nand->oob_poi[bbtd->offs + i] = ~bbtd->pattern[i];
1079
1080 /* write first page of block */
1081 write_page_prologue(mtd, g4_addr);
1082 docg4_write_page(mtd, nand, buf);
1083 ret = pageprog(mtd);
1084 if (!ret)
1085 mtd->ecc_stats.badblocks++;
1086
1087 kfree(buf);
1088
1089 return ret;
1090}
1091
1092static int docg4_block_neverbad(struct mtd_info *mtd, loff_t ofs, int getchip)
1093{
1094 /* only called when module_param ignore_badblocks is set */
1095 return 0;
1096}
1097
1098static int docg4_suspend(struct platform_device *pdev, pm_message_t state)
1099{
1100 /*
1101 * Put the device into "deep power-down" mode. Note that CE# must be
1102 * deasserted for this to take effect. The xscale, e.g., can be
1103 * configured to float this signal when the processor enters power-down,
1104 * and a suitable pull-up ensures its deassertion.
1105 */
1106
1107 int i;
1108 uint8_t pwr_down;
1109 struct docg4_priv *doc = platform_get_drvdata(pdev);
1110 void __iomem *docptr = doc->virtadr;
1111
1112 dev_dbg(doc->dev, "%s...\n", __func__);
1113
1114 /* poll the register that tells us we're ready to go to sleep */
1115 for (i = 0; i < 10; i++) {
1116 pwr_down = readb(docptr + DOC_POWERMODE);
1117 if (pwr_down & DOC_POWERDOWN_READY)
1118 break;
1119 usleep_range(1000, 4000);
1120 }
1121
1122 if (pwr_down & DOC_POWERDOWN_READY) {
1123 dev_err(doc->dev, "suspend failed; "
1124 "timeout polling DOC_POWERDOWN_READY\n");
1125 return -EIO;
1126 }
1127
1128 writew(DOC_ASICMODE_POWERDOWN | DOC_ASICMODE_MDWREN,
1129 docptr + DOC_ASICMODE);
1130 writew(~(DOC_ASICMODE_POWERDOWN | DOC_ASICMODE_MDWREN),
1131 docptr + DOC_ASICMODECONFIRM);
1132
1133 write_nop(docptr);
1134
1135 return 0;
1136}
1137
1138static int docg4_resume(struct platform_device *pdev)
1139{
1140
1141 /*
1142 * Exit power-down. Twelve consecutive reads of the address below
1143 * accomplishes this, assuming CE# has been asserted.
1144 */
1145
1146 struct docg4_priv *doc = platform_get_drvdata(pdev);
1147 void __iomem *docptr = doc->virtadr;
1148 int i;
1149
1150 dev_dbg(doc->dev, "%s...\n", __func__);
1151
1152 for (i = 0; i < 12; i++)
1153 readb(docptr + 0x1fff);
1154
1155 return 0;
1156}
1157
1158static void __init init_mtd_structs(struct mtd_info *mtd)
1159{
1160 /* initialize mtd and nand data structures */
1161
1162 /*
1163 * Note that some of the following initializations are not usually
1164 * required within a nand driver because they are performed by the nand
1165 * infrastructure code as part of nand_scan(). In this case they need
1166 * to be initialized here because we skip call to nand_scan_ident() (the
1167 * first half of nand_scan()). The call to nand_scan_ident() is skipped
1168 * because for this device the chip id is not read in the manner of a
1169 * standard nand device. Unfortunately, nand_scan_ident() does other
1170 * things as well, such as call nand_set_defaults().
1171 */
1172
1173 struct nand_chip *nand = mtd->priv;
1174 struct docg4_priv *doc = nand->priv;
1175
1176 mtd->size = DOCG4_CHIP_SIZE;
1177 mtd->name = "Msys_Diskonchip_G4";
1178 mtd->writesize = DOCG4_PAGE_SIZE;
1179 mtd->erasesize = DOCG4_BLOCK_SIZE;
1180 mtd->oobsize = DOCG4_OOB_SIZE;
1181 nand->chipsize = DOCG4_CHIP_SIZE;
1182 nand->chip_shift = DOCG4_CHIP_SHIFT;
1183 nand->bbt_erase_shift = nand->phys_erase_shift = DOCG4_ERASE_SHIFT;
1184 nand->chip_delay = 20;
1185 nand->page_shift = DOCG4_PAGE_SHIFT;
1186 nand->pagemask = 0x3ffff;
1187 nand->badblockpos = NAND_LARGE_BADBLOCK_POS;
1188 nand->badblockbits = 8;
1189 nand->ecc.layout = &docg4_oobinfo;
1190 nand->ecc.mode = NAND_ECC_HW_SYNDROME;
1191 nand->ecc.size = DOCG4_PAGE_SIZE;
1192 nand->ecc.prepad = 8;
1193 nand->ecc.bytes = 8;
1194 nand->ecc.strength = DOCG4_T;
1195 nand->options =
1196 NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE | NAND_NO_AUTOINCR;
1197 nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA;
1198 nand->controller = &nand->hwcontrol;
1199 spin_lock_init(&nand->controller->lock);
1200 init_waitqueue_head(&nand->controller->wq);
1201
1202 /* methods */
1203 nand->cmdfunc = docg4_command;
1204 nand->waitfunc = docg4_wait;
1205 nand->select_chip = docg4_select_chip;
1206 nand->read_byte = docg4_read_byte;
1207 nand->block_markbad = docg4_block_markbad;
1208 nand->read_buf = docg4_read_buf;
1209 nand->write_buf = docg4_write_buf16;
1210 nand->scan_bbt = nand_default_bbt;
1211 nand->erase_cmd = docg4_erase_block;
1212 nand->ecc.read_page = docg4_read_page;
1213 nand->ecc.write_page = docg4_write_page;
1214 nand->ecc.read_page_raw = docg4_read_page_raw;
1215 nand->ecc.write_page_raw = docg4_write_page_raw;
1216 nand->ecc.read_oob = docg4_read_oob;
1217 nand->ecc.write_oob = docg4_write_oob;
1218
1219 /*
1220 * The way the nand infrastructure code is written, a memory-based bbt
1221 * is not created if NAND_SKIP_BBTSCAN is set. With no memory bbt,
1222 * nand->block_bad() is used. So when ignoring bad blocks, we skip the
1223 * scan and define a dummy block_bad() which always returns 0.
1224 */
1225 if (ignore_badblocks) {
1226 nand->options |= NAND_SKIP_BBTSCAN;
1227 nand->block_bad = docg4_block_neverbad;
1228 }
1229
1230}
1231
1232static int __init read_id_reg(struct mtd_info *mtd)
1233{
1234 struct nand_chip *nand = mtd->priv;
1235 struct docg4_priv *doc = nand->priv;
1236 void __iomem *docptr = doc->virtadr;
1237 uint16_t id1, id2;
1238
1239 /* check for presence of g4 chip by reading id registers */
1240 id1 = readw(docptr + DOC_CHIPID);
1241 id1 = readw(docptr + DOCG4_MYSTERY_REG);
1242 id2 = readw(docptr + DOC_CHIPID_INV);
1243 id2 = readw(docptr + DOCG4_MYSTERY_REG);
1244
1245 if (id1 == DOCG4_IDREG1_VALUE && id2 == DOCG4_IDREG2_VALUE) {
1246 dev_info(doc->dev,
1247 "NAND device: 128MiB Diskonchip G4 detected\n");
1248 return 0;
1249 }
1250
1251 return -ENODEV;
1252}
1253
1254static char const *part_probes[] = { "cmdlinepart", "saftlpart", NULL };
1255
1256static int __init probe_docg4(struct platform_device *pdev)
1257{
1258 struct mtd_info *mtd;
1259 struct nand_chip *nand;
1260 void __iomem *virtadr;
1261 struct docg4_priv *doc;
1262 int len, retval;
1263 struct resource *r;
1264 struct device *dev = &pdev->dev;
1265
1266 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1267 if (r == NULL) {
1268 dev_err(dev, "no io memory resource defined!\n");
1269 return -ENODEV;
1270 }
1271
1272 virtadr = ioremap(r->start, resource_size(r));
1273 if (!virtadr) {
1274 dev_err(dev, "Diskonchip ioremap failed: %pR\n", r);
1275 return -EIO;
1276 }
1277
1278 len = sizeof(struct mtd_info) + sizeof(struct nand_chip) +
1279 sizeof(struct docg4_priv);
1280 mtd = kzalloc(len, GFP_KERNEL);
1281 if (mtd == NULL) {
1282 retval = -ENOMEM;
1283 goto fail;
1284 }
1285 nand = (struct nand_chip *) (mtd + 1);
1286 doc = (struct docg4_priv *) (nand + 1);
1287 mtd->priv = nand;
1288 nand->priv = doc;
1289 mtd->owner = THIS_MODULE;
1290 doc->virtadr = virtadr;
1291 doc->dev = dev;
1292
1293 init_mtd_structs(mtd);
1294
1295 /* initialize kernel bch algorithm */
1296 doc->bch = init_bch(DOCG4_M, DOCG4_T, DOCG4_PRIMITIVE_POLY);
1297 if (doc->bch == NULL) {
1298 retval = -EINVAL;
1299 goto fail;
1300 }
1301
1302 platform_set_drvdata(pdev, doc);
1303
1304 reset(mtd);
1305 retval = read_id_reg(mtd);
1306 if (retval == -ENODEV) {
1307 dev_warn(dev, "No diskonchip G4 device found.\n");
1308 goto fail;
1309 }
1310
1311 retval = nand_scan_tail(mtd);
1312 if (retval)
1313 goto fail;
1314
1315 retval = read_factory_bbt(mtd);
1316 if (retval)
1317 goto fail;
1318
1319 retval = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
1320 if (retval)
1321 goto fail;
1322
1323 doc->mtd = mtd;
1324 return 0;
1325
1326 fail:
1327 iounmap(virtadr);
1328 if (mtd) {
1329 /* re-declarations avoid compiler warning */
1330 struct nand_chip *nand = mtd->priv;
1331 struct docg4_priv *doc = nand->priv;
1332 nand_release(mtd); /* deletes partitions and mtd devices */
1333 platform_set_drvdata(pdev, NULL);
1334 free_bch(doc->bch);
1335 kfree(mtd);
1336 }
1337
1338 return retval;
1339}
1340
1341static int __exit cleanup_docg4(struct platform_device *pdev)
1342{
1343 struct docg4_priv *doc = platform_get_drvdata(pdev);
1344 nand_release(doc->mtd);
1345 platform_set_drvdata(pdev, NULL);
1346 free_bch(doc->bch);
1347 kfree(doc->mtd);
1348 iounmap(doc->virtadr);
1349 return 0;
1350}
1351
1352static struct platform_driver docg4_driver = {
1353 .driver = {
1354 .name = "docg4",
1355 .owner = THIS_MODULE,
1356 },
1357 .suspend = docg4_suspend,
1358 .resume = docg4_resume,
1359 .remove = __exit_p(cleanup_docg4),
1360};
1361
1362static int __init docg4_init(void)
1363{
1364 return platform_driver_probe(&docg4_driver, probe_docg4);
1365}
1366
1367static void __exit docg4_exit(void)
1368{
1369 platform_driver_unregister(&docg4_driver);
1370}
1371
1372module_init(docg4_init);
1373module_exit(docg4_exit);
1374
1375MODULE_LICENSE("GPL");
1376MODULE_AUTHOR("Mike Dunn");
1377MODULE_DESCRIPTION("M-Systems DiskOnChip G4 device driver");
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 7195ee6efe12..80b5264f0a32 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -813,6 +813,12 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
813 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0; 813 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
814 chip->ecc.size = 512; 814 chip->ecc.size = 512;
815 chip->ecc.bytes = 3; 815 chip->ecc.bytes = 3;
816 chip->ecc.strength = 1;
817 /*
818 * FIXME: can hardware ecc correct 4 bitflips if page size is
819 * 2k? Then does hardware report number of corrections for this
820 * case? If so, ecc_stats reporting needs to be fixed as well.
821 */
816 } else { 822 } else {
817 /* otherwise fall back to default software ECC */ 823 /* otherwise fall back to default software ECC */
818 chip->ecc.mode = NAND_ECC_SOFT; 824 chip->ecc.mode = NAND_ECC_SOFT;
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index e53b76064133..1b8330e1155a 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -17,6 +17,10 @@
17 */ 17 */
18 18
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/completion.h>
21#include <linux/dmaengine.h>
22#include <linux/dma-direction.h>
23#include <linux/dma-mapping.h>
20#include <linux/err.h> 24#include <linux/err.h>
21#include <linux/init.h> 25#include <linux/init.h>
22#include <linux/module.h> 26#include <linux/module.h>
@@ -27,6 +31,7 @@
27#include <linux/mtd/nand.h> 31#include <linux/mtd/nand.h>
28#include <linux/mtd/nand_ecc.h> 32#include <linux/mtd/nand_ecc.h>
29#include <linux/platform_device.h> 33#include <linux/platform_device.h>
34#include <linux/of.h>
30#include <linux/mtd/partitions.h> 35#include <linux/mtd/partitions.h>
31#include <linux/io.h> 36#include <linux/io.h>
32#include <linux/slab.h> 37#include <linux/slab.h>
@@ -34,7 +39,7 @@
34#include <linux/amba/bus.h> 39#include <linux/amba/bus.h>
35#include <mtd/mtd-abi.h> 40#include <mtd/mtd-abi.h>
36 41
37static struct nand_ecclayout fsmc_ecc1_layout = { 42static struct nand_ecclayout fsmc_ecc1_128_layout = {
38 .eccbytes = 24, 43 .eccbytes = 24,
39 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, 44 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
40 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, 45 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
@@ -50,7 +55,127 @@ static struct nand_ecclayout fsmc_ecc1_layout = {
50 } 55 }
51}; 56};
52 57
53static struct nand_ecclayout fsmc_ecc4_lp_layout = { 58static struct nand_ecclayout fsmc_ecc1_64_layout = {
59 .eccbytes = 12,
60 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52},
61 .oobfree = {
62 {.offset = 8, .length = 8},
63 {.offset = 24, .length = 8},
64 {.offset = 40, .length = 8},
65 {.offset = 56, .length = 8},
66 }
67};
68
69static struct nand_ecclayout fsmc_ecc1_16_layout = {
70 .eccbytes = 3,
71 .eccpos = {2, 3, 4},
72 .oobfree = {
73 {.offset = 8, .length = 8},
74 }
75};
76
77/*
78 * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes
79 * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46
80 * bytes are free for use.
81 */
82static struct nand_ecclayout fsmc_ecc4_256_layout = {
83 .eccbytes = 208,
84 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
85 9, 10, 11, 12, 13, 14,
86 18, 19, 20, 21, 22, 23, 24,
87 25, 26, 27, 28, 29, 30,
88 34, 35, 36, 37, 38, 39, 40,
89 41, 42, 43, 44, 45, 46,
90 50, 51, 52, 53, 54, 55, 56,
91 57, 58, 59, 60, 61, 62,
92 66, 67, 68, 69, 70, 71, 72,
93 73, 74, 75, 76, 77, 78,
94 82, 83, 84, 85, 86, 87, 88,
95 89, 90, 91, 92, 93, 94,
96 98, 99, 100, 101, 102, 103, 104,
97 105, 106, 107, 108, 109, 110,
98 114, 115, 116, 117, 118, 119, 120,
99 121, 122, 123, 124, 125, 126,
100 130, 131, 132, 133, 134, 135, 136,
101 137, 138, 139, 140, 141, 142,
102 146, 147, 148, 149, 150, 151, 152,
103 153, 154, 155, 156, 157, 158,
104 162, 163, 164, 165, 166, 167, 168,
105 169, 170, 171, 172, 173, 174,
106 178, 179, 180, 181, 182, 183, 184,
107 185, 186, 187, 188, 189, 190,
108 194, 195, 196, 197, 198, 199, 200,
109 201, 202, 203, 204, 205, 206,
110 210, 211, 212, 213, 214, 215, 216,
111 217, 218, 219, 220, 221, 222,
112 226, 227, 228, 229, 230, 231, 232,
113 233, 234, 235, 236, 237, 238,
114 242, 243, 244, 245, 246, 247, 248,
115 249, 250, 251, 252, 253, 254
116 },
117 .oobfree = {
118 {.offset = 15, .length = 3},
119 {.offset = 31, .length = 3},
120 {.offset = 47, .length = 3},
121 {.offset = 63, .length = 3},
122 {.offset = 79, .length = 3},
123 {.offset = 95, .length = 3},
124 {.offset = 111, .length = 3},
125 {.offset = 127, .length = 3},
126 {.offset = 143, .length = 3},
127 {.offset = 159, .length = 3},
128 {.offset = 175, .length = 3},
129 {.offset = 191, .length = 3},
130 {.offset = 207, .length = 3},
131 {.offset = 223, .length = 3},
132 {.offset = 239, .length = 3},
133 {.offset = 255, .length = 1}
134 }
135};
136
137/*
138 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
139 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
140 * bytes are free for use.
141 */
142static struct nand_ecclayout fsmc_ecc4_224_layout = {
143 .eccbytes = 104,
144 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
145 9, 10, 11, 12, 13, 14,
146 18, 19, 20, 21, 22, 23, 24,
147 25, 26, 27, 28, 29, 30,
148 34, 35, 36, 37, 38, 39, 40,
149 41, 42, 43, 44, 45, 46,
150 50, 51, 52, 53, 54, 55, 56,
151 57, 58, 59, 60, 61, 62,
152 66, 67, 68, 69, 70, 71, 72,
153 73, 74, 75, 76, 77, 78,
154 82, 83, 84, 85, 86, 87, 88,
155 89, 90, 91, 92, 93, 94,
156 98, 99, 100, 101, 102, 103, 104,
157 105, 106, 107, 108, 109, 110,
158 114, 115, 116, 117, 118, 119, 120,
159 121, 122, 123, 124, 125, 126
160 },
161 .oobfree = {
162 {.offset = 15, .length = 3},
163 {.offset = 31, .length = 3},
164 {.offset = 47, .length = 3},
165 {.offset = 63, .length = 3},
166 {.offset = 79, .length = 3},
167 {.offset = 95, .length = 3},
168 {.offset = 111, .length = 3},
169 {.offset = 127, .length = 97}
170 }
171};
172
173/*
174 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
175 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
176 * bytes are free for use.
177 */
178static struct nand_ecclayout fsmc_ecc4_128_layout = {
54 .eccbytes = 104, 179 .eccbytes = 104,
55 .eccpos = { 2, 3, 4, 5, 6, 7, 8, 180 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
56 9, 10, 11, 12, 13, 14, 181 9, 10, 11, 12, 13, 14,
@@ -82,6 +207,45 @@ static struct nand_ecclayout fsmc_ecc4_lp_layout = {
82}; 207};
83 208
84/* 209/*
210 * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of
211 * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10
212 * bytes are free for use.
213 */
214static struct nand_ecclayout fsmc_ecc4_64_layout = {
215 .eccbytes = 52,
216 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
217 9, 10, 11, 12, 13, 14,
218 18, 19, 20, 21, 22, 23, 24,
219 25, 26, 27, 28, 29, 30,
220 34, 35, 36, 37, 38, 39, 40,
221 41, 42, 43, 44, 45, 46,
222 50, 51, 52, 53, 54, 55, 56,
223 57, 58, 59, 60, 61, 62,
224 },
225 .oobfree = {
226 {.offset = 15, .length = 3},
227 {.offset = 31, .length = 3},
228 {.offset = 47, .length = 3},
229 {.offset = 63, .length = 1},
230 }
231};
232
233/*
234 * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of
235 * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One
236 * byte is free for use.
237 */
238static struct nand_ecclayout fsmc_ecc4_16_layout = {
239 .eccbytes = 13,
240 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
241 9, 10, 11, 12, 13, 14
242 },
243 .oobfree = {
244 {.offset = 15, .length = 1},
245 }
246};
247
248/*
85 * ECC placement definitions in oobfree type format. 249 * ECC placement definitions in oobfree type format.
86 * There are 13 bytes of ecc for every 512 byte block and it has to be read 250 * There are 13 bytes of ecc for every 512 byte block and it has to be read
87 * consecutively and immediately after the 512 byte data block for hardware to 251 * consecutively and immediately after the 512 byte data block for hardware to
@@ -103,16 +267,6 @@ static struct fsmc_eccplace fsmc_ecc4_lp_place = {
103 } 267 }
104}; 268};
105 269
106static struct nand_ecclayout fsmc_ecc4_sp_layout = {
107 .eccbytes = 13,
108 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
109 9, 10, 11, 12, 13, 14
110 },
111 .oobfree = {
112 {.offset = 15, .length = 1},
113 }
114};
115
116static struct fsmc_eccplace fsmc_ecc4_sp_place = { 270static struct fsmc_eccplace fsmc_ecc4_sp_place = {
117 .eccplace = { 271 .eccplace = {
118 {.offset = 0, .length = 4}, 272 {.offset = 0, .length = 4},
@@ -120,75 +274,24 @@ static struct fsmc_eccplace fsmc_ecc4_sp_place = {
120 } 274 }
121}; 275};
122 276
123/*
124 * Default partition tables to be used if the partition information not
125 * provided through platform data.
126 *
127 * Default partition layout for small page(= 512 bytes) devices
128 * Size for "Root file system" is updated in driver based on actual device size
129 */
130static struct mtd_partition partition_info_16KB_blk[] = {
131 {
132 .name = "X-loader",
133 .offset = 0,
134 .size = 4*0x4000,
135 },
136 {
137 .name = "U-Boot",
138 .offset = 0x10000,
139 .size = 20*0x4000,
140 },
141 {
142 .name = "Kernel",
143 .offset = 0x60000,
144 .size = 256*0x4000,
145 },
146 {
147 .name = "Root File System",
148 .offset = 0x460000,
149 .size = MTDPART_SIZ_FULL,
150 },
151};
152
153/*
154 * Default partition layout for large page(> 512 bytes) devices
155 * Size for "Root file system" is updated in driver based on actual device size
156 */
157static struct mtd_partition partition_info_128KB_blk[] = {
158 {
159 .name = "X-loader",
160 .offset = 0,
161 .size = 4*0x20000,
162 },
163 {
164 .name = "U-Boot",
165 .offset = 0x80000,
166 .size = 12*0x20000,
167 },
168 {
169 .name = "Kernel",
170 .offset = 0x200000,
171 .size = 48*0x20000,
172 },
173 {
174 .name = "Root File System",
175 .offset = 0x800000,
176 .size = MTDPART_SIZ_FULL,
177 },
178};
179
180
181/** 277/**
182 * struct fsmc_nand_data - structure for FSMC NAND device state 278 * struct fsmc_nand_data - structure for FSMC NAND device state
183 * 279 *
184 * @pid: Part ID on the AMBA PrimeCell format 280 * @pid: Part ID on the AMBA PrimeCell format
185 * @mtd: MTD info for a NAND flash. 281 * @mtd: MTD info for a NAND flash.
186 * @nand: Chip related info for a NAND flash. 282 * @nand: Chip related info for a NAND flash.
283 * @partitions: Partition info for a NAND Flash.
284 * @nr_partitions: Total number of partition of a NAND flash.
187 * 285 *
188 * @ecc_place: ECC placing locations in oobfree type format. 286 * @ecc_place: ECC placing locations in oobfree type format.
189 * @bank: Bank number for probed device. 287 * @bank: Bank number for probed device.
190 * @clk: Clock structure for FSMC. 288 * @clk: Clock structure for FSMC.
191 * 289 *
290 * @read_dma_chan: DMA channel for read access
291 * @write_dma_chan: DMA channel for write access to NAND
292 * @dma_access_complete: Completion structure
293 *
294 * @data_pa: NAND Physical port for Data.
192 * @data_va: NAND port for Data. 295 * @data_va: NAND port for Data.
193 * @cmd_va: NAND port for Command. 296 * @cmd_va: NAND port for Command.
194 * @addr_va: NAND port for Address. 297 * @addr_va: NAND port for Address.
@@ -198,16 +301,23 @@ struct fsmc_nand_data {
198 u32 pid; 301 u32 pid;
199 struct mtd_info mtd; 302 struct mtd_info mtd;
200 struct nand_chip nand; 303 struct nand_chip nand;
304 struct mtd_partition *partitions;
305 unsigned int nr_partitions;
201 306
202 struct fsmc_eccplace *ecc_place; 307 struct fsmc_eccplace *ecc_place;
203 unsigned int bank; 308 unsigned int bank;
309 struct device *dev;
310 enum access_mode mode;
204 struct clk *clk; 311 struct clk *clk;
205 312
206 struct resource *resregs; 313 /* DMA related objects */
207 struct resource *rescmd; 314 struct dma_chan *read_dma_chan;
208 struct resource *resaddr; 315 struct dma_chan *write_dma_chan;
209 struct resource *resdata; 316 struct completion dma_access_complete;
317
318 struct fsmc_nand_timings *dev_timings;
210 319
320 dma_addr_t data_pa;
211 void __iomem *data_va; 321 void __iomem *data_va;
212 void __iomem *cmd_va; 322 void __iomem *cmd_va;
213 void __iomem *addr_va; 323 void __iomem *addr_va;
@@ -251,28 +361,29 @@ static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
251 struct nand_chip *this = mtd->priv; 361 struct nand_chip *this = mtd->priv;
252 struct fsmc_nand_data *host = container_of(mtd, 362 struct fsmc_nand_data *host = container_of(mtd,
253 struct fsmc_nand_data, mtd); 363 struct fsmc_nand_data, mtd);
254 struct fsmc_regs *regs = host->regs_va; 364 void *__iomem *regs = host->regs_va;
255 unsigned int bank = host->bank; 365 unsigned int bank = host->bank;
256 366
257 if (ctrl & NAND_CTRL_CHANGE) { 367 if (ctrl & NAND_CTRL_CHANGE) {
368 u32 pc;
369
258 if (ctrl & NAND_CLE) { 370 if (ctrl & NAND_CLE) {
259 this->IO_ADDR_R = (void __iomem *)host->cmd_va; 371 this->IO_ADDR_R = host->cmd_va;
260 this->IO_ADDR_W = (void __iomem *)host->cmd_va; 372 this->IO_ADDR_W = host->cmd_va;
261 } else if (ctrl & NAND_ALE) { 373 } else if (ctrl & NAND_ALE) {
262 this->IO_ADDR_R = (void __iomem *)host->addr_va; 374 this->IO_ADDR_R = host->addr_va;
263 this->IO_ADDR_W = (void __iomem *)host->addr_va; 375 this->IO_ADDR_W = host->addr_va;
264 } else { 376 } else {
265 this->IO_ADDR_R = (void __iomem *)host->data_va; 377 this->IO_ADDR_R = host->data_va;
266 this->IO_ADDR_W = (void __iomem *)host->data_va; 378 this->IO_ADDR_W = host->data_va;
267 } 379 }
268 380
269 if (ctrl & NAND_NCE) { 381 pc = readl(FSMC_NAND_REG(regs, bank, PC));
270 writel(readl(&regs->bank_regs[bank].pc) | FSMC_ENABLE, 382 if (ctrl & NAND_NCE)
271 &regs->bank_regs[bank].pc); 383 pc |= FSMC_ENABLE;
272 } else { 384 else
273 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ENABLE, 385 pc &= ~FSMC_ENABLE;
274 &regs->bank_regs[bank].pc); 386 writel(pc, FSMC_NAND_REG(regs, bank, PC));
275 }
276 } 387 }
277 388
278 mb(); 389 mb();
@@ -287,22 +398,42 @@ static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
287 * This routine initializes timing parameters related to NAND memory access in 398 * This routine initializes timing parameters related to NAND memory access in
288 * FSMC registers 399 * FSMC registers
289 */ 400 */
290static void __init fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank, 401static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
291 uint32_t busw) 402 uint32_t busw, struct fsmc_nand_timings *timings)
292{ 403{
293 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON; 404 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
405 uint32_t tclr, tar, thiz, thold, twait, tset;
406 struct fsmc_nand_timings *tims;
407 struct fsmc_nand_timings default_timings = {
408 .tclr = FSMC_TCLR_1,
409 .tar = FSMC_TAR_1,
410 .thiz = FSMC_THIZ_1,
411 .thold = FSMC_THOLD_4,
412 .twait = FSMC_TWAIT_6,
413 .tset = FSMC_TSET_0,
414 };
415
416 if (timings)
417 tims = timings;
418 else
419 tims = &default_timings;
420
421 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
422 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
423 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
424 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
425 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
426 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
294 427
295 if (busw) 428 if (busw)
296 writel(value | FSMC_DEVWID_16, &regs->bank_regs[bank].pc); 429 writel(value | FSMC_DEVWID_16, FSMC_NAND_REG(regs, bank, PC));
297 else 430 else
298 writel(value | FSMC_DEVWID_8, &regs->bank_regs[bank].pc); 431 writel(value | FSMC_DEVWID_8, FSMC_NAND_REG(regs, bank, PC));
299 432
300 writel(readl(&regs->bank_regs[bank].pc) | FSMC_TCLR_1 | FSMC_TAR_1, 433 writel(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
301 &regs->bank_regs[bank].pc); 434 FSMC_NAND_REG(regs, bank, PC));
302 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, 435 writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, COMM));
303 &regs->bank_regs[bank].comm); 436 writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, ATTRIB));
304 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
305 &regs->bank_regs[bank].attrib);
306} 437}
307 438
308/* 439/*
@@ -312,15 +443,15 @@ static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
312{ 443{
313 struct fsmc_nand_data *host = container_of(mtd, 444 struct fsmc_nand_data *host = container_of(mtd,
314 struct fsmc_nand_data, mtd); 445 struct fsmc_nand_data, mtd);
315 struct fsmc_regs *regs = host->regs_va; 446 void __iomem *regs = host->regs_va;
316 uint32_t bank = host->bank; 447 uint32_t bank = host->bank;
317 448
318 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256, 449 writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
319 &regs->bank_regs[bank].pc); 450 FSMC_NAND_REG(regs, bank, PC));
320 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ECCEN, 451 writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
321 &regs->bank_regs[bank].pc); 452 FSMC_NAND_REG(regs, bank, PC));
322 writel(readl(&regs->bank_regs[bank].pc) | FSMC_ECCEN, 453 writel(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
323 &regs->bank_regs[bank].pc); 454 FSMC_NAND_REG(regs, bank, PC));
324} 455}
325 456
326/* 457/*
@@ -333,37 +464,42 @@ static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
333{ 464{
334 struct fsmc_nand_data *host = container_of(mtd, 465 struct fsmc_nand_data *host = container_of(mtd,
335 struct fsmc_nand_data, mtd); 466 struct fsmc_nand_data, mtd);
336 struct fsmc_regs *regs = host->regs_va; 467 void __iomem *regs = host->regs_va;
337 uint32_t bank = host->bank; 468 uint32_t bank = host->bank;
338 uint32_t ecc_tmp; 469 uint32_t ecc_tmp;
339 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT; 470 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
340 471
341 do { 472 do {
342 if (readl(&regs->bank_regs[bank].sts) & FSMC_CODE_RDY) 473 if (readl(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
343 break; 474 break;
344 else 475 else
345 cond_resched(); 476 cond_resched();
346 } while (!time_after_eq(jiffies, deadline)); 477 } while (!time_after_eq(jiffies, deadline));
347 478
348 ecc_tmp = readl(&regs->bank_regs[bank].ecc1); 479 if (time_after_eq(jiffies, deadline)) {
480 dev_err(host->dev, "calculate ecc timed out\n");
481 return -ETIMEDOUT;
482 }
483
484 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
349 ecc[0] = (uint8_t) (ecc_tmp >> 0); 485 ecc[0] = (uint8_t) (ecc_tmp >> 0);
350 ecc[1] = (uint8_t) (ecc_tmp >> 8); 486 ecc[1] = (uint8_t) (ecc_tmp >> 8);
351 ecc[2] = (uint8_t) (ecc_tmp >> 16); 487 ecc[2] = (uint8_t) (ecc_tmp >> 16);
352 ecc[3] = (uint8_t) (ecc_tmp >> 24); 488 ecc[3] = (uint8_t) (ecc_tmp >> 24);
353 489
354 ecc_tmp = readl(&regs->bank_regs[bank].ecc2); 490 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC2));
355 ecc[4] = (uint8_t) (ecc_tmp >> 0); 491 ecc[4] = (uint8_t) (ecc_tmp >> 0);
356 ecc[5] = (uint8_t) (ecc_tmp >> 8); 492 ecc[5] = (uint8_t) (ecc_tmp >> 8);
357 ecc[6] = (uint8_t) (ecc_tmp >> 16); 493 ecc[6] = (uint8_t) (ecc_tmp >> 16);
358 ecc[7] = (uint8_t) (ecc_tmp >> 24); 494 ecc[7] = (uint8_t) (ecc_tmp >> 24);
359 495
360 ecc_tmp = readl(&regs->bank_regs[bank].ecc3); 496 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC3));
361 ecc[8] = (uint8_t) (ecc_tmp >> 0); 497 ecc[8] = (uint8_t) (ecc_tmp >> 0);
362 ecc[9] = (uint8_t) (ecc_tmp >> 8); 498 ecc[9] = (uint8_t) (ecc_tmp >> 8);
363 ecc[10] = (uint8_t) (ecc_tmp >> 16); 499 ecc[10] = (uint8_t) (ecc_tmp >> 16);
364 ecc[11] = (uint8_t) (ecc_tmp >> 24); 500 ecc[11] = (uint8_t) (ecc_tmp >> 24);
365 501
366 ecc_tmp = readl(&regs->bank_regs[bank].sts); 502 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, STS));
367 ecc[12] = (uint8_t) (ecc_tmp >> 16); 503 ecc[12] = (uint8_t) (ecc_tmp >> 16);
368 504
369 return 0; 505 return 0;
@@ -379,11 +515,11 @@ static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
379{ 515{
380 struct fsmc_nand_data *host = container_of(mtd, 516 struct fsmc_nand_data *host = container_of(mtd,
381 struct fsmc_nand_data, mtd); 517 struct fsmc_nand_data, mtd);
382 struct fsmc_regs *regs = host->regs_va; 518 void __iomem *regs = host->regs_va;
383 uint32_t bank = host->bank; 519 uint32_t bank = host->bank;
384 uint32_t ecc_tmp; 520 uint32_t ecc_tmp;
385 521
386 ecc_tmp = readl(&regs->bank_regs[bank].ecc1); 522 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
387 ecc[0] = (uint8_t) (ecc_tmp >> 0); 523 ecc[0] = (uint8_t) (ecc_tmp >> 0);
388 ecc[1] = (uint8_t) (ecc_tmp >> 8); 524 ecc[1] = (uint8_t) (ecc_tmp >> 8);
389 ecc[2] = (uint8_t) (ecc_tmp >> 16); 525 ecc[2] = (uint8_t) (ecc_tmp >> 16);
@@ -391,6 +527,166 @@ static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
391 return 0; 527 return 0;
392} 528}
393 529
530/* Count the number of 0's in buff upto a max of max_bits */
531static int count_written_bits(uint8_t *buff, int size, int max_bits)
532{
533 int k, written_bits = 0;
534
535 for (k = 0; k < size; k++) {
536 written_bits += hweight8(~buff[k]);
537 if (written_bits > max_bits)
538 break;
539 }
540
541 return written_bits;
542}
543
544static void dma_complete(void *param)
545{
546 struct fsmc_nand_data *host = param;
547
548 complete(&host->dma_access_complete);
549}
550
551static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
552 enum dma_data_direction direction)
553{
554 struct dma_chan *chan;
555 struct dma_device *dma_dev;
556 struct dma_async_tx_descriptor *tx;
557 dma_addr_t dma_dst, dma_src, dma_addr;
558 dma_cookie_t cookie;
559 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
560 int ret;
561
562 if (direction == DMA_TO_DEVICE)
563 chan = host->write_dma_chan;
564 else if (direction == DMA_FROM_DEVICE)
565 chan = host->read_dma_chan;
566 else
567 return -EINVAL;
568
569 dma_dev = chan->device;
570 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
571
572 if (direction == DMA_TO_DEVICE) {
573 dma_src = dma_addr;
574 dma_dst = host->data_pa;
575 flags |= DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_SKIP_DEST_UNMAP;
576 } else {
577 dma_src = host->data_pa;
578 dma_dst = dma_addr;
579 flags |= DMA_COMPL_DEST_UNMAP_SINGLE | DMA_COMPL_SKIP_SRC_UNMAP;
580 }
581
582 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
583 len, flags);
584
585 if (!tx) {
586 dev_err(host->dev, "device_prep_dma_memcpy error\n");
587 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
588 return -EIO;
589 }
590
591 tx->callback = dma_complete;
592 tx->callback_param = host;
593 cookie = tx->tx_submit(tx);
594
595 ret = dma_submit_error(cookie);
596 if (ret) {
597 dev_err(host->dev, "dma_submit_error %d\n", cookie);
598 return ret;
599 }
600
601 dma_async_issue_pending(chan);
602
603 ret =
604 wait_for_completion_interruptible_timeout(&host->dma_access_complete,
605 msecs_to_jiffies(3000));
606 if (ret <= 0) {
607 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
608 dev_err(host->dev, "wait_for_completion_timeout\n");
609 return ret ? ret : -ETIMEDOUT;
610 }
611
612 return 0;
613}
614
615/*
616 * fsmc_write_buf - write buffer to chip
617 * @mtd: MTD device structure
618 * @buf: data buffer
619 * @len: number of bytes to write
620 */
621static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
622{
623 int i;
624 struct nand_chip *chip = mtd->priv;
625
626 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
627 IS_ALIGNED(len, sizeof(uint32_t))) {
628 uint32_t *p = (uint32_t *)buf;
629 len = len >> 2;
630 for (i = 0; i < len; i++)
631 writel(p[i], chip->IO_ADDR_W);
632 } else {
633 for (i = 0; i < len; i++)
634 writeb(buf[i], chip->IO_ADDR_W);
635 }
636}
637
638/*
639 * fsmc_read_buf - read chip data into buffer
640 * @mtd: MTD device structure
641 * @buf: buffer to store date
642 * @len: number of bytes to read
643 */
644static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
645{
646 int i;
647 struct nand_chip *chip = mtd->priv;
648
649 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
650 IS_ALIGNED(len, sizeof(uint32_t))) {
651 uint32_t *p = (uint32_t *)buf;
652 len = len >> 2;
653 for (i = 0; i < len; i++)
654 p[i] = readl(chip->IO_ADDR_R);
655 } else {
656 for (i = 0; i < len; i++)
657 buf[i] = readb(chip->IO_ADDR_R);
658 }
659}
660
661/*
662 * fsmc_read_buf_dma - read chip data into buffer
663 * @mtd: MTD device structure
664 * @buf: buffer to store date
665 * @len: number of bytes to read
666 */
667static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
668{
669 struct fsmc_nand_data *host;
670
671 host = container_of(mtd, struct fsmc_nand_data, mtd);
672 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
673}
674
675/*
676 * fsmc_write_buf_dma - write buffer to chip
677 * @mtd: MTD device structure
678 * @buf: data buffer
679 * @len: number of bytes to write
680 */
681static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
682 int len)
683{
684 struct fsmc_nand_data *host;
685
686 host = container_of(mtd, struct fsmc_nand_data, mtd);
687 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
688}
689
394/* 690/*
395 * fsmc_read_page_hwecc 691 * fsmc_read_page_hwecc
396 * @mtd: mtd info structure 692 * @mtd: mtd info structure
@@ -426,7 +722,6 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
426 uint8_t *oob = (uint8_t *)&ecc_oob[0]; 722 uint8_t *oob = (uint8_t *)&ecc_oob[0];
427 723
428 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { 724 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
429
430 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page); 725 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
431 chip->ecc.hwctl(mtd, NAND_ECC_READ); 726 chip->ecc.hwctl(mtd, NAND_ECC_READ);
432 chip->read_buf(mtd, p, eccsize); 727 chip->read_buf(mtd, p, eccsize);
@@ -437,17 +732,19 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
437 group++; 732 group++;
438 733
439 /* 734 /*
440 * length is intentionally kept a higher multiple of 2 735 * length is intentionally kept a higher multiple of 2
441 * to read at least 13 bytes even in case of 16 bit NAND 736 * to read at least 13 bytes even in case of 16 bit NAND
442 * devices 737 * devices
443 */ 738 */
444 len = roundup(len, 2); 739 if (chip->options & NAND_BUSWIDTH_16)
740 len = roundup(len, 2);
741
445 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page); 742 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
446 chip->read_buf(mtd, oob + j, len); 743 chip->read_buf(mtd, oob + j, len);
447 j += len; 744 j += len;
448 } 745 }
449 746
450 memcpy(&ecc_code[i], oob, 13); 747 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
451 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 748 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
452 749
453 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 750 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
@@ -461,7 +758,7 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
461} 758}
462 759
463/* 760/*
464 * fsmc_correct_data 761 * fsmc_bch8_correct_data
465 * @mtd: mtd info structure 762 * @mtd: mtd info structure
466 * @dat: buffer of read data 763 * @dat: buffer of read data
467 * @read_ecc: ecc read from device spare area 764 * @read_ecc: ecc read from device spare area
@@ -470,19 +767,51 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
470 * calc_ecc is a 104 bit information containing maximum of 8 error 767 * calc_ecc is a 104 bit information containing maximum of 8 error
471 * offset informations of 13 bits each in 512 bytes of read data. 768 * offset informations of 13 bits each in 512 bytes of read data.
472 */ 769 */
473static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat, 770static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
474 uint8_t *read_ecc, uint8_t *calc_ecc) 771 uint8_t *read_ecc, uint8_t *calc_ecc)
475{ 772{
476 struct fsmc_nand_data *host = container_of(mtd, 773 struct fsmc_nand_data *host = container_of(mtd,
477 struct fsmc_nand_data, mtd); 774 struct fsmc_nand_data, mtd);
478 struct fsmc_regs *regs = host->regs_va; 775 struct nand_chip *chip = mtd->priv;
776 void __iomem *regs = host->regs_va;
479 unsigned int bank = host->bank; 777 unsigned int bank = host->bank;
480 uint16_t err_idx[8]; 778 uint32_t err_idx[8];
481 uint64_t ecc_data[2];
482 uint32_t num_err, i; 779 uint32_t num_err, i;
780 uint32_t ecc1, ecc2, ecc3, ecc4;
781
782 num_err = (readl(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
783
784 /* no bit flipping */
785 if (likely(num_err == 0))
786 return 0;
787
788 /* too many errors */
789 if (unlikely(num_err > 8)) {
790 /*
791 * This is a temporary erase check. A newly erased page read
792 * would result in an ecc error because the oob data is also
793 * erased to FF and the calculated ecc for an FF data is not
794 * FF..FF.
795 * This is a workaround to skip performing correction in case
796 * data is FF..FF
797 *
798 * Logic:
799 * For every page, each bit written as 0 is counted until these
800 * number of bits are greater than 8 (the maximum correction
801 * capability of FSMC for each 512 + 13 bytes)
802 */
803
804 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
805 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
806
807 if ((bits_ecc + bits_data) <= 8) {
808 if (bits_data)
809 memset(dat, 0xff, chip->ecc.size);
810 return bits_data;
811 }
483 812
484 /* The calculated ecc is actually the correction index in data */ 813 return -EBADMSG;
485 memcpy(ecc_data, calc_ecc, 13); 814 }
486 815
487 /* 816 /*
488 * ------------------- calc_ecc[] bit wise -----------|--13 bits--| 817 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
@@ -493,27 +822,26 @@ static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
493 * uint64_t array and error offset indexes are populated in err_idx 822 * uint64_t array and error offset indexes are populated in err_idx
494 * array 823 * array
495 */ 824 */
496 for (i = 0; i < 8; i++) { 825 ecc1 = readl(FSMC_NAND_REG(regs, bank, ECC1));
497 if (i == 4) { 826 ecc2 = readl(FSMC_NAND_REG(regs, bank, ECC2));
498 err_idx[4] = ((ecc_data[1] & 0x1) << 12) | ecc_data[0]; 827 ecc3 = readl(FSMC_NAND_REG(regs, bank, ECC3));
499 ecc_data[1] >>= 1; 828 ecc4 = readl(FSMC_NAND_REG(regs, bank, STS));
500 continue; 829
501 } 830 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
502 err_idx[i] = (ecc_data[i/4] & 0x1FFF); 831 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
503 ecc_data[i/4] >>= 13; 832 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
504 } 833 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
505 834 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
506 num_err = (readl(&regs->bank_regs[bank].sts) >> 10) & 0xF; 835 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
507 836 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
508 if (num_err == 0xF) 837 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
509 return -EBADMSG;
510 838
511 i = 0; 839 i = 0;
512 while (num_err--) { 840 while (num_err--) {
513 change_bit(0, (unsigned long *)&err_idx[i]); 841 change_bit(0, (unsigned long *)&err_idx[i]);
514 change_bit(1, (unsigned long *)&err_idx[i]); 842 change_bit(1, (unsigned long *)&err_idx[i]);
515 843
516 if (err_idx[i] <= 512 * 8) { 844 if (err_idx[i] < chip->ecc.size * 8) {
517 change_bit(err_idx[i], (unsigned long *)dat); 845 change_bit(err_idx[i], (unsigned long *)dat);
518 i++; 846 i++;
519 } 847 }
@@ -521,6 +849,44 @@ static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
521 return i; 849 return i;
522} 850}
523 851
852static bool filter(struct dma_chan *chan, void *slave)
853{
854 chan->private = slave;
855 return true;
856}
857
858#ifdef CONFIG_OF
859static int __devinit fsmc_nand_probe_config_dt(struct platform_device *pdev,
860 struct device_node *np)
861{
862 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
863 u32 val;
864
865 /* Set default NAND width to 8 bits */
866 pdata->width = 8;
867 if (!of_property_read_u32(np, "bank-width", &val)) {
868 if (val == 2) {
869 pdata->width = 16;
870 } else if (val != 1) {
871 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
872 return -EINVAL;
873 }
874 }
875 of_property_read_u32(np, "st,ale-off", &pdata->ale_off);
876 of_property_read_u32(np, "st,cle-off", &pdata->cle_off);
877 if (of_get_property(np, "nand-skip-bbtscan", NULL))
878 pdata->options = NAND_SKIP_BBTSCAN;
879
880 return 0;
881}
882#else
883static int __devinit fsmc_nand_probe_config_dt(struct platform_device *pdev,
884 struct device_node *np)
885{
886 return -ENOSYS;
887}
888#endif
889
524/* 890/*
525 * fsmc_nand_probe - Probe function 891 * fsmc_nand_probe - Probe function
526 * @pdev: platform device structure 892 * @pdev: platform device structure
@@ -528,102 +894,109 @@ static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
528static int __init fsmc_nand_probe(struct platform_device *pdev) 894static int __init fsmc_nand_probe(struct platform_device *pdev)
529{ 895{
530 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); 896 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
897 struct device_node __maybe_unused *np = pdev->dev.of_node;
898 struct mtd_part_parser_data ppdata = {};
531 struct fsmc_nand_data *host; 899 struct fsmc_nand_data *host;
532 struct mtd_info *mtd; 900 struct mtd_info *mtd;
533 struct nand_chip *nand; 901 struct nand_chip *nand;
534 struct fsmc_regs *regs;
535 struct resource *res; 902 struct resource *res;
903 dma_cap_mask_t mask;
536 int ret = 0; 904 int ret = 0;
537 u32 pid; 905 u32 pid;
538 int i; 906 int i;
539 907
908 if (np) {
909 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
910 pdev->dev.platform_data = pdata;
911 ret = fsmc_nand_probe_config_dt(pdev, np);
912 if (ret) {
913 dev_err(&pdev->dev, "no platform data\n");
914 return -ENODEV;
915 }
916 }
917
540 if (!pdata) { 918 if (!pdata) {
541 dev_err(&pdev->dev, "platform data is NULL\n"); 919 dev_err(&pdev->dev, "platform data is NULL\n");
542 return -EINVAL; 920 return -EINVAL;
543 } 921 }
544 922
545 /* Allocate memory for the device structure (and zero it) */ 923 /* Allocate memory for the device structure (and zero it) */
546 host = kzalloc(sizeof(*host), GFP_KERNEL); 924 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
547 if (!host) { 925 if (!host) {
548 dev_err(&pdev->dev, "failed to allocate device structure\n"); 926 dev_err(&pdev->dev, "failed to allocate device structure\n");
549 return -ENOMEM; 927 return -ENOMEM;
550 } 928 }
551 929
552 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); 930 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
553 if (!res) { 931 if (!res)
554 ret = -EIO; 932 return -EINVAL;
555 goto err_probe1;
556 }
557 933
558 host->resdata = request_mem_region(res->start, resource_size(res), 934 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
559 pdev->name); 935 pdev->name)) {
560 if (!host->resdata) { 936 dev_err(&pdev->dev, "Failed to get memory data resourse\n");
561 ret = -EIO; 937 return -ENOENT;
562 goto err_probe1;
563 } 938 }
564 939
565 host->data_va = ioremap(res->start, resource_size(res)); 940 host->data_pa = (dma_addr_t)res->start;
941 host->data_va = devm_ioremap(&pdev->dev, res->start,
942 resource_size(res));
566 if (!host->data_va) { 943 if (!host->data_va) {
567 ret = -EIO; 944 dev_err(&pdev->dev, "data ioremap failed\n");
568 goto err_probe1; 945 return -ENOMEM;
569 } 946 }
570 947
571 host->resaddr = request_mem_region(res->start + PLAT_NAND_ALE, 948 if (!devm_request_mem_region(&pdev->dev, res->start + pdata->ale_off,
572 resource_size(res), pdev->name); 949 resource_size(res), pdev->name)) {
573 if (!host->resaddr) { 950 dev_err(&pdev->dev, "Failed to get memory ale resourse\n");
574 ret = -EIO; 951 return -ENOENT;
575 goto err_probe1;
576 } 952 }
577 953
578 host->addr_va = ioremap(res->start + PLAT_NAND_ALE, resource_size(res)); 954 host->addr_va = devm_ioremap(&pdev->dev, res->start + pdata->ale_off,
955 resource_size(res));
579 if (!host->addr_va) { 956 if (!host->addr_va) {
580 ret = -EIO; 957 dev_err(&pdev->dev, "ale ioremap failed\n");
581 goto err_probe1; 958 return -ENOMEM;
582 } 959 }
583 960
584 host->rescmd = request_mem_region(res->start + PLAT_NAND_CLE, 961 if (!devm_request_mem_region(&pdev->dev, res->start + pdata->cle_off,
585 resource_size(res), pdev->name); 962 resource_size(res), pdev->name)) {
586 if (!host->rescmd) { 963 dev_err(&pdev->dev, "Failed to get memory cle resourse\n");
587 ret = -EIO; 964 return -ENOENT;
588 goto err_probe1;
589 } 965 }
590 966
591 host->cmd_va = ioremap(res->start + PLAT_NAND_CLE, resource_size(res)); 967 host->cmd_va = devm_ioremap(&pdev->dev, res->start + pdata->cle_off,
968 resource_size(res));
592 if (!host->cmd_va) { 969 if (!host->cmd_va) {
593 ret = -EIO; 970 dev_err(&pdev->dev, "ale ioremap failed\n");
594 goto err_probe1; 971 return -ENOMEM;
595 } 972 }
596 973
597 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs"); 974 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
598 if (!res) { 975 if (!res)
599 ret = -EIO; 976 return -EINVAL;
600 goto err_probe1;
601 }
602 977
603 host->resregs = request_mem_region(res->start, resource_size(res), 978 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
604 pdev->name); 979 pdev->name)) {
605 if (!host->resregs) { 980 dev_err(&pdev->dev, "Failed to get memory regs resourse\n");
606 ret = -EIO; 981 return -ENOENT;
607 goto err_probe1;
608 } 982 }
609 983
610 host->regs_va = ioremap(res->start, resource_size(res)); 984 host->regs_va = devm_ioremap(&pdev->dev, res->start,
985 resource_size(res));
611 if (!host->regs_va) { 986 if (!host->regs_va) {
612 ret = -EIO; 987 dev_err(&pdev->dev, "regs ioremap failed\n");
613 goto err_probe1; 988 return -ENOMEM;
614 } 989 }
615 990
616 host->clk = clk_get(&pdev->dev, NULL); 991 host->clk = clk_get(&pdev->dev, NULL);
617 if (IS_ERR(host->clk)) { 992 if (IS_ERR(host->clk)) {
618 dev_err(&pdev->dev, "failed to fetch block clock\n"); 993 dev_err(&pdev->dev, "failed to fetch block clock\n");
619 ret = PTR_ERR(host->clk); 994 return PTR_ERR(host->clk);
620 host->clk = NULL;
621 goto err_probe1;
622 } 995 }
623 996
624 ret = clk_enable(host->clk); 997 ret = clk_enable(host->clk);
625 if (ret) 998 if (ret)
626 goto err_probe1; 999 goto err_clk_enable;
627 1000
628 /* 1001 /*
629 * This device ID is actually a common AMBA ID as used on the 1002 * This device ID is actually a common AMBA ID as used on the
@@ -639,7 +1012,14 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
639 1012
640 host->bank = pdata->bank; 1013 host->bank = pdata->bank;
641 host->select_chip = pdata->select_bank; 1014 host->select_chip = pdata->select_bank;
642 regs = host->regs_va; 1015 host->partitions = pdata->partitions;
1016 host->nr_partitions = pdata->nr_partitions;
1017 host->dev = &pdev->dev;
1018 host->dev_timings = pdata->nand_timings;
1019 host->mode = pdata->mode;
1020
1021 if (host->mode == USE_DMA_ACCESS)
1022 init_completion(&host->dma_access_complete);
643 1023
644 /* Link all private pointers */ 1024 /* Link all private pointers */
645 mtd = &host->mtd; 1025 mtd = &host->mtd;
@@ -658,21 +1038,53 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
658 nand->ecc.size = 512; 1038 nand->ecc.size = 512;
659 nand->options = pdata->options; 1039 nand->options = pdata->options;
660 nand->select_chip = fsmc_select_chip; 1040 nand->select_chip = fsmc_select_chip;
1041 nand->badblockbits = 7;
661 1042
662 if (pdata->width == FSMC_NAND_BW16) 1043 if (pdata->width == FSMC_NAND_BW16)
663 nand->options |= NAND_BUSWIDTH_16; 1044 nand->options |= NAND_BUSWIDTH_16;
664 1045
665 fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16); 1046 switch (host->mode) {
1047 case USE_DMA_ACCESS:
1048 dma_cap_zero(mask);
1049 dma_cap_set(DMA_MEMCPY, mask);
1050 host->read_dma_chan = dma_request_channel(mask, filter,
1051 pdata->read_dma_priv);
1052 if (!host->read_dma_chan) {
1053 dev_err(&pdev->dev, "Unable to get read dma channel\n");
1054 goto err_req_read_chnl;
1055 }
1056 host->write_dma_chan = dma_request_channel(mask, filter,
1057 pdata->write_dma_priv);
1058 if (!host->write_dma_chan) {
1059 dev_err(&pdev->dev, "Unable to get write dma channel\n");
1060 goto err_req_write_chnl;
1061 }
1062 nand->read_buf = fsmc_read_buf_dma;
1063 nand->write_buf = fsmc_write_buf_dma;
1064 break;
1065
1066 default:
1067 case USE_WORD_ACCESS:
1068 nand->read_buf = fsmc_read_buf;
1069 nand->write_buf = fsmc_write_buf;
1070 break;
1071 }
1072
1073 fsmc_nand_setup(host->regs_va, host->bank,
1074 nand->options & NAND_BUSWIDTH_16,
1075 host->dev_timings);
666 1076
667 if (AMBA_REV_BITS(host->pid) >= 8) { 1077 if (AMBA_REV_BITS(host->pid) >= 8) {
668 nand->ecc.read_page = fsmc_read_page_hwecc; 1078 nand->ecc.read_page = fsmc_read_page_hwecc;
669 nand->ecc.calculate = fsmc_read_hwecc_ecc4; 1079 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
670 nand->ecc.correct = fsmc_correct_data; 1080 nand->ecc.correct = fsmc_bch8_correct_data;
671 nand->ecc.bytes = 13; 1081 nand->ecc.bytes = 13;
1082 nand->ecc.strength = 8;
672 } else { 1083 } else {
673 nand->ecc.calculate = fsmc_read_hwecc_ecc1; 1084 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
674 nand->ecc.correct = nand_correct_data; 1085 nand->ecc.correct = nand_correct_data;
675 nand->ecc.bytes = 3; 1086 nand->ecc.bytes = 3;
1087 nand->ecc.strength = 1;
676 } 1088 }
677 1089
678 /* 1090 /*
@@ -681,19 +1093,52 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
681 if (nand_scan_ident(&host->mtd, 1, NULL)) { 1093 if (nand_scan_ident(&host->mtd, 1, NULL)) {
682 ret = -ENXIO; 1094 ret = -ENXIO;
683 dev_err(&pdev->dev, "No NAND Device found!\n"); 1095 dev_err(&pdev->dev, "No NAND Device found!\n");
684 goto err_probe; 1096 goto err_scan_ident;
685 } 1097 }
686 1098
687 if (AMBA_REV_BITS(host->pid) >= 8) { 1099 if (AMBA_REV_BITS(host->pid) >= 8) {
688 if (host->mtd.writesize == 512) { 1100 switch (host->mtd.oobsize) {
689 nand->ecc.layout = &fsmc_ecc4_sp_layout; 1101 case 16:
1102 nand->ecc.layout = &fsmc_ecc4_16_layout;
690 host->ecc_place = &fsmc_ecc4_sp_place; 1103 host->ecc_place = &fsmc_ecc4_sp_place;
691 } else { 1104 break;
692 nand->ecc.layout = &fsmc_ecc4_lp_layout; 1105 case 64:
1106 nand->ecc.layout = &fsmc_ecc4_64_layout;
1107 host->ecc_place = &fsmc_ecc4_lp_place;
1108 break;
1109 case 128:
1110 nand->ecc.layout = &fsmc_ecc4_128_layout;
1111 host->ecc_place = &fsmc_ecc4_lp_place;
1112 break;
1113 case 224:
1114 nand->ecc.layout = &fsmc_ecc4_224_layout;
693 host->ecc_place = &fsmc_ecc4_lp_place; 1115 host->ecc_place = &fsmc_ecc4_lp_place;
1116 break;
1117 case 256:
1118 nand->ecc.layout = &fsmc_ecc4_256_layout;
1119 host->ecc_place = &fsmc_ecc4_lp_place;
1120 break;
1121 default:
1122 printk(KERN_WARNING "No oob scheme defined for "
1123 "oobsize %d\n", mtd->oobsize);
1124 BUG();
694 } 1125 }
695 } else { 1126 } else {
696 nand->ecc.layout = &fsmc_ecc1_layout; 1127 switch (host->mtd.oobsize) {
1128 case 16:
1129 nand->ecc.layout = &fsmc_ecc1_16_layout;
1130 break;
1131 case 64:
1132 nand->ecc.layout = &fsmc_ecc1_64_layout;
1133 break;
1134 case 128:
1135 nand->ecc.layout = &fsmc_ecc1_128_layout;
1136 break;
1137 default:
1138 printk(KERN_WARNING "No oob scheme defined for "
1139 "oobsize %d\n", mtd->oobsize);
1140 BUG();
1141 }
697 } 1142 }
698 1143
699 /* Second stage of scan to fill MTD data-structures */ 1144 /* Second stage of scan to fill MTD data-structures */
@@ -713,13 +1158,9 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
713 * Check for partition info passed 1158 * Check for partition info passed
714 */ 1159 */
715 host->mtd.name = "nand"; 1160 host->mtd.name = "nand";
716 ret = mtd_device_parse_register(&host->mtd, NULL, 0, 1161 ppdata.of_node = np;
717 host->mtd.size <= 0x04000000 ? 1162 ret = mtd_device_parse_register(&host->mtd, NULL, &ppdata,
718 partition_info_16KB_blk : 1163 host->partitions, host->nr_partitions);
719 partition_info_128KB_blk,
720 host->mtd.size <= 0x04000000 ?
721 ARRAY_SIZE(partition_info_16KB_blk) :
722 ARRAY_SIZE(partition_info_128KB_blk));
723 if (ret) 1164 if (ret)
724 goto err_probe; 1165 goto err_probe;
725 1166
@@ -728,32 +1169,16 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
728 return 0; 1169 return 0;
729 1170
730err_probe: 1171err_probe:
1172err_scan_ident:
1173 if (host->mode == USE_DMA_ACCESS)
1174 dma_release_channel(host->write_dma_chan);
1175err_req_write_chnl:
1176 if (host->mode == USE_DMA_ACCESS)
1177 dma_release_channel(host->read_dma_chan);
1178err_req_read_chnl:
731 clk_disable(host->clk); 1179 clk_disable(host->clk);
732err_probe1: 1180err_clk_enable:
733 if (host->clk) 1181 clk_put(host->clk);
734 clk_put(host->clk);
735 if (host->regs_va)
736 iounmap(host->regs_va);
737 if (host->resregs)
738 release_mem_region(host->resregs->start,
739 resource_size(host->resregs));
740 if (host->cmd_va)
741 iounmap(host->cmd_va);
742 if (host->rescmd)
743 release_mem_region(host->rescmd->start,
744 resource_size(host->rescmd));
745 if (host->addr_va)
746 iounmap(host->addr_va);
747 if (host->resaddr)
748 release_mem_region(host->resaddr->start,
749 resource_size(host->resaddr));
750 if (host->data_va)
751 iounmap(host->data_va);
752 if (host->resdata)
753 release_mem_region(host->resdata->start,
754 resource_size(host->resdata));
755
756 kfree(host);
757 return ret; 1182 return ret;
758} 1183}
759 1184
@@ -768,24 +1193,15 @@ static int fsmc_nand_remove(struct platform_device *pdev)
768 1193
769 if (host) { 1194 if (host) {
770 nand_release(&host->mtd); 1195 nand_release(&host->mtd);
1196
1197 if (host->mode == USE_DMA_ACCESS) {
1198 dma_release_channel(host->write_dma_chan);
1199 dma_release_channel(host->read_dma_chan);
1200 }
771 clk_disable(host->clk); 1201 clk_disable(host->clk);
772 clk_put(host->clk); 1202 clk_put(host->clk);
773
774 iounmap(host->regs_va);
775 release_mem_region(host->resregs->start,
776 resource_size(host->resregs));
777 iounmap(host->cmd_va);
778 release_mem_region(host->rescmd->start,
779 resource_size(host->rescmd));
780 iounmap(host->addr_va);
781 release_mem_region(host->resaddr->start,
782 resource_size(host->resaddr));
783 iounmap(host->data_va);
784 release_mem_region(host->resdata->start,
785 resource_size(host->resdata));
786
787 kfree(host);
788 } 1203 }
1204
789 return 0; 1205 return 0;
790} 1206}
791 1207
@@ -801,15 +1217,24 @@ static int fsmc_nand_suspend(struct device *dev)
801static int fsmc_nand_resume(struct device *dev) 1217static int fsmc_nand_resume(struct device *dev)
802{ 1218{
803 struct fsmc_nand_data *host = dev_get_drvdata(dev); 1219 struct fsmc_nand_data *host = dev_get_drvdata(dev);
804 if (host) 1220 if (host) {
805 clk_enable(host->clk); 1221 clk_enable(host->clk);
1222 fsmc_nand_setup(host->regs_va, host->bank,
1223 host->nand.options & NAND_BUSWIDTH_16,
1224 host->dev_timings);
1225 }
806 return 0; 1226 return 0;
807} 1227}
808 1228
809static const struct dev_pm_ops fsmc_nand_pm_ops = { 1229static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
810 .suspend = fsmc_nand_suspend, 1230#endif
811 .resume = fsmc_nand_resume, 1231
1232#ifdef CONFIG_OF
1233static const struct of_device_id fsmc_nand_id_table[] = {
1234 { .compatible = "st,spear600-fsmc-nand" },
1235 {}
812}; 1236};
1237MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
813#endif 1238#endif
814 1239
815static struct platform_driver fsmc_nand_driver = { 1240static struct platform_driver fsmc_nand_driver = {
@@ -817,6 +1242,7 @@ static struct platform_driver fsmc_nand_driver = {
817 .driver = { 1242 .driver = {
818 .owner = THIS_MODULE, 1243 .owner = THIS_MODULE,
819 .name = "fsmc-nand", 1244 .name = "fsmc-nand",
1245 .of_match_table = of_match_ptr(fsmc_nand_id_table),
820#ifdef CONFIG_PM 1246#ifdef CONFIG_PM
821 .pm = &fsmc_nand_pm_ops, 1247 .pm = &fsmc_nand_pm_ops,
822#endif 1248#endif
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 590dd5cceed6..e8ea7107932e 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -848,7 +848,10 @@ int gpmi_send_command(struct gpmi_nand_data *this)
848 848
849 sg_init_one(sgl, this->cmd_buffer, this->command_length); 849 sg_init_one(sgl, this->cmd_buffer, this->command_length);
850 dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE); 850 dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
851 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_MEM_TO_DEV, 1); 851 desc = dmaengine_prep_slave_sg(channel,
852 sgl, 1, DMA_MEM_TO_DEV,
853 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
854
852 if (!desc) { 855 if (!desc) {
853 pr_err("step 2 error\n"); 856 pr_err("step 2 error\n");
854 return -1; 857 return -1;
@@ -889,7 +892,8 @@ int gpmi_send_data(struct gpmi_nand_data *this)
889 /* [2] send DMA request */ 892 /* [2] send DMA request */
890 prepare_data_dma(this, DMA_TO_DEVICE); 893 prepare_data_dma(this, DMA_TO_DEVICE);
891 desc = dmaengine_prep_slave_sg(channel, &this->data_sgl, 894 desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
892 1, DMA_MEM_TO_DEV, 1); 895 1, DMA_MEM_TO_DEV,
896 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
893 if (!desc) { 897 if (!desc) {
894 pr_err("step 2 error\n"); 898 pr_err("step 2 error\n");
895 return -1; 899 return -1;
@@ -925,7 +929,8 @@ int gpmi_read_data(struct gpmi_nand_data *this)
925 /* [2] : send DMA request */ 929 /* [2] : send DMA request */
926 prepare_data_dma(this, DMA_FROM_DEVICE); 930 prepare_data_dma(this, DMA_FROM_DEVICE);
927 desc = dmaengine_prep_slave_sg(channel, &this->data_sgl, 931 desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
928 1, DMA_DEV_TO_MEM, 1); 932 1, DMA_DEV_TO_MEM,
933 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
929 if (!desc) { 934 if (!desc) {
930 pr_err("step 2 error\n"); 935 pr_err("step 2 error\n");
931 return -1; 936 return -1;
@@ -970,8 +975,10 @@ int gpmi_send_page(struct gpmi_nand_data *this,
970 pio[4] = payload; 975 pio[4] = payload;
971 pio[5] = auxiliary; 976 pio[5] = auxiliary;
972 977
973 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio, 978 desc = dmaengine_prep_slave_sg(channel,
974 ARRAY_SIZE(pio), DMA_TRANS_NONE, 0); 979 (struct scatterlist *)pio,
980 ARRAY_SIZE(pio), DMA_TRANS_NONE,
981 DMA_CTRL_ACK);
975 if (!desc) { 982 if (!desc) {
976 pr_err("step 2 error\n"); 983 pr_err("step 2 error\n");
977 return -1; 984 return -1;
@@ -1035,7 +1042,8 @@ int gpmi_read_page(struct gpmi_nand_data *this,
1035 pio[5] = auxiliary; 1042 pio[5] = auxiliary;
1036 desc = dmaengine_prep_slave_sg(channel, 1043 desc = dmaengine_prep_slave_sg(channel,
1037 (struct scatterlist *)pio, 1044 (struct scatterlist *)pio,
1038 ARRAY_SIZE(pio), DMA_TRANS_NONE, 1); 1045 ARRAY_SIZE(pio), DMA_TRANS_NONE,
1046 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1039 if (!desc) { 1047 if (!desc) {
1040 pr_err("step 2 error\n"); 1048 pr_err("step 2 error\n");
1041 return -1; 1049 return -1;
@@ -1052,9 +1060,11 @@ int gpmi_read_page(struct gpmi_nand_data *this,
1052 | BF_GPMI_CTRL0_ADDRESS(address) 1060 | BF_GPMI_CTRL0_ADDRESS(address)
1053 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size); 1061 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1054 pio[1] = 0; 1062 pio[1] = 0;
1063 pio[2] = 0; /* clear GPMI_HW_GPMI_ECCCTRL, disable the BCH. */
1055 desc = dmaengine_prep_slave_sg(channel, 1064 desc = dmaengine_prep_slave_sg(channel,
1056 (struct scatterlist *)pio, 2, 1065 (struct scatterlist *)pio, 3,
1057 DMA_TRANS_NONE, 1); 1066 DMA_TRANS_NONE,
1067 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1058 if (!desc) { 1068 if (!desc) {
1059 pr_err("step 3 error\n"); 1069 pr_err("step 3 error\n");
1060 return -1; 1070 return -1;
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 493ec2fcf97f..75b1dde16358 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -1124,7 +1124,7 @@ static int gpmi_block_markbad(struct mtd_info *mtd, loff_t ofs)
1124 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); 1124 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1125 1125
1126 /* Do we have a flash based bad block table ? */ 1126 /* Do we have a flash based bad block table ? */
1127 if (chip->options & NAND_BBT_USE_FLASH) 1127 if (chip->bbt_options & NAND_BBT_USE_FLASH)
1128 ret = nand_update_bbt(mtd, ofs); 1128 ret = nand_update_bbt(mtd, ofs);
1129 else { 1129 else {
1130 chipnr = (int)(ofs >> chip->chip_shift); 1130 chipnr = (int)(ofs >> chip->chip_shift);
@@ -1155,7 +1155,7 @@ static int gpmi_block_markbad(struct mtd_info *mtd, loff_t ofs)
1155 return ret; 1155 return ret;
1156} 1156}
1157 1157
1158static int __devinit nand_boot_set_geometry(struct gpmi_nand_data *this) 1158static int nand_boot_set_geometry(struct gpmi_nand_data *this)
1159{ 1159{
1160 struct boot_rom_geometry *geometry = &this->rom_geometry; 1160 struct boot_rom_geometry *geometry = &this->rom_geometry;
1161 1161
@@ -1182,7 +1182,7 @@ static int __devinit nand_boot_set_geometry(struct gpmi_nand_data *this)
1182} 1182}
1183 1183
1184static const char *fingerprint = "STMP"; 1184static const char *fingerprint = "STMP";
1185static int __devinit mx23_check_transcription_stamp(struct gpmi_nand_data *this) 1185static int mx23_check_transcription_stamp(struct gpmi_nand_data *this)
1186{ 1186{
1187 struct boot_rom_geometry *rom_geo = &this->rom_geometry; 1187 struct boot_rom_geometry *rom_geo = &this->rom_geometry;
1188 struct device *dev = this->dev; 1188 struct device *dev = this->dev;
@@ -1239,7 +1239,7 @@ static int __devinit mx23_check_transcription_stamp(struct gpmi_nand_data *this)
1239} 1239}
1240 1240
1241/* Writes a transcription stamp. */ 1241/* Writes a transcription stamp. */
1242static int __devinit mx23_write_transcription_stamp(struct gpmi_nand_data *this) 1242static int mx23_write_transcription_stamp(struct gpmi_nand_data *this)
1243{ 1243{
1244 struct device *dev = this->dev; 1244 struct device *dev = this->dev;
1245 struct boot_rom_geometry *rom_geo = &this->rom_geometry; 1245 struct boot_rom_geometry *rom_geo = &this->rom_geometry;
@@ -1322,7 +1322,7 @@ static int __devinit mx23_write_transcription_stamp(struct gpmi_nand_data *this)
1322 return 0; 1322 return 0;
1323} 1323}
1324 1324
1325static int __devinit mx23_boot_init(struct gpmi_nand_data *this) 1325static int mx23_boot_init(struct gpmi_nand_data *this)
1326{ 1326{
1327 struct device *dev = this->dev; 1327 struct device *dev = this->dev;
1328 struct nand_chip *chip = &this->nand; 1328 struct nand_chip *chip = &this->nand;
@@ -1391,7 +1391,7 @@ static int __devinit mx23_boot_init(struct gpmi_nand_data *this)
1391 return 0; 1391 return 0;
1392} 1392}
1393 1393
1394static int __devinit nand_boot_init(struct gpmi_nand_data *this) 1394static int nand_boot_init(struct gpmi_nand_data *this)
1395{ 1395{
1396 nand_boot_set_geometry(this); 1396 nand_boot_set_geometry(this);
1397 1397
@@ -1401,7 +1401,7 @@ static int __devinit nand_boot_init(struct gpmi_nand_data *this)
1401 return 0; 1401 return 0;
1402} 1402}
1403 1403
1404static int __devinit gpmi_set_geometry(struct gpmi_nand_data *this) 1404static int gpmi_set_geometry(struct gpmi_nand_data *this)
1405{ 1405{
1406 int ret; 1406 int ret;
1407 1407
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
index e023bccb7781..ec6180d4ff8f 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -20,7 +20,7 @@
20#include <linux/mtd/nand.h> 20#include <linux/mtd/nand.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h> 22#include <linux/dma-mapping.h>
23#include <mach/dma.h> 23#include <linux/fsl/mxs-dma.h>
24 24
25struct resources { 25struct resources {
26 void *gpmi_regs; 26 void *gpmi_regs;
diff --git a/drivers/mtd/nand/h1910.c b/drivers/mtd/nand/h1910.c
index 5dc6f0d92f1a..11e487813428 100644
--- a/drivers/mtd/nand/h1910.c
+++ b/drivers/mtd/nand/h1910.c
@@ -135,8 +135,8 @@ static int __init h1910_init(void)
135 } 135 }
136 136
137 /* Register the partitions */ 137 /* Register the partitions */
138 mtd_device_parse_register(h1910_nand_mtd, NULL, 0, 138 mtd_device_parse_register(h1910_nand_mtd, NULL, NULL, partition_info,
139 partition_info, NUM_PARTITIONS); 139 NUM_PARTITIONS);
140 140
141 /* Return happy */ 141 /* Return happy */
142 return 0; 142 return 0;
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index ac3b9f255e00..e4147e8acb7c 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -332,6 +332,11 @@ static int __devinit jz_nand_probe(struct platform_device *pdev)
332 chip->ecc.mode = NAND_ECC_HW_OOB_FIRST; 332 chip->ecc.mode = NAND_ECC_HW_OOB_FIRST;
333 chip->ecc.size = 512; 333 chip->ecc.size = 512;
334 chip->ecc.bytes = 9; 334 chip->ecc.bytes = 9;
335 chip->ecc.strength = 2;
336 /*
337 * FIXME: ecc_strength value of 2 bits per 512 bytes of data is a
338 * conservative guess, given 9 ecc bytes and reed-solomon alg.
339 */
335 340
336 if (pdata) 341 if (pdata)
337 chip->ecc.layout = pdata->ecc_layout; 342 chip->ecc.layout = pdata->ecc_layout;
@@ -367,9 +372,9 @@ static int __devinit jz_nand_probe(struct platform_device *pdev)
367 goto err_gpio_free; 372 goto err_gpio_free;
368 } 373 }
369 374
370 ret = mtd_device_parse_register(mtd, NULL, 0, 375 ret = mtd_device_parse_register(mtd, NULL, NULL,
371 pdata ? pdata->partitions : NULL, 376 pdata ? pdata->partitions : NULL,
372 pdata ? pdata->num_partitions : 0); 377 pdata ? pdata->num_partitions : 0);
373 378
374 if (ret) { 379 if (ret) {
375 dev_err(&pdev->dev, "Failed to add mtd device\n"); 380 dev_err(&pdev->dev, "Failed to add mtd device\n");
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 74a43b818d0e..cc0678a967c1 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -1225,9 +1225,16 @@ static int __init mxcnd_probe(struct platform_device *pdev)
1225 goto escan; 1225 goto escan;
1226 } 1226 }
1227 1227
1228 if (this->ecc.mode == NAND_ECC_HW) {
1229 if (nfc_is_v1())
1230 this->ecc.strength = 1;
1231 else
1232 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1233 }
1234
1228 /* Register the partitions */ 1235 /* Register the partitions */
1229 mtd_device_parse_register(mtd, part_probes, 0, 1236 mtd_device_parse_register(mtd, part_probes, NULL, pdata->parts,
1230 pdata->parts, pdata->nr_parts); 1237 pdata->nr_parts);
1231 1238
1232 platform_set_drvdata(pdev, host); 1239 platform_set_drvdata(pdev, host);
1233 1240
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 8a393f9e6027..47b19c0bb070 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -123,12 +123,6 @@ static int check_offs_len(struct mtd_info *mtd,
123 ret = -EINVAL; 123 ret = -EINVAL;
124 } 124 }
125 125
126 /* Do not allow past end of device */
127 if (ofs + len > mtd->size) {
128 pr_debug("%s: past end of device\n", __func__);
129 ret = -EINVAL;
130 }
131
132 return ret; 126 return ret;
133} 127}
134 128
@@ -338,7 +332,7 @@ static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
338 */ 332 */
339static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) 333static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
340{ 334{
341 int page, chipnr, res = 0; 335 int page, chipnr, res = 0, i = 0;
342 struct nand_chip *chip = mtd->priv; 336 struct nand_chip *chip = mtd->priv;
343 u16 bad; 337 u16 bad;
344 338
@@ -356,23 +350,29 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
356 chip->select_chip(mtd, chipnr); 350 chip->select_chip(mtd, chipnr);
357 } 351 }
358 352
359 if (chip->options & NAND_BUSWIDTH_16) { 353 do {
360 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE, 354 if (chip->options & NAND_BUSWIDTH_16) {
361 page); 355 chip->cmdfunc(mtd, NAND_CMD_READOOB,
362 bad = cpu_to_le16(chip->read_word(mtd)); 356 chip->badblockpos & 0xFE, page);
363 if (chip->badblockpos & 0x1) 357 bad = cpu_to_le16(chip->read_word(mtd));
364 bad >>= 8; 358 if (chip->badblockpos & 0x1)
365 else 359 bad >>= 8;
366 bad &= 0xFF; 360 else
367 } else { 361 bad &= 0xFF;
368 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); 362 } else {
369 bad = chip->read_byte(mtd); 363 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
370 } 364 page);
365 bad = chip->read_byte(mtd);
366 }
371 367
372 if (likely(chip->badblockbits == 8)) 368 if (likely(chip->badblockbits == 8))
373 res = bad != 0xFF; 369 res = bad != 0xFF;
374 else 370 else
375 res = hweight8(bad) < chip->badblockbits; 371 res = hweight8(bad) < chip->badblockbits;
372 ofs += mtd->writesize;
373 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
374 i++;
375 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
376 376
377 if (getchip) 377 if (getchip)
378 nand_release_device(mtd); 378 nand_release_device(mtd);
@@ -386,51 +386,79 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
386 * @ofs: offset from device start 386 * @ofs: offset from device start
387 * 387 *
388 * This is the default implementation, which can be overridden by a hardware 388 * This is the default implementation, which can be overridden by a hardware
389 * specific driver. 389 * specific driver. We try operations in the following order, according to our
390 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
391 * (1) erase the affected block, to allow OOB marker to be written cleanly
392 * (2) update in-memory BBT
393 * (3) write bad block marker to OOB area of affected block
394 * (4) update flash-based BBT
395 * Note that we retain the first error encountered in (3) or (4), finish the
396 * procedures, and dump the error in the end.
390*/ 397*/
391static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) 398static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
392{ 399{
393 struct nand_chip *chip = mtd->priv; 400 struct nand_chip *chip = mtd->priv;
394 uint8_t buf[2] = { 0, 0 }; 401 uint8_t buf[2] = { 0, 0 };
395 int block, ret, i = 0; 402 int block, res, ret = 0, i = 0;
403 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
396 404
397 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) 405 if (write_oob) {
398 ofs += mtd->erasesize - mtd->writesize; 406 struct erase_info einfo;
407
408 /* Attempt erase before marking OOB */
409 memset(&einfo, 0, sizeof(einfo));
410 einfo.mtd = mtd;
411 einfo.addr = ofs;
412 einfo.len = 1 << chip->phys_erase_shift;
413 nand_erase_nand(mtd, &einfo, 0);
414 }
399 415
400 /* Get block number */ 416 /* Get block number */
401 block = (int)(ofs >> chip->bbt_erase_shift); 417 block = (int)(ofs >> chip->bbt_erase_shift);
418 /* Mark block bad in memory-based BBT */
402 if (chip->bbt) 419 if (chip->bbt)
403 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); 420 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
404 421
405 /* Do we have a flash based bad block table? */ 422 /* Write bad block marker to OOB */
406 if (chip->bbt_options & NAND_BBT_USE_FLASH) 423 if (write_oob) {
407 ret = nand_update_bbt(mtd, ofs);
408 else {
409 struct mtd_oob_ops ops; 424 struct mtd_oob_ops ops;
425 loff_t wr_ofs = ofs;
410 426
411 nand_get_device(chip, mtd, FL_WRITING); 427 nand_get_device(chip, mtd, FL_WRITING);
412 428
413 /*
414 * Write to first two pages if necessary. If we write to more
415 * than one location, the first error encountered quits the
416 * procedure. We write two bytes per location, so we dont have
417 * to mess with 16 bit access.
418 */
419 ops.len = ops.ooblen = 2;
420 ops.datbuf = NULL; 429 ops.datbuf = NULL;
421 ops.oobbuf = buf; 430 ops.oobbuf = buf;
422 ops.ooboffs = chip->badblockpos & ~0x01; 431 ops.ooboffs = chip->badblockpos;
432 if (chip->options & NAND_BUSWIDTH_16) {
433 ops.ooboffs &= ~0x01;
434 ops.len = ops.ooblen = 2;
435 } else {
436 ops.len = ops.ooblen = 1;
437 }
423 ops.mode = MTD_OPS_PLACE_OOB; 438 ops.mode = MTD_OPS_PLACE_OOB;
439
440 /* Write to first/last page(s) if necessary */
441 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
442 wr_ofs += mtd->erasesize - mtd->writesize;
424 do { 443 do {
425 ret = nand_do_write_oob(mtd, ofs, &ops); 444 res = nand_do_write_oob(mtd, wr_ofs, &ops);
445 if (!ret)
446 ret = res;
426 447
427 i++; 448 i++;
428 ofs += mtd->writesize; 449 wr_ofs += mtd->writesize;
429 } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && 450 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
430 i < 2);
431 451
432 nand_release_device(mtd); 452 nand_release_device(mtd);
433 } 453 }
454
455 /* Update flash-based bad block table */
456 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
457 res = nand_update_bbt(mtd, ofs);
458 if (!ret)
459 ret = res;
460 }
461
434 if (!ret) 462 if (!ret)
435 mtd->ecc_stats.badblocks++; 463 mtd->ecc_stats.badblocks++;
436 464
@@ -1586,25 +1614,14 @@ static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1586 struct mtd_oob_ops ops; 1614 struct mtd_oob_ops ops;
1587 int ret; 1615 int ret;
1588 1616
1589 /* Do not allow reads past end of device */
1590 if ((from + len) > mtd->size)
1591 return -EINVAL;
1592 if (!len)
1593 return 0;
1594
1595 nand_get_device(chip, mtd, FL_READING); 1617 nand_get_device(chip, mtd, FL_READING);
1596
1597 ops.len = len; 1618 ops.len = len;
1598 ops.datbuf = buf; 1619 ops.datbuf = buf;
1599 ops.oobbuf = NULL; 1620 ops.oobbuf = NULL;
1600 ops.mode = 0; 1621 ops.mode = 0;
1601
1602 ret = nand_do_read_ops(mtd, from, &ops); 1622 ret = nand_do_read_ops(mtd, from, &ops);
1603
1604 *retlen = ops.retlen; 1623 *retlen = ops.retlen;
1605
1606 nand_release_device(mtd); 1624 nand_release_device(mtd);
1607
1608 return ret; 1625 return ret;
1609} 1626}
1610 1627
@@ -2293,12 +2310,6 @@ static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2293 struct mtd_oob_ops ops; 2310 struct mtd_oob_ops ops;
2294 int ret; 2311 int ret;
2295 2312
2296 /* Do not allow reads past end of device */
2297 if ((to + len) > mtd->size)
2298 return -EINVAL;
2299 if (!len)
2300 return 0;
2301
2302 /* Wait for the device to get ready */ 2313 /* Wait for the device to get ready */
2303 panic_nand_wait(mtd, chip, 400); 2314 panic_nand_wait(mtd, chip, 400);
2304 2315
@@ -2333,25 +2344,14 @@ static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2333 struct mtd_oob_ops ops; 2344 struct mtd_oob_ops ops;
2334 int ret; 2345 int ret;
2335 2346
2336 /* Do not allow reads past end of device */
2337 if ((to + len) > mtd->size)
2338 return -EINVAL;
2339 if (!len)
2340 return 0;
2341
2342 nand_get_device(chip, mtd, FL_WRITING); 2347 nand_get_device(chip, mtd, FL_WRITING);
2343
2344 ops.len = len; 2348 ops.len = len;
2345 ops.datbuf = (uint8_t *)buf; 2349 ops.datbuf = (uint8_t *)buf;
2346 ops.oobbuf = NULL; 2350 ops.oobbuf = NULL;
2347 ops.mode = 0; 2351 ops.mode = 0;
2348
2349 ret = nand_do_write_ops(mtd, to, &ops); 2352 ret = nand_do_write_ops(mtd, to, &ops);
2350
2351 *retlen = ops.retlen; 2353 *retlen = ops.retlen;
2352
2353 nand_release_device(mtd); 2354 nand_release_device(mtd);
2354
2355 return ret; 2355 return ret;
2356} 2356}
2357 2357
@@ -2550,8 +2550,6 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2550 if (check_offs_len(mtd, instr->addr, instr->len)) 2550 if (check_offs_len(mtd, instr->addr, instr->len))
2551 return -EINVAL; 2551 return -EINVAL;
2552 2552
2553 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2554
2555 /* Grab the lock and see if the device is available */ 2553 /* Grab the lock and see if the device is available */
2556 nand_get_device(chip, mtd, FL_ERASING); 2554 nand_get_device(chip, mtd, FL_ERASING);
2557 2555
@@ -2715,10 +2713,6 @@ static void nand_sync(struct mtd_info *mtd)
2715 */ 2713 */
2716static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) 2714static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2717{ 2715{
2718 /* Check for invalid offset */
2719 if (offs > mtd->size)
2720 return -EINVAL;
2721
2722 return nand_block_checkbad(mtd, offs, 1, 0); 2716 return nand_block_checkbad(mtd, offs, 1, 0);
2723} 2717}
2724 2718
@@ -2857,7 +2851,6 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2857 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') 2851 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2858 return 0; 2852 return 0;
2859 2853
2860 pr_info("ONFI flash detected\n");
2861 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); 2854 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2862 for (i = 0; i < 3; i++) { 2855 for (i = 0; i < 3; i++) {
2863 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); 2856 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
@@ -2898,7 +2891,8 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2898 mtd->writesize = le32_to_cpu(p->byte_per_page); 2891 mtd->writesize = le32_to_cpu(p->byte_per_page);
2899 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; 2892 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2900 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); 2893 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2901 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize; 2894 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2895 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2902 *busw = 0; 2896 *busw = 0;
2903 if (le16_to_cpu(p->features) & 1) 2897 if (le16_to_cpu(p->features) & 1)
2904 *busw = NAND_BUSWIDTH_16; 2898 *busw = NAND_BUSWIDTH_16;
@@ -2907,6 +2901,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2907 chip->options |= (NAND_NO_READRDY | 2901 chip->options |= (NAND_NO_READRDY |
2908 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK; 2902 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2909 2903
2904 pr_info("ONFI flash detected\n");
2910 return 1; 2905 return 1;
2911} 2906}
2912 2907
@@ -3238,6 +3233,10 @@ int nand_scan_tail(struct mtd_info *mtd)
3238 int i; 3233 int i;
3239 struct nand_chip *chip = mtd->priv; 3234 struct nand_chip *chip = mtd->priv;
3240 3235
3236 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3237 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3238 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3239
3241 if (!(chip->options & NAND_OWN_BUFFERS)) 3240 if (!(chip->options & NAND_OWN_BUFFERS))
3242 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); 3241 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3243 if (!chip->buffers) 3242 if (!chip->buffers)
@@ -3350,6 +3349,7 @@ int nand_scan_tail(struct mtd_info *mtd)
3350 if (!chip->ecc.size) 3349 if (!chip->ecc.size)
3351 chip->ecc.size = 256; 3350 chip->ecc.size = 256;
3352 chip->ecc.bytes = 3; 3351 chip->ecc.bytes = 3;
3352 chip->ecc.strength = 1;
3353 break; 3353 break;
3354 3354
3355 case NAND_ECC_SOFT_BCH: 3355 case NAND_ECC_SOFT_BCH:
@@ -3384,6 +3384,8 @@ int nand_scan_tail(struct mtd_info *mtd)
3384 pr_warn("BCH ECC initialization failed!\n"); 3384 pr_warn("BCH ECC initialization failed!\n");
3385 BUG(); 3385 BUG();
3386 } 3386 }
3387 chip->ecc.strength =
3388 chip->ecc.bytes*8 / fls(8*chip->ecc.size);
3387 break; 3389 break;
3388 3390
3389 case NAND_ECC_NONE: 3391 case NAND_ECC_NONE:
@@ -3397,6 +3399,7 @@ int nand_scan_tail(struct mtd_info *mtd)
3397 chip->ecc.write_oob = nand_write_oob_std; 3399 chip->ecc.write_oob = nand_write_oob_std;
3398 chip->ecc.size = mtd->writesize; 3400 chip->ecc.size = mtd->writesize;
3399 chip->ecc.bytes = 0; 3401 chip->ecc.bytes = 0;
3402 chip->ecc.strength = 0;
3400 break; 3403 break;
3401 3404
3402 default: 3405 default:
@@ -3461,25 +3464,26 @@ int nand_scan_tail(struct mtd_info *mtd)
3461 mtd->type = MTD_NANDFLASH; 3464 mtd->type = MTD_NANDFLASH;
3462 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : 3465 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3463 MTD_CAP_NANDFLASH; 3466 MTD_CAP_NANDFLASH;
3464 mtd->erase = nand_erase; 3467 mtd->_erase = nand_erase;
3465 mtd->point = NULL; 3468 mtd->_point = NULL;
3466 mtd->unpoint = NULL; 3469 mtd->_unpoint = NULL;
3467 mtd->read = nand_read; 3470 mtd->_read = nand_read;
3468 mtd->write = nand_write; 3471 mtd->_write = nand_write;
3469 mtd->panic_write = panic_nand_write; 3472 mtd->_panic_write = panic_nand_write;
3470 mtd->read_oob = nand_read_oob; 3473 mtd->_read_oob = nand_read_oob;
3471 mtd->write_oob = nand_write_oob; 3474 mtd->_write_oob = nand_write_oob;
3472 mtd->sync = nand_sync; 3475 mtd->_sync = nand_sync;
3473 mtd->lock = NULL; 3476 mtd->_lock = NULL;
3474 mtd->unlock = NULL; 3477 mtd->_unlock = NULL;
3475 mtd->suspend = nand_suspend; 3478 mtd->_suspend = nand_suspend;
3476 mtd->resume = nand_resume; 3479 mtd->_resume = nand_resume;
3477 mtd->block_isbad = nand_block_isbad; 3480 mtd->_block_isbad = nand_block_isbad;
3478 mtd->block_markbad = nand_block_markbad; 3481 mtd->_block_markbad = nand_block_markbad;
3479 mtd->writebufsize = mtd->writesize; 3482 mtd->writebufsize = mtd->writesize;
3480 3483
3481 /* propagate ecc.layout to mtd_info */ 3484 /* propagate ecc info to mtd_info */
3482 mtd->ecclayout = chip->ecc.layout; 3485 mtd->ecclayout = chip->ecc.layout;
3486 mtd->ecc_strength = chip->ecc.strength * chip->ecc.steps;
3483 3487
3484 /* Check, if we should skip the bad block table scan */ 3488 /* Check, if we should skip the bad block table scan */
3485 if (chip->options & NAND_SKIP_BBTSCAN) 3489 if (chip->options & NAND_SKIP_BBTSCAN)
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index ec688548c880..2b6f632cf274 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -179,6 +179,7 @@ static int ndfc_chip_init(struct ndfc_controller *ndfc,
179 chip->ecc.mode = NAND_ECC_HW; 179 chip->ecc.mode = NAND_ECC_HW;
180 chip->ecc.size = 256; 180 chip->ecc.size = 256;
181 chip->ecc.bytes = 3; 181 chip->ecc.bytes = 3;
182 chip->ecc.strength = 1;
182 chip->priv = ndfc; 183 chip->priv = ndfc;
183 184
184 ndfc->mtd.priv = chip; 185 ndfc->mtd.priv = chip;
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index b3a883e2a22f..c2b0bba9d8b3 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1058,6 +1058,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
1058 (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) { 1058 (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
1059 info->nand.ecc.bytes = 3; 1059 info->nand.ecc.bytes = 3;
1060 info->nand.ecc.size = 512; 1060 info->nand.ecc.size = 512;
1061 info->nand.ecc.strength = 1;
1061 info->nand.ecc.calculate = omap_calculate_ecc; 1062 info->nand.ecc.calculate = omap_calculate_ecc;
1062 info->nand.ecc.hwctl = omap_enable_hwecc; 1063 info->nand.ecc.hwctl = omap_enable_hwecc;
1063 info->nand.ecc.correct = omap_correct_data; 1064 info->nand.ecc.correct = omap_correct_data;
@@ -1101,8 +1102,8 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
1101 goto out_release_mem_region; 1102 goto out_release_mem_region;
1102 } 1103 }
1103 1104
1104 mtd_device_parse_register(&info->mtd, NULL, 0, 1105 mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts,
1105 pdata->parts, pdata->nr_parts); 1106 pdata->nr_parts);
1106 1107
1107 platform_set_drvdata(pdev, &info->mtd); 1108 platform_set_drvdata(pdev, &info->mtd);
1108 1109
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
index 29f505adaf84..1d3bfb26080c 100644
--- a/drivers/mtd/nand/orion_nand.c
+++ b/drivers/mtd/nand/orion_nand.c
@@ -129,8 +129,8 @@ static int __init orion_nand_probe(struct platform_device *pdev)
129 } 129 }
130 130
131 mtd->name = "orion_nand"; 131 mtd->name = "orion_nand";
132 ret = mtd_device_parse_register(mtd, NULL, 0, 132 ret = mtd_device_parse_register(mtd, NULL, NULL, board->parts,
133 board->parts, board->nr_parts); 133 board->nr_parts);
134 if (ret) { 134 if (ret) {
135 nand_release(mtd); 135 nand_release(mtd);
136 goto no_dev; 136 goto no_dev;
diff --git a/drivers/mtd/nand/plat_nand.c b/drivers/mtd/nand/plat_nand.c
index 7f2da6953357..6404e6e81b10 100644
--- a/drivers/mtd/nand/plat_nand.c
+++ b/drivers/mtd/nand/plat_nand.c
@@ -99,8 +99,9 @@ static int __devinit plat_nand_probe(struct platform_device *pdev)
99 } 99 }
100 100
101 err = mtd_device_parse_register(&data->mtd, 101 err = mtd_device_parse_register(&data->mtd,
102 pdata->chip.part_probe_types, 0, 102 pdata->chip.part_probe_types, NULL,
103 pdata->chip.partitions, pdata->chip.nr_partitions); 103 pdata->chip.partitions,
104 pdata->chip.nr_partitions);
104 105
105 if (!err) 106 if (!err)
106 return err; 107 return err;
diff --git a/drivers/mtd/nand/ppchameleonevb.c b/drivers/mtd/nand/ppchameleonevb.c
index 7e52af51a198..0ddd90e5788f 100644
--- a/drivers/mtd/nand/ppchameleonevb.c
+++ b/drivers/mtd/nand/ppchameleonevb.c
@@ -275,11 +275,10 @@ static int __init ppchameleonevb_init(void)
275 ppchameleon_mtd->name = "ppchameleon-nand"; 275 ppchameleon_mtd->name = "ppchameleon-nand";
276 276
277 /* Register the partitions */ 277 /* Register the partitions */
278 mtd_device_parse_register(ppchameleon_mtd, NULL, 0, 278 mtd_device_parse_register(ppchameleon_mtd, NULL, NULL,
279 ppchameleon_mtd->size == NAND_SMALL_SIZE ? 279 ppchameleon_mtd->size == NAND_SMALL_SIZE ?
280 partition_info_me : 280 partition_info_me : partition_info_hi,
281 partition_info_hi, 281 NUM_PARTITIONS);
282 NUM_PARTITIONS);
283 282
284 nand_evb_init: 283 nand_evb_init:
285 /**************************** 284 /****************************
@@ -365,11 +364,10 @@ static int __init ppchameleonevb_init(void)
365 ppchameleonevb_mtd->name = NAND_EVB_MTD_NAME; 364 ppchameleonevb_mtd->name = NAND_EVB_MTD_NAME;
366 365
367 /* Register the partitions */ 366 /* Register the partitions */
368 mtd_device_parse_register(ppchameleonevb_mtd, NULL, 0, 367 mtd_device_parse_register(ppchameleonevb_mtd, NULL, NULL,
369 ppchameleon_mtd->size == NAND_SMALL_SIZE ? 368 ppchameleon_mtd->size == NAND_SMALL_SIZE ?
370 partition_info_me : 369 partition_info_me : partition_info_hi,
371 partition_info_hi, 370 NUM_PARTITIONS);
372 NUM_PARTITIONS);
373 371
374 /* Return happy */ 372 /* Return happy */
375 return 0; 373 return 0;
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 5c3d719c37e6..def50caa6f84 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1002,6 +1002,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
1002KEEP_CONFIG: 1002KEEP_CONFIG:
1003 chip->ecc.mode = NAND_ECC_HW; 1003 chip->ecc.mode = NAND_ECC_HW;
1004 chip->ecc.size = host->page_size; 1004 chip->ecc.size = host->page_size;
1005 chip->ecc.strength = 1;
1005 1006
1006 chip->options = NAND_NO_AUTOINCR; 1007 chip->options = NAND_NO_AUTOINCR;
1007 chip->options |= NAND_NO_READRDY; 1008 chip->options |= NAND_NO_READRDY;
@@ -1228,8 +1229,9 @@ static int pxa3xx_nand_probe(struct platform_device *pdev)
1228 continue; 1229 continue;
1229 } 1230 }
1230 1231
1231 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL, 0, 1232 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL,
1232 pdata->parts[cs], pdata->nr_parts[cs]); 1233 NULL, pdata->parts[cs],
1234 pdata->nr_parts[cs]);
1233 if (!ret) 1235 if (!ret)
1234 probe_success = 1; 1236 probe_success = 1;
1235 } 1237 }
diff --git a/drivers/mtd/nand/r852.c b/drivers/mtd/nand/r852.c
index 769a4e096b3c..c2040187c813 100644
--- a/drivers/mtd/nand/r852.c
+++ b/drivers/mtd/nand/r852.c
@@ -891,6 +891,7 @@ int r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
891 chip->ecc.mode = NAND_ECC_HW_SYNDROME; 891 chip->ecc.mode = NAND_ECC_HW_SYNDROME;
892 chip->ecc.size = R852_DMA_LEN; 892 chip->ecc.size = R852_DMA_LEN;
893 chip->ecc.bytes = SM_OOB_SIZE; 893 chip->ecc.bytes = SM_OOB_SIZE;
894 chip->ecc.strength = 2;
894 chip->ecc.hwctl = r852_ecc_hwctl; 895 chip->ecc.hwctl = r852_ecc_hwctl;
895 chip->ecc.calculate = r852_ecc_calculate; 896 chip->ecc.calculate = r852_ecc_calculate;
896 chip->ecc.correct = r852_ecc_correct; 897 chip->ecc.correct = r852_ecc_correct;
diff --git a/drivers/mtd/nand/rtc_from4.c b/drivers/mtd/nand/rtc_from4.c
index f309addc2fa0..e55b5cfbe145 100644
--- a/drivers/mtd/nand/rtc_from4.c
+++ b/drivers/mtd/nand/rtc_from4.c
@@ -527,6 +527,7 @@ static int __init rtc_from4_init(void)
527 this->ecc.mode = NAND_ECC_HW_SYNDROME; 527 this->ecc.mode = NAND_ECC_HW_SYNDROME;
528 this->ecc.size = 512; 528 this->ecc.size = 512;
529 this->ecc.bytes = 8; 529 this->ecc.bytes = 8;
530 this->ecc.strength = 3;
530 /* return the status of extra status and ECC checks */ 531 /* return the status of extra status and ECC checks */
531 this->errstat = rtc_from4_errstat; 532 this->errstat = rtc_from4_errstat;
532 /* set the nand_oobinfo to support FPGA H/W error detection */ 533 /* set the nand_oobinfo to support FPGA H/W error detection */
diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
index 868685db6712..91121f33f743 100644
--- a/drivers/mtd/nand/s3c2410.c
+++ b/drivers/mtd/nand/s3c2410.c
@@ -751,8 +751,8 @@ static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
751 if (set) 751 if (set)
752 mtd->mtd.name = set->name; 752 mtd->mtd.name = set->name;
753 753
754 return mtd_device_parse_register(&mtd->mtd, NULL, 0, 754 return mtd_device_parse_register(&mtd->mtd, NULL, NULL,
755 set->partitions, set->nr_partitions); 755 set->partitions, set->nr_partitions);
756} 756}
757 757
758/** 758/**
@@ -823,6 +823,7 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
823 chip->ecc.calculate = s3c2410_nand_calculate_ecc; 823 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
824 chip->ecc.correct = s3c2410_nand_correct_data; 824 chip->ecc.correct = s3c2410_nand_correct_data;
825 chip->ecc.mode = NAND_ECC_HW; 825 chip->ecc.mode = NAND_ECC_HW;
826 chip->ecc.strength = 1;
826 827
827 switch (info->cpu_type) { 828 switch (info->cpu_type) {
828 case TYPE_S3C2410: 829 case TYPE_S3C2410:
diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 93b1f74321c2..e9b2b260de3a 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -26,6 +26,7 @@
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/io.h> 27#include <linux/io.h>
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
29#include <linux/slab.h> 30#include <linux/slab.h>
30 31
31#include <linux/mtd/mtd.h> 32#include <linux/mtd/mtd.h>
@@ -283,7 +284,7 @@ static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
283static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val) 284static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val)
284{ 285{
285 struct sh_flctl *flctl = mtd_to_flctl(mtd); 286 struct sh_flctl *flctl = mtd_to_flctl(mtd);
286 uint32_t flcmncr_val = readl(FLCMNCR(flctl)) & ~SEL_16BIT; 287 uint32_t flcmncr_val = flctl->flcmncr_base & ~SEL_16BIT;
287 uint32_t flcmdcr_val, addr_len_bytes = 0; 288 uint32_t flcmdcr_val, addr_len_bytes = 0;
288 289
289 /* Set SNAND bit if page size is 2048byte */ 290 /* Set SNAND bit if page size is 2048byte */
@@ -303,6 +304,7 @@ static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_va
303 break; 304 break;
304 case NAND_CMD_READ0: 305 case NAND_CMD_READ0:
305 case NAND_CMD_READOOB: 306 case NAND_CMD_READOOB:
307 case NAND_CMD_RNDOUT:
306 addr_len_bytes = flctl->rw_ADRCNT; 308 addr_len_bytes = flctl->rw_ADRCNT;
307 flcmdcr_val |= CDSRC_E; 309 flcmdcr_val |= CDSRC_E;
308 if (flctl->chip.options & NAND_BUSWIDTH_16) 310 if (flctl->chip.options & NAND_BUSWIDTH_16)
@@ -320,6 +322,7 @@ static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_va
320 break; 322 break;
321 case NAND_CMD_READID: 323 case NAND_CMD_READID:
322 flcmncr_val &= ~SNAND_E; 324 flcmncr_val &= ~SNAND_E;
325 flcmdcr_val |= CDSRC_E;
323 addr_len_bytes = ADRCNT_1; 326 addr_len_bytes = ADRCNT_1;
324 break; 327 break;
325 case NAND_CMD_STATUS: 328 case NAND_CMD_STATUS:
@@ -513,6 +516,8 @@ static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
513 struct sh_flctl *flctl = mtd_to_flctl(mtd); 516 struct sh_flctl *flctl = mtd_to_flctl(mtd);
514 uint32_t read_cmd = 0; 517 uint32_t read_cmd = 0;
515 518
519 pm_runtime_get_sync(&flctl->pdev->dev);
520
516 flctl->read_bytes = 0; 521 flctl->read_bytes = 0;
517 if (command != NAND_CMD_PAGEPROG) 522 if (command != NAND_CMD_PAGEPROG)
518 flctl->index = 0; 523 flctl->index = 0;
@@ -525,7 +530,6 @@ static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
525 execmd_read_page_sector(mtd, page_addr); 530 execmd_read_page_sector(mtd, page_addr);
526 break; 531 break;
527 } 532 }
528 empty_fifo(flctl);
529 if (flctl->page_size) 533 if (flctl->page_size)
530 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8) 534 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
531 | command); 535 | command);
@@ -547,7 +551,6 @@ static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
547 break; 551 break;
548 } 552 }
549 553
550 empty_fifo(flctl);
551 if (flctl->page_size) { 554 if (flctl->page_size) {
552 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8) 555 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
553 | NAND_CMD_READ0); 556 | NAND_CMD_READ0);
@@ -559,15 +562,35 @@ static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
559 flctl->read_bytes = mtd->oobsize; 562 flctl->read_bytes = mtd->oobsize;
560 goto read_normal_exit; 563 goto read_normal_exit;
561 564
565 case NAND_CMD_RNDOUT:
566 if (flctl->hwecc)
567 break;
568
569 if (flctl->page_size)
570 set_cmd_regs(mtd, command, (NAND_CMD_RNDOUTSTART << 8)
571 | command);
572 else
573 set_cmd_regs(mtd, command, command);
574
575 set_addr(mtd, column, 0);
576
577 flctl->read_bytes = mtd->writesize + mtd->oobsize - column;
578 goto read_normal_exit;
579
562 case NAND_CMD_READID: 580 case NAND_CMD_READID:
563 empty_fifo(flctl);
564 set_cmd_regs(mtd, command, command); 581 set_cmd_regs(mtd, command, command);
565 set_addr(mtd, 0, 0);
566 582
567 flctl->read_bytes = 4; 583 /* READID is always performed using an 8-bit bus */
584 if (flctl->chip.options & NAND_BUSWIDTH_16)
585 column <<= 1;
586 set_addr(mtd, column, 0);
587
588 flctl->read_bytes = 8;
568 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */ 589 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
590 empty_fifo(flctl);
569 start_translation(flctl); 591 start_translation(flctl);
570 read_datareg(flctl, 0); /* read and end */ 592 read_fiforeg(flctl, flctl->read_bytes, 0);
593 wait_completion(flctl);
571 break; 594 break;
572 595
573 case NAND_CMD_ERASE1: 596 case NAND_CMD_ERASE1:
@@ -650,29 +673,55 @@ static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
650 default: 673 default:
651 break; 674 break;
652 } 675 }
653 return; 676 goto runtime_exit;
654 677
655read_normal_exit: 678read_normal_exit:
656 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */ 679 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
680 empty_fifo(flctl);
657 start_translation(flctl); 681 start_translation(flctl);
658 read_fiforeg(flctl, flctl->read_bytes, 0); 682 read_fiforeg(flctl, flctl->read_bytes, 0);
659 wait_completion(flctl); 683 wait_completion(flctl);
684runtime_exit:
685 pm_runtime_put_sync(&flctl->pdev->dev);
660 return; 686 return;
661} 687}
662 688
663static void flctl_select_chip(struct mtd_info *mtd, int chipnr) 689static void flctl_select_chip(struct mtd_info *mtd, int chipnr)
664{ 690{
665 struct sh_flctl *flctl = mtd_to_flctl(mtd); 691 struct sh_flctl *flctl = mtd_to_flctl(mtd);
666 uint32_t flcmncr_val = readl(FLCMNCR(flctl)); 692 int ret;
667 693
668 switch (chipnr) { 694 switch (chipnr) {
669 case -1: 695 case -1:
670 flcmncr_val &= ~CE0_ENABLE; 696 flctl->flcmncr_base &= ~CE0_ENABLE;
671 writel(flcmncr_val, FLCMNCR(flctl)); 697
698 pm_runtime_get_sync(&flctl->pdev->dev);
699 writel(flctl->flcmncr_base, FLCMNCR(flctl));
700
701 if (flctl->qos_request) {
702 dev_pm_qos_remove_request(&flctl->pm_qos);
703 flctl->qos_request = 0;
704 }
705
706 pm_runtime_put_sync(&flctl->pdev->dev);
672 break; 707 break;
673 case 0: 708 case 0:
674 flcmncr_val |= CE0_ENABLE; 709 flctl->flcmncr_base |= CE0_ENABLE;
675 writel(flcmncr_val, FLCMNCR(flctl)); 710
711 if (!flctl->qos_request) {
712 ret = dev_pm_qos_add_request(&flctl->pdev->dev,
713 &flctl->pm_qos, 100);
714 if (ret < 0)
715 dev_err(&flctl->pdev->dev,
716 "PM QoS request failed: %d\n", ret);
717 flctl->qos_request = 1;
718 }
719
720 if (flctl->holden) {
721 pm_runtime_get_sync(&flctl->pdev->dev);
722 writel(HOLDEN, FLHOLDCR(flctl));
723 pm_runtime_put_sync(&flctl->pdev->dev);
724 }
676 break; 725 break;
677 default: 726 default:
678 BUG(); 727 BUG();
@@ -730,11 +779,6 @@ static int flctl_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
730 return 0; 779 return 0;
731} 780}
732 781
733static void flctl_register_init(struct sh_flctl *flctl, unsigned long val)
734{
735 writel(val, FLCMNCR(flctl));
736}
737
738static int flctl_chip_init_tail(struct mtd_info *mtd) 782static int flctl_chip_init_tail(struct mtd_info *mtd)
739{ 783{
740 struct sh_flctl *flctl = mtd_to_flctl(mtd); 784 struct sh_flctl *flctl = mtd_to_flctl(mtd);
@@ -781,13 +825,13 @@ static int flctl_chip_init_tail(struct mtd_info *mtd)
781 825
782 chip->ecc.size = 512; 826 chip->ecc.size = 512;
783 chip->ecc.bytes = 10; 827 chip->ecc.bytes = 10;
828 chip->ecc.strength = 4;
784 chip->ecc.read_page = flctl_read_page_hwecc; 829 chip->ecc.read_page = flctl_read_page_hwecc;
785 chip->ecc.write_page = flctl_write_page_hwecc; 830 chip->ecc.write_page = flctl_write_page_hwecc;
786 chip->ecc.mode = NAND_ECC_HW; 831 chip->ecc.mode = NAND_ECC_HW;
787 832
788 /* 4 symbols ECC enabled */ 833 /* 4 symbols ECC enabled */
789 writel(readl(FLCMNCR(flctl)) | _4ECCEN | ECCPOS2 | ECCPOS_02, 834 flctl->flcmncr_base |= _4ECCEN | ECCPOS2 | ECCPOS_02;
790 FLCMNCR(flctl));
791 } else { 835 } else {
792 chip->ecc.mode = NAND_ECC_SOFT; 836 chip->ecc.mode = NAND_ECC_SOFT;
793 } 837 }
@@ -819,13 +863,13 @@ static int __devinit flctl_probe(struct platform_device *pdev)
819 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 863 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
820 if (!res) { 864 if (!res) {
821 dev_err(&pdev->dev, "failed to get I/O memory\n"); 865 dev_err(&pdev->dev, "failed to get I/O memory\n");
822 goto err; 866 goto err_iomap;
823 } 867 }
824 868
825 flctl->reg = ioremap(res->start, resource_size(res)); 869 flctl->reg = ioremap(res->start, resource_size(res));
826 if (flctl->reg == NULL) { 870 if (flctl->reg == NULL) {
827 dev_err(&pdev->dev, "failed to remap I/O memory\n"); 871 dev_err(&pdev->dev, "failed to remap I/O memory\n");
828 goto err; 872 goto err_iomap;
829 } 873 }
830 874
831 platform_set_drvdata(pdev, flctl); 875 platform_set_drvdata(pdev, flctl);
@@ -833,9 +877,9 @@ static int __devinit flctl_probe(struct platform_device *pdev)
833 nand = &flctl->chip; 877 nand = &flctl->chip;
834 flctl_mtd->priv = nand; 878 flctl_mtd->priv = nand;
835 flctl->pdev = pdev; 879 flctl->pdev = pdev;
880 flctl->flcmncr_base = pdata->flcmncr_val;
836 flctl->hwecc = pdata->has_hwecc; 881 flctl->hwecc = pdata->has_hwecc;
837 882 flctl->holden = pdata->use_holden;
838 flctl_register_init(flctl, pdata->flcmncr_val);
839 883
840 nand->options = NAND_NO_AUTOINCR; 884 nand->options = NAND_NO_AUTOINCR;
841 885
@@ -855,23 +899,28 @@ static int __devinit flctl_probe(struct platform_device *pdev)
855 nand->read_word = flctl_read_word; 899 nand->read_word = flctl_read_word;
856 } 900 }
857 901
902 pm_runtime_enable(&pdev->dev);
903 pm_runtime_resume(&pdev->dev);
904
858 ret = nand_scan_ident(flctl_mtd, 1, NULL); 905 ret = nand_scan_ident(flctl_mtd, 1, NULL);
859 if (ret) 906 if (ret)
860 goto err; 907 goto err_chip;
861 908
862 ret = flctl_chip_init_tail(flctl_mtd); 909 ret = flctl_chip_init_tail(flctl_mtd);
863 if (ret) 910 if (ret)
864 goto err; 911 goto err_chip;
865 912
866 ret = nand_scan_tail(flctl_mtd); 913 ret = nand_scan_tail(flctl_mtd);
867 if (ret) 914 if (ret)
868 goto err; 915 goto err_chip;
869 916
870 mtd_device_register(flctl_mtd, pdata->parts, pdata->nr_parts); 917 mtd_device_register(flctl_mtd, pdata->parts, pdata->nr_parts);
871 918
872 return 0; 919 return 0;
873 920
874err: 921err_chip:
922 pm_runtime_disable(&pdev->dev);
923err_iomap:
875 kfree(flctl); 924 kfree(flctl);
876 return ret; 925 return ret;
877} 926}
@@ -881,6 +930,7 @@ static int __devexit flctl_remove(struct platform_device *pdev)
881 struct sh_flctl *flctl = platform_get_drvdata(pdev); 930 struct sh_flctl *flctl = platform_get_drvdata(pdev);
882 931
883 nand_release(&flctl->mtd); 932 nand_release(&flctl->mtd);
933 pm_runtime_disable(&pdev->dev);
884 kfree(flctl); 934 kfree(flctl);
885 935
886 return 0; 936 return 0;
diff --git a/drivers/mtd/nand/sharpsl.c b/drivers/mtd/nand/sharpsl.c
index b175c0fd8b93..3421e3762a5a 100644
--- a/drivers/mtd/nand/sharpsl.c
+++ b/drivers/mtd/nand/sharpsl.c
@@ -167,6 +167,7 @@ static int __devinit sharpsl_nand_probe(struct platform_device *pdev)
167 this->ecc.mode = NAND_ECC_HW; 167 this->ecc.mode = NAND_ECC_HW;
168 this->ecc.size = 256; 168 this->ecc.size = 256;
169 this->ecc.bytes = 3; 169 this->ecc.bytes = 3;
170 this->ecc.strength = 1;
170 this->badblock_pattern = data->badblock_pattern; 171 this->badblock_pattern = data->badblock_pattern;
171 this->ecc.layout = data->ecc_layout; 172 this->ecc.layout = data->ecc_layout;
172 this->ecc.hwctl = sharpsl_nand_enable_hwecc; 173 this->ecc.hwctl = sharpsl_nand_enable_hwecc;
@@ -181,8 +182,8 @@ static int __devinit sharpsl_nand_probe(struct platform_device *pdev)
181 /* Register the partitions */ 182 /* Register the partitions */
182 sharpsl->mtd.name = "sharpsl-nand"; 183 sharpsl->mtd.name = "sharpsl-nand";
183 184
184 err = mtd_device_parse_register(&sharpsl->mtd, NULL, 0, 185 err = mtd_device_parse_register(&sharpsl->mtd, NULL, NULL,
185 data->partitions, data->nr_partitions); 186 data->partitions, data->nr_partitions);
186 if (err) 187 if (err)
187 goto err_add; 188 goto err_add;
188 189
diff --git a/drivers/mtd/nand/tmio_nand.c b/drivers/mtd/nand/tmio_nand.c
index 6caa0cd9d6a7..5aa518081c51 100644
--- a/drivers/mtd/nand/tmio_nand.c
+++ b/drivers/mtd/nand/tmio_nand.c
@@ -430,6 +430,7 @@ static int tmio_probe(struct platform_device *dev)
430 nand_chip->ecc.mode = NAND_ECC_HW; 430 nand_chip->ecc.mode = NAND_ECC_HW;
431 nand_chip->ecc.size = 512; 431 nand_chip->ecc.size = 512;
432 nand_chip->ecc.bytes = 6; 432 nand_chip->ecc.bytes = 6;
433 nand_chip->ecc.strength = 2;
433 nand_chip->ecc.hwctl = tmio_nand_enable_hwecc; 434 nand_chip->ecc.hwctl = tmio_nand_enable_hwecc;
434 nand_chip->ecc.calculate = tmio_nand_calculate_ecc; 435 nand_chip->ecc.calculate = tmio_nand_calculate_ecc;
435 nand_chip->ecc.correct = tmio_nand_correct_data; 436 nand_chip->ecc.correct = tmio_nand_correct_data;
@@ -456,9 +457,9 @@ static int tmio_probe(struct platform_device *dev)
456 goto err_scan; 457 goto err_scan;
457 } 458 }
458 /* Register the partitions */ 459 /* Register the partitions */
459 retval = mtd_device_parse_register(mtd, NULL, 0, 460 retval = mtd_device_parse_register(mtd, NULL, NULL,
460 data ? data->partition : NULL, 461 data ? data->partition : NULL,
461 data ? data->num_partitions : 0); 462 data ? data->num_partitions : 0);
462 if (!retval) 463 if (!retval)
463 return retval; 464 return retval;
464 465
diff --git a/drivers/mtd/nand/txx9ndfmc.c b/drivers/mtd/nand/txx9ndfmc.c
index c7c4f1d11c77..26398dcf21cf 100644
--- a/drivers/mtd/nand/txx9ndfmc.c
+++ b/drivers/mtd/nand/txx9ndfmc.c
@@ -356,6 +356,7 @@ static int __init txx9ndfmc_probe(struct platform_device *dev)
356 /* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */ 356 /* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */
357 chip->ecc.size = 256; 357 chip->ecc.size = 256;
358 chip->ecc.bytes = 3; 358 chip->ecc.bytes = 3;
359 chip->ecc.strength = 1;
359 chip->chip_delay = 100; 360 chip->chip_delay = 100;
360 chip->controller = &drvdata->hw_control; 361 chip->controller = &drvdata->hw_control;
361 362
@@ -386,7 +387,7 @@ static int __init txx9ndfmc_probe(struct platform_device *dev)
386 } 387 }
387 mtd->name = txx9_priv->mtdname; 388 mtd->name = txx9_priv->mtdname;
388 389
389 mtd_device_parse_register(mtd, NULL, 0, NULL, 0); 390 mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
390 drvdata->mtds[i] = mtd; 391 drvdata->mtds[i] = mtd;
391 } 392 }
392 393
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-11 07:27:11 -0400