diff options
author | Huang Shijie <b32955@freescale.com> | 2012-09-13 02:57:57 -0400 |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-09-29 10:55:54 -0400 |
commit | c50d35a9fdb628c5fcce5c2d4ab5ad9bedb2edb9 (patch) | |
tree | 12f5fca644d4dff62f43186240a6f1825e97f3e8 /drivers/mtd/nand/gpmi-nand | |
parent | d37e02d8f3a892b57738f1c1431779d5939214d1 (diff) |
mtd: gpmi: simplify the DLL setting code
The setting DLL code is a little mess.
Just simplify the code and the comments.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd/nand/gpmi-nand')
-rw-r--r-- | drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 22 |
1 files changed, 9 insertions, 13 deletions
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c index 2d1f77c0527e..010665ca631a 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c | |||
@@ -779,30 +779,26 @@ void gpmi_begin(struct gpmi_nand_data *this) | |||
779 | writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR); | 779 | writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR); |
780 | 780 | ||
781 | /* Clear out the DLL control fields. */ | 781 | /* Clear out the DLL control fields. */ |
782 | writel(BM_GPMI_CTRL1_RDN_DELAY, gpmi_regs + HW_GPMI_CTRL1_CLR); | 782 | reg = BM_GPMI_CTRL1_RDN_DELAY | BM_GPMI_CTRL1_HALF_PERIOD; |
783 | writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR); | 783 | writel(reg, gpmi_regs + HW_GPMI_CTRL1_CLR); |
784 | 784 | ||
785 | /* If no sample delay is called for, return immediately. */ | 785 | /* If no sample delay is called for, return immediately. */ |
786 | if (!hw.sample_delay_factor) | 786 | if (!hw.sample_delay_factor) |
787 | return; | 787 | return; |
788 | 788 | ||
789 | /* Configure the HALF_PERIOD flag. */ | 789 | /* Set RDN_DELAY or HALF_PERIOD. */ |
790 | if (hw.use_half_periods) | 790 | reg = ((hw.use_half_periods) ? BM_GPMI_CTRL1_HALF_PERIOD : 0) |
791 | writel(BM_GPMI_CTRL1_HALF_PERIOD, | 791 | | BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor); |
792 | gpmi_regs + HW_GPMI_CTRL1_SET); | ||
793 | 792 | ||
794 | /* Set the delay factor. */ | 793 | writel(reg, gpmi_regs + HW_GPMI_CTRL1_SET); |
795 | writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor), | ||
796 | gpmi_regs + HW_GPMI_CTRL1_SET); | ||
797 | 794 | ||
798 | /* Enable the DLL. */ | 795 | /* At last, we enable the DLL. */ |
799 | writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET); | 796 | writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET); |
800 | 797 | ||
801 | /* | 798 | /* |
802 | * After we enable the GPMI DLL, we have to wait 64 clock cycles before | 799 | * After we enable the GPMI DLL, we have to wait 64 clock cycles before |
803 | * we can use the GPMI. | 800 | * we can use the GPMI. Calculate the amount of time we need to wait, |
804 | * | 801 | * in microseconds. |
805 | * Calculate the amount of time we need to wait, in microseconds. | ||
806 | */ | 802 | */ |
807 | clock_period_in_ns = NSEC_PER_SEC / clk_get_rate(r->clock[0]); | 803 | clock_period_in_ns = NSEC_PER_SEC / clk_get_rate(r->clock[0]); |
808 | dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000; | 804 | dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000; |