Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master

29 files changed, 3218 insertions, 786 deletions

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 432ae8358c86..2e13b94769fd 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -44,6 +44,19 @@ config MMC_SDHCI_IO_ACCESSORS
           This is silent Kconfig symbol that is selected by the drivers that
           need to overwrite SDHCI IO memory accessors.
 
+config MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
+        bool
+        select MMC_SDHCI_IO_ACCESSORS
+        help
+          This option is selected by drivers running on big endian hosts
+          and performing I/O to a SDHCI controller through a bus that
+          implements a hardware byte swapper using a 32-bit datum.
+          This endian mapping mode is called "data invariance" and
+          has the effect of scrambling the addresses and formats of data
+          accessed in sizes other than the datum size.
+
+          This is the case for the Freescale eSDHC and Nintendo Wii SDHCI.
+
 config MMC_SDHCI_PCI
         tristate "SDHCI support on PCI bus"
         depends on MMC_SDHCI && PCI
@@ -56,30 +69,44 @@ config MMC_SDHCI_PCI
           If unsure, say N.
 
 config MMC_RICOH_MMC
-        tristate "Ricoh MMC Controller Disabler  (EXPERIMENTAL)"
+        bool "Ricoh MMC Controller Disabler  (EXPERIMENTAL)"
         depends on MMC_SDHCI_PCI
         help
-          This selects the disabler for the Ricoh MMC Controller. This
+          This adds a pci quirk to disable Ricoh MMC Controller. This
           proprietary controller is unnecessary because the SDHCI driver
           supports MMC cards on the SD controller, but if it is not
           disabled, it will steal the MMC cards away - rendering them
-          useless. It is safe to select this driver even if you don't
+          useless. It is safe to select this even if you don't
           have a Ricoh based card reader.
 
-
-          To compile this driver as a module, choose M here:
-          the module will be called ricoh_mmc.
-
           If unsure, say Y.
 
 config MMC_SDHCI_OF
         tristate "SDHCI support on OpenFirmware platforms"
         depends on MMC_SDHCI && PPC_OF
-        select MMC_SDHCI_IO_ACCESSORS
         help
           This selects the OF support for Secure Digital Host Controller
-          Interfaces. So far, only the Freescale eSDHC controller is known
-          to exist on OF platforms.
+          Interfaces.
+
+          If unsure, say N.
+
+config MMC_SDHCI_OF_ESDHC
+        bool "SDHCI OF support for the Freescale eSDHC controller"
+        depends on MMC_SDHCI_OF
+        select MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
+        help
+          This selects the Freescale eSDHC controller support.
+
+          If unsure, say N.
+
+config MMC_SDHCI_OF_HLWD
+        bool "SDHCI OF support for the Nintendo Wii SDHCI controllers"
+        depends on MMC_SDHCI_OF
+        select MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
+        help
+          This selects the Secure Digital Host Controller Interface (SDHCI)
+          found in the "Hollywood" chipset of the Nintendo Wii video game
+          console.
 
           If unsure, say N.
 
@@ -162,6 +189,7 @@ config MMC_AU1X
 
 choice
         prompt "Atmel SD/MMC Driver"
+        depends on AVR32 || ARCH_AT91
         default MMC_ATMELMCI if AVR32
         help
           Choose which driver to use for the Atmel MCI Silicon
@@ -251,6 +279,14 @@ config MMC_MVSDIO
           To compile this driver as a module, choose M here: the
           module will be called mvsdio.
 
+config MMC_DAVINCI
+        tristate "TI DAVINCI Multimedia Card Interface support"
+        depends on ARCH_DAVINCI
+        help
+          This selects the TI DAVINCI Multimedia card Interface.
+          If you have an DAVINCI board with a Multimedia Card slot,
+          say Y or M here.  If unsure, say N.
+
 config MMC_SPI
         tristate "MMC/SD/SDIO over SPI"
         depends on SPI_MASTER && !HIGHMEM && HAS_DMA
@@ -329,7 +365,7 @@ config MMC_SDRICOH_CS
 
 config MMC_TMIO
         tristate "Toshiba Mobile IO Controller (TMIO) MMC/SD function support"
-        depends on MFD_TMIO || MFD_ASIC3
+        depends on MFD_TMIO || MFD_ASIC3 || MFD_SH_MOBILE_SDHI
         help
           This provides support for the SD/MMC cell found in TC6393XB,
           T7L66XB and also HTC ASIC3
@@ -357,3 +393,22 @@ config MMC_VIA_SDMMC
           If you have a controller with this interface, say Y or M here.
 
           If unsure, say N.
+
+config SDH_BFIN
+        tristate "Blackfin Secure Digital Host support"
+        depends on (BF54x && !BF544) || (BF51x && !BF512)
+        help
+          If you say yes here you will get support for the Blackfin on-chip
+          Secure Digital Host interface.  This includes support for MMC and
+          SD cards.
+
+          To compile this driver as a module, choose M here: the
+          module will be called bfin_sdh.
+
+          If unsure, say N.
+
+config SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
+        bool "Blackfin EZkit Missing SDH_CMD Pull Up Resistor Workaround"
+        depends on SDH_BFIN
+        help
+          If you say yes here SD-Cards may work on the EZkit.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index abcb0400e06d..f4803977dfce 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -12,8 +12,6 @@ obj-$(CONFIG_MMC_IMX)		+= imxmmc.o
 obj-$(CONFIG_MMC_MXC)           += mxcmmc.o
 obj-$(CONFIG_MMC_SDHCI)         += sdhci.o
 obj-$(CONFIG_MMC_SDHCI_PCI)     += sdhci-pci.o
-obj-$(CONFIG_MMC_RICOH_MMC)     += ricoh_mmc.o
-obj-$(CONFIG_MMC_SDHCI_OF)      += sdhci-of.o
 obj-$(CONFIG_MMC_SDHCI_PLTFM)   += sdhci-pltfm.o
 obj-$(CONFIG_MMC_SDHCI_S3C)     += sdhci-s3c.o
 obj-$(CONFIG_MMC_WBSD)          += wbsd.o
@@ -25,6 +23,7 @@ obj-$(CONFIG_MMC_ATMELMCI)	+= atmel-mci.o
 obj-$(CONFIG_MMC_TIFM_SD)       += tifm_sd.o
 obj-$(CONFIG_MMC_MSM7X00A)      += msm_sdcc.o
 obj-$(CONFIG_MMC_MVSDIO)        += mvsdio.o
+obj-$(CONFIG_MMC_DAVINCI)       += davinci_mmc.o
 obj-$(CONFIG_MMC_SPI)           += mmc_spi.o
 ifeq ($(CONFIG_OF),y)
 obj-$(CONFIG_MMC_SPI)           += of_mmc_spi.o
@@ -34,6 +33,12 @@ obj-$(CONFIG_MMC_SDRICOH_CS)	+= sdricoh_cs.o
 obj-$(CONFIG_MMC_TMIO)          += tmio_mmc.o
 obj-$(CONFIG_MMC_CB710) += cb710-mmc.o
 obj-$(CONFIG_MMC_VIA_SDMMC)     += via-sdmmc.o
+obj-$(CONFIG_SDH_BFIN)          += bfin_sdh.o
+
+obj-$(CONFIG_MMC_SDHCI_OF)      += sdhci-of.o
+sdhci-of-y                              := sdhci-of-core.o
+sdhci-of-$(CONFIG_MMC_SDHCI_OF_ESDHC)   += sdhci-of-esdhc.o
+sdhci-of-$(CONFIG_MMC_SDHCI_OF_HLWD)    += sdhci-of-hlwd.o
 
 ifeq ($(CONFIG_CB710_DEBUG),y)
         CFLAGS-cb710-mmc        += -DDEBUG
diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c
index 63924e0c7ea9..336d9f553f3e 100644
--- a/drivers/mmc/host/at91_mci.c
+++ b/drivers/mmc/host/at91_mci.c
@@ -65,6 +65,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/clk.h>
 #include <linux/atmel_pdc.h>
+#include <linux/gfp.h>
 
 #include <linux/mmc/host.h>
 
@@ -78,6 +79,17 @@
 
 #define DRIVER_NAME "at91_mci"
 
+static inline int at91mci_is_mci1rev2xx(void)
+{
+        return (   cpu_is_at91sam9260()
+                || cpu_is_at91sam9263()
+                || cpu_is_at91cap9()
+                || cpu_is_at91sam9rl()
+                || cpu_is_at91sam9g10()
+                || cpu_is_at91sam9g20()
+                );
+}
+
 #define FL_SENT_COMMAND (1 << 0)
 #define FL_SENT_STOP    (1 << 1)
 
@@ -88,6 +100,10 @@
 #define at91_mci_read(host, reg)        __raw_readl((host)->baseaddr + (reg))
 #define at91_mci_write(host, reg, val)  __raw_writel((val), (host)->baseaddr + (reg))
 
+#define MCI_BLKSIZE             512
+#define MCI_MAXBLKSIZE          4095
+#define MCI_BLKATONCE           256
+#define MCI_BUFSIZE             (MCI_BLKSIZE * MCI_BLKATONCE)
 
 /*
  * Low level type for this driver
@@ -200,8 +216,8 @@ static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data
         size = data->blksz * data->blocks;
         len = data->sg_len;
 
-        /* AT91SAM926[0/3] Data Write Operation and number of bytes erratum */
-        if (cpu_is_at91sam9260() || cpu_is_at91sam9263())
+        /* MCI1 rev2xx Data Write Operation and number of bytes erratum */
+        if (at91mci_is_mci1rev2xx())
                 if (host->total_length == 12)
                         memset(dmabuf, 0, 12);
 
@@ -227,8 +243,10 @@ static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data
                         for (index = 0; index < (amount / 4); index++)
                                 *dmabuf++ = swab32(sgbuffer[index]);
                 } else {
-                        memcpy(dmabuf, sgbuffer, amount);
-                        dmabuf += amount;
+                        char *tmpv = (char *)dmabuf;
+                        memcpy(tmpv, sgbuffer, amount);
+                        tmpv += amount;
+                        dmabuf = (unsigned *)tmpv;
                 }
 
                 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
@@ -245,80 +263,14 @@ static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data
 }
 
 /*
- * Prepare a dma read
- */
-static void at91_mci_pre_dma_read(struct at91mci_host *host)
-{
-        int i;
-        struct scatterlist *sg;
-        struct mmc_command *cmd;
-        struct mmc_data *data;
-
-        pr_debug("pre dma read\n");
-
-        cmd = host->cmd;
-        if (!cmd) {
-                pr_debug("no command\n");
-                return;
-        }
-
-        data = cmd->data;
-        if (!data) {
-                pr_debug("no data\n");
-                return;
-        }
-
-        for (i = 0; i < 2; i++) {
-                /* nothing left to transfer */
-                if (host->transfer_index >= data->sg_len) {
-                        pr_debug("Nothing left to transfer (index = %d)\n", host->transfer_index);
-                        break;
-                }
-
-                /* Check to see if this needs filling */
-                if (i == 0) {
-                        if (at91_mci_read(host, ATMEL_PDC_RCR) != 0) {
-                                pr_debug("Transfer active in current\n");
-                                continue;
-                        }
-                }
-                else {
-                        if (at91_mci_read(host, ATMEL_PDC_RNCR) != 0) {
-                                pr_debug("Transfer active in next\n");
-                                continue;
-                        }
-                }
-
-                /* Setup the next transfer */
-                pr_debug("Using transfer index %d\n", host->transfer_index);
-
-                sg = &data->sg[host->transfer_index++];
-                pr_debug("sg = %p\n", sg);
-
-                sg->dma_address = dma_map_page(NULL, sg_page(sg), sg->offset, sg->length, DMA_FROM_DEVICE);
-
-                pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length);
-
-                if (i == 0) {
-                        at91_mci_write(host, ATMEL_PDC_RPR, sg->dma_address);
-                        at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ? sg->length : sg->length / 4);
-                }
-                else {
-                        at91_mci_write(host, ATMEL_PDC_RNPR, sg->dma_address);
-                        at91_mci_write(host, ATMEL_PDC_RNCR, (data->blksz & 0x3) ? sg->length : sg->length / 4);
-                }
-        }
-
-        pr_debug("pre dma read done\n");
-}
-
-/*
  * Handle after a dma read
  */
 static void at91_mci_post_dma_read(struct at91mci_host *host)
 {
         struct mmc_command *cmd;
         struct mmc_data *data;
+        unsigned int len, i, size;
+        unsigned *dmabuf = host->buffer;
 
         pr_debug("post dma read\n");
 
@@ -334,42 +286,39 @@ static void at91_mci_post_dma_read(struct at91mci_host *host)
                 return;
         }
 
-        while (host->in_use_index < host->transfer_index) {
-                struct scatterlist *sg;
+        size = data->blksz * data->blocks;
+        len = data->sg_len;
 
-                pr_debug("finishing index %d\n", host->in_use_index);
+        at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX);
+        at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
 
-                sg = &data->sg[host->in_use_index++];
+        for (i = 0; i < len; i++) {
+                struct scatterlist *sg;
+                int amount;
+                unsigned int *sgbuffer;
 
-                pr_debug("Unmapping page %08X\n", sg->dma_address);
+                sg = &data->sg[i];
 
-                dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE);
+                sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
+                amount = min(size, sg->length);
+                size -= amount;
 
                 if (cpu_is_at91rm9200()) {      /* AT91RM9200 errata */
-                        unsigned int *buffer;
                         int index;
-
-                        /* Swap the contents of the buffer */
-                        buffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
-                        pr_debug("buffer = %p, length = %d\n", buffer, sg->length);
-
-                        for (index = 0; index < (sg->length / 4); index++)
-                                buffer[index] = swab32(buffer[index]);
-
-                        kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
+                        for (index = 0; index < (amount / 4); index++)
+                                sgbuffer[index] = swab32(*dmabuf++);
+                } else {
+                        char *tmpv = (char *)dmabuf;
+                        memcpy(sgbuffer, tmpv, amount);
+                        tmpv += amount;
+                        dmabuf = (unsigned *)tmpv;
                 }
 
-                flush_dcache_page(sg_page(sg));
-
-                data->bytes_xfered += sg->length;
-        }
-
-        /* Is there another transfer to trigger? */
-        if (host->transfer_index < data->sg_len)
-                at91_mci_pre_dma_read(host);
-        else {
-                at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX);
-                at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
+                flush_kernel_dcache_page(sg_page(sg));
+                kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
+                data->bytes_xfered += amount;
+                if (size == 0)
+                        break;
         }
 
         pr_debug("post dma read done\n");
@@ -461,7 +410,7 @@ static void at91_mci_enable(struct at91mci_host *host)
         at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
         mr = AT91_MCI_PDCMODE | 0x34a;
 
-        if (cpu_is_at91sam9260() || cpu_is_at91sam9263())
+        if (at91mci_is_mci1rev2xx())
                 mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;
 
         at91_mci_write(host, AT91_MCI_MR, mr);
@@ -602,10 +551,14 @@ static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command
                                 /*
                                  * Handle a read
                                  */
-                                host->buffer = NULL;
                                 host->total_length = 0;
 
-                                at91_mci_pre_dma_read(host);
+                                at91_mci_write(host, ATMEL_PDC_RPR, host->physical_address);
+                                at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ?
+                                        (blocks * block_length) : (blocks * block_length) / 4);
+                                at91_mci_write(host, ATMEL_PDC_RNPR, 0);
+                                at91_mci_write(host, ATMEL_PDC_RNCR, 0);
+
                                 ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
                         }
                         else {
@@ -614,27 +567,15 @@ static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command
                                  */
                                 host->total_length = block_length * blocks;
                                 /*
-                                 * AT91SAM926[0/3] Data Write Operation and
+                                 * MCI1 rev2xx Data Write Operation and
                                  * number of bytes erratum
                                  */
-                                if (cpu_is_at91sam9260 () || cpu_is_at91sam9263())
+                                if (at91mci_is_mci1rev2xx())
                                         if (host->total_length < 12)
                                                 host->total_length = 12;
 
-                                host->buffer = kmalloc(host->total_length, GFP_KERNEL);
-                                if (!host->buffer) {
-                                        pr_debug("Can't alloc tx buffer\n");
-                                        cmd->error = -ENOMEM;
-                                        mmc_request_done(host->mmc, host->request);
-                                        return;
-                                }
-
                                 at91_mci_sg_to_dma(host, data);
 
-                                host->physical_address = dma_map_single(NULL,
-                                                host->buffer, host->total_length,
-                                                DMA_TO_DEVICE);
-
                                 pr_debug("Transmitting %d bytes\n", host->total_length);
 
                                 at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address);
@@ -701,14 +642,6 @@ static void at91_mci_completed_command(struct at91mci_host *host, unsigned int s
         cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2));
         cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3));
 
-        if (host->buffer) {
-                dma_unmap_single(NULL,
-                                host->physical_address, host->total_length,
-                                DMA_TO_DEVICE);
-                kfree(host->buffer);
-                host->buffer = NULL;
-        }
-
         pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n",
                  status, at91_mci_read(host, AT91_MCI_SR),
                  cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
@@ -754,7 +687,8 @@ static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
         host->request = mrq;
         host->flags = 0;
 
-        mod_timer(&host->timer, jiffies +  HZ);
+        /* more than 1s timeout needed with slow SD cards */
+        mod_timer(&host->timer, jiffies +  msecs_to_jiffies(2000));
 
         at91_mci_process_next(host);
 }
@@ -942,7 +876,8 @@ static irqreturn_t at91_mmc_det_irq(int irq, void *_host)
                         pr_debug("****** Resetting SD-card bus width ******\n");
                         at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
                 }
-                mmc_detect_change(host->mmc, msecs_to_jiffies(100));
+                /* 0.5s needed because of early card detect switch firing */
+                mmc_detect_change(host->mmc, msecs_to_jiffies(500));
         }
         return IRQ_HANDLED;
 }
@@ -1006,24 +941,42 @@ static int __init at91_mci_probe(struct platform_device *pdev)
         mmc->f_min = 375000;
         mmc->f_max = 25000000;
         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-        mmc->caps = MMC_CAP_SDIO_IRQ;
+        mmc->caps = 0;
 
-        mmc->max_blk_size = 4095;
-        mmc->max_blk_count = mmc->max_req_size;
+        mmc->max_blk_size  = MCI_MAXBLKSIZE;
+        mmc->max_blk_count = MCI_BLKATONCE;
+        mmc->max_req_size  = MCI_BUFSIZE;
+        mmc->max_phys_segs = MCI_BLKATONCE;
+        mmc->max_hw_segs   = MCI_BLKATONCE;
+        mmc->max_seg_size  = MCI_BUFSIZE;
 
         host = mmc_priv(mmc);
         host->mmc = mmc;
-        host->buffer = NULL;
         host->bus_mode = 0;
         host->board = pdev->dev.platform_data;
         if (host->board->wire4) {
-                if (cpu_is_at91sam9260() || cpu_is_at91sam9263())
+                if (at91mci_is_mci1rev2xx())
                         mmc->caps |= MMC_CAP_4_BIT_DATA;
                 else
                         dev_warn(&pdev->dev, "4 wire bus mode not supported"
                                 " - using 1 wire\n");
         }
 
+        host->buffer = dma_alloc_coherent(&pdev->dev, MCI_BUFSIZE,
+                                        &host->physical_address, GFP_KERNEL);
+        if (!host->buffer) {
+                ret = -ENOMEM;
+                dev_err(&pdev->dev, "Can't allocate transmit buffer\n");
+                goto fail5;
+        }
+
+        /* Add SDIO capability when available */
+        if (at91mci_is_mci1rev2xx()) {
+                /* at91mci MCI1 rev2xx sdio interrupt erratum */
+                if (host->board->wire4 || !host->board->slot_b)
+                        mmc->caps |= MMC_CAP_SDIO_IRQ;
+        }
+
         /*
          * Reserve GPIOs ... board init code makes sure these pins are set
          * up as GPIOs with the right direction (input, except for vcc)
@@ -1032,7 +985,7 @@ static int __init at91_mci_probe(struct platform_device *pdev)
                 ret = gpio_request(host->board->det_pin, "mmc_detect");
                 if (ret < 0) {
                         dev_dbg(&pdev->dev, "couldn't claim card detect pin\n");
-                        goto fail5;
+                        goto fail4b;
                 }
         }
         if (host->board->wp_pin) {
@@ -1132,6 +1085,10 @@ fail3:
 fail4:
         if (host->board->det_pin)
                 gpio_free(host->board->det_pin);
+fail4b:
+        if (host->buffer)
+                dma_free_coherent(&pdev->dev, MCI_BUFSIZE,
+                                host->buffer, host->physical_address);
 fail5:
         mmc_free_host(mmc);
 fail6:
@@ -1154,6 +1111,10 @@ static int __exit at91_mci_remove(struct platform_device *pdev)
 
         host = mmc_priv(mmc);
 
+        if (host->buffer)
+                dma_free_coherent(&pdev->dev, MCI_BUFSIZE,
+                                host->buffer, host->physical_address);
+
         if (host->board->det_pin) {
                 if (device_can_wakeup(&pdev->dev))
                         free_irq(gpio_to_irq(host->board->det_pin), host);
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index fc25586b7ee1..fb279f4ed8b3 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -22,9 +22,12 @@
 #include <linux/platform_device.h>
 #include <linux/scatterlist.h>
 #include <linux/seq_file.h>
+#include <linux/slab.h>
 #include <linux/stat.h>
 
 #include <linux/mmc/host.h>
+
+#include <mach/atmel-mci.h>
 #include <linux/atmel-mci.h>
 
 #include <asm/io.h>
@@ -92,6 +95,7 @@ struct atmel_mci_dma {
  * @need_clock_update: Update the clock rate before the next request.
  * @need_reset: Reset controller before next request.
  * @mode_reg: Value of the MR register.
+ * @cfg_reg: Value of the CFG register.
  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
  *      rate and timeout calculations.
  * @mapbase: Physical address of the MMIO registers.
@@ -155,6 +159,7 @@ struct atmel_mci {
         bool                    need_clock_update;
         bool                    need_reset;
         u32                     mode_reg;
+        u32                     cfg_reg;
         unsigned long           bus_hz;
         unsigned long           mapbase;
         struct clk              *mck;
@@ -223,6 +228,19 @@ static bool mci_has_rwproof(void)
 }
 
 /*
+ * The new MCI2 module isn't 100% compatible with the old MCI module,
+ * and it has a few nice features which we want to use...
+ */
+static inline bool atmci_is_mci2(void)
+{
+        if (cpu_is_at91sam9g45())
+                return true;
+
+        return false;
+}
+
+
+/*
  * The debugfs stuff below is mostly optimized away when
  * CONFIG_DEBUG_FS is not set.
  */
@@ -248,7 +266,7 @@ static int atmci_req_show(struct seq_file *s, void *v)
                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
                                 cmd->opcode, cmd->arg, cmd->flags,
                                 cmd->resp[0], cmd->resp[1], cmd->resp[2],
-                                cmd->resp[2], cmd->error);
+                                cmd->resp[3], cmd->error);
                 if (data)
                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
                                 data->bytes_xfered, data->blocks,
@@ -258,7 +276,7 @@ static int atmci_req_show(struct seq_file *s, void *v)
                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
                                 stop->opcode, stop->arg, stop->flags,
                                 stop->resp[0], stop->resp[1], stop->resp[2],
-                                stop->resp[2], stop->error);
+                                stop->resp[3], stop->error);
         }
 
         spin_unlock_bh(&slot->host->lock);
@@ -357,12 +375,33 @@ static int atmci_regs_show(struct seq_file *s, void *v)
                         buf[MCI_BLKR / 4],
                         buf[MCI_BLKR / 4] & 0xffff,
                         (buf[MCI_BLKR / 4] >> 16) & 0xffff);
+        if (atmci_is_mci2())
+                seq_printf(s, "CSTOR:\t0x%08x\n", buf[MCI_CSTOR / 4]);
 
         /* Don't read RSPR and RDR; it will consume the data there */
 
         atmci_show_status_reg(s, "SR", buf[MCI_SR / 4]);
         atmci_show_status_reg(s, "IMR", buf[MCI_IMR / 4]);
 
+        if (atmci_is_mci2()) {
+                u32 val;
+
+                val = buf[MCI_DMA / 4];
+                seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
+                                val, val & 3,
+                                ((val >> 4) & 3) ?
+                                        1 << (((val >> 4) & 3) + 1) : 1,
+                                val & MCI_DMAEN ? " DMAEN" : "");
+
+                val = buf[MCI_CFG / 4];
+                seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
+                                val,
+                                val & MCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
+                                val & MCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
+                                val & MCI_CFG_HSMODE ? " HSMODE" : "",
+                                val & MCI_CFG_LSYNC ? " LSYNC" : "");
+        }
+
         kfree(buf);
 
         return 0;
@@ -530,9 +569,10 @@ static void atmci_dma_cleanup(struct atmel_mci *host)
 {
         struct mmc_data                 *data = host->data;
 
-        dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
-                     ((data->flags & MMC_DATA_WRITE)
-                      ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
+        if (data)
+                dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
+                             ((data->flags & MMC_DATA_WRITE)
+                              ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
 }
 
 static void atmci_stop_dma(struct atmel_mci *host)
@@ -557,6 +597,10 @@ static void atmci_dma_complete(void *arg)
 
         dev_vdbg(&host->pdev->dev, "DMA complete\n");
 
+        if (atmci_is_mci2())
+                /* Disable DMA hardware handshaking on MCI */
+                mci_writel(host, DMA, mci_readl(host, DMA) & ~MCI_DMAEN);
+
         atmci_dma_cleanup(host);
 
         /*
@@ -592,7 +636,7 @@ static void atmci_dma_complete(void *arg)
 }
 
 static int
-atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
+atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
 {
         struct dma_chan                 *chan;
         struct dma_async_tx_descriptor  *desc;
@@ -624,6 +668,9 @@ atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
         if (!chan)
                 return -ENODEV;
 
+        if (atmci_is_mci2())
+                mci_writel(host, DMA, MCI_DMA_CHKSIZE(3) | MCI_DMAEN);
+
         if (data->flags & MMC_DATA_READ)
                 direction = DMA_FROM_DEVICE;
         else
@@ -641,10 +688,6 @@ atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
         host->dma.data_desc = desc;
         desc->callback = atmci_dma_complete;
         desc->callback_param = host;
-        desc->tx_submit(desc);
-
-        /* Go! */
-        chan->device->device_issue_pending(chan);
 
         return 0;
 unmap_exit:
@@ -652,13 +695,26 @@ unmap_exit:
         return -ENOMEM;
 }
 
+static void atmci_submit_data(struct atmel_mci *host)
+{
+        struct dma_chan                 *chan = host->data_chan;
+        struct dma_async_tx_descriptor  *desc = host->dma.data_desc;
+
+        if (chan) {
+                desc->tx_submit(desc);
+                chan->device->device_issue_pending(chan);
+        }
+}
+
 #else /* CONFIG_MMC_ATMELMCI_DMA */
 
-static int atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
+static int atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
 {
         return -ENOSYS;
 }
 
+static void atmci_submit_data(struct atmel_mci *host) {}
+
 static void atmci_stop_dma(struct atmel_mci *host)
 {
         /* Data transfer was stopped by the interrupt handler */
@@ -672,7 +728,7 @@ static void atmci_stop_dma(struct atmel_mci *host)
  * Returns a mask of interrupt flags to be enabled after the whole
  * request has been prepared.
  */
-static u32 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
+static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
 {
         u32 iflags;
 
@@ -683,7 +739,7 @@ static u32 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
         host->data = data;
 
         iflags = ATMCI_DATA_ERROR_FLAGS;
-        if (atmci_submit_data_dma(host, data)) {
+        if (atmci_prepare_data_dma(host, data)) {
                 host->data_chan = NULL;
 
                 /*
@@ -729,6 +785,8 @@ static void atmci_start_request(struct atmel_mci *host,
                 mci_writel(host, CR, MCI_CR_SWRST);
                 mci_writel(host, CR, MCI_CR_MCIEN);
                 mci_writel(host, MR, host->mode_reg);
+                if (atmci_is_mci2())
+                        mci_writel(host, CFG, host->cfg_reg);
                 host->need_reset = false;
         }
         mci_writel(host, SDCR, slot->sdc_reg);
@@ -744,6 +802,7 @@ static void atmci_start_request(struct atmel_mci *host,
                 while (!(mci_readl(host, SR) & MCI_CMDRDY))
                         cpu_relax();
         }
+        iflags = 0;
         data = mrq->data;
         if (data) {
                 atmci_set_timeout(host, slot, data);
@@ -753,15 +812,17 @@ static void atmci_start_request(struct atmel_mci *host,
                                 | MCI_BLKLEN(data->blksz));
                 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
                         MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz));
+
+                iflags |= atmci_prepare_data(host, data);
         }
 
-        iflags = MCI_CMDRDY;
+        iflags |= MCI_CMDRDY;
         cmd = mrq->cmd;
         cmdflags = atmci_prepare_command(slot->mmc, cmd);
         atmci_start_command(host, cmd, cmdflags);
 
         if (data)
-                iflags |= atmci_submit_data(host, data);
+                atmci_submit_data(host);
 
         if (mrq->stop) {
                 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
@@ -857,6 +918,8 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
                         clk_enable(host->mck);
                         mci_writel(host, CR, MCI_CR_SWRST);
                         mci_writel(host, CR, MCI_CR_MCIEN);
+                        if (atmci_is_mci2())
+                                mci_writel(host, CFG, host->cfg_reg);
                 }
 
                 /*
@@ -1037,8 +1100,8 @@ static void atmci_command_complete(struct atmel_mci *host,
                         "command error: status=0x%08x\n", status);
 
                 if (cmd->data) {
-                        host->data = NULL;
                         atmci_stop_dma(host);
+                        host->data = NULL;
                         mci_writel(host, IDR, MCI_NOTBUSY
                                         | MCI_TXRDY | MCI_RXRDY
                                         | ATMCI_DATA_ERROR_FLAGS);
@@ -1095,6 +1158,8 @@ static void atmci_detect_change(unsigned long data)
                                 mci_writel(host, CR, MCI_CR_SWRST);
                                 mci_writel(host, CR, MCI_CR_MCIEN);
                                 mci_writel(host, MR, host->mode_reg);
+                                if (atmci_is_mci2())
+                                        mci_writel(host, CFG, host->cfg_reg);
 
                                 host->data = NULL;
                                 host->cmd = NULL;
@@ -1229,6 +1294,7 @@ static void atmci_tasklet_func(unsigned long priv)
                         } else {
                                 data->bytes_xfered = data->blocks * data->blksz;
                                 data->error = 0;
+                                mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS);
                         }
 
                         if (!data->stop) {
@@ -1584,14 +1650,47 @@ static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
 #ifdef CONFIG_MMC_ATMELMCI_DMA
 static bool filter(struct dma_chan *chan, void *slave)
 {
-        struct dw_dma_slave *dws = slave;
+        struct mci_dma_data     *sl = slave;
 
-        if (dws->dma_dev == chan->device->dev) {
-                chan->private = dws;
+        if (sl && find_slave_dev(sl) == chan->device->dev) {
+                chan->private = slave_data_ptr(sl);
                 return true;
-        } else
+        } else {
                 return false;
+        }
 }
+
+static void atmci_configure_dma(struct atmel_mci *host)
+{
+        struct mci_platform_data        *pdata;
+
+        if (host == NULL)
+                return;
+
+        pdata = host->pdev->dev.platform_data;
+
+        if (pdata && find_slave_dev(pdata->dma_slave)) {
+                dma_cap_mask_t mask;
+
+                setup_dma_addr(pdata->dma_slave,
+                               host->mapbase + MCI_TDR,
+                               host->mapbase + MCI_RDR);
+
+                /* Try to grab a DMA channel */
+                dma_cap_zero(mask);
+                dma_cap_set(DMA_SLAVE, mask);
+                host->dma.chan =
+                        dma_request_channel(mask, filter, pdata->dma_slave);
+        }
+        if (!host->dma.chan)
+                dev_notice(&host->pdev->dev, "DMA not available, using PIO\n");
+        else
+                dev_info(&host->pdev->dev,
+                                        "Using %s for DMA transfers\n",
+                                        dma_chan_name(host->dma.chan));
+}
+#else
+static void atmci_configure_dma(struct atmel_mci *host) {}
 #endif
 
 static int __init atmci_probe(struct platform_device *pdev)
@@ -1645,22 +1744,7 @@ static int __init atmci_probe(struct platform_device *pdev)
         if (ret)
                 goto err_request_irq;
 
-#ifdef CONFIG_MMC_ATMELMCI_DMA
-        if (pdata->dma_slave.dma_dev) {
-                struct dw_dma_slave *dws = &pdata->dma_slave;
-                dma_cap_mask_t mask;
-
-                dws->tx_reg = regs->start + MCI_TDR;
-                dws->rx_reg = regs->start + MCI_RDR;
-
-                /* Try to grab a DMA channel */
-                dma_cap_zero(mask);
-                dma_cap_set(DMA_SLAVE, mask);
-                host->dma.chan = dma_request_channel(mask, filter, dws);
-        }
-        if (!host->dma.chan)
-                dev_notice(&pdev->dev, "DMA not available, using PIO\n");
-#endif /* CONFIG_MMC_ATMELMCI_DMA */
+        atmci_configure_dma(host);
 
         platform_set_drvdata(pdev, host);
 
@@ -1669,13 +1753,13 @@ static int __init atmci_probe(struct platform_device *pdev)
         ret = -ENODEV;
         if (pdata->slot[0].bus_width) {
                 ret = atmci_init_slot(host, &pdata->slot[0],
-                                MCI_SDCSEL_SLOT_A, 0);
+                                0, MCI_SDCSEL_SLOT_A);
                 if (!ret)
                         nr_slots++;
         }
         if (pdata->slot[1].bus_width) {
                 ret = atmci_init_slot(host, &pdata->slot[1],
-                                MCI_SDCSEL_SLOT_B, 1);
+                                1, MCI_SDCSEL_SLOT_B);
                 if (!ret)
                         nr_slots++;
         }
diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c
index d3f55615c099..f5834449400e 100644
--- a/drivers/mmc/host/au1xmmc.c
+++ b/drivers/mmc/host/au1xmmc.c
@@ -41,6 +41,7 @@
 #include <linux/scatterlist.h>
 #include <linux/leds.h>
 #include <linux/mmc/host.h>
+#include <linux/slab.h>
 
 #include <asm/io.h>
 #include <asm/mach-au1x00/au1000.h>
@@ -650,11 +651,11 @@ static int au1xmmc_prepare_data(struct au1xmmc_host *host,
                                 flags = DDMA_FLAGS_IE;
 
                         if (host->flags & HOST_F_XMIT) {
-                                ret = au1xxx_dbdma_put_source_flags(channel,
-                                        (void *)sg_virt(sg), len, flags);
+                                ret = au1xxx_dbdma_put_source(channel,
+                                        sg_phys(sg), len, flags);
                         } else {
-                                ret = au1xxx_dbdma_put_dest_flags(channel,
-                                        (void *)sg_virt(sg), len, flags);
+                                ret = au1xxx_dbdma_put_dest(channel,
+                                        sg_phys(sg), len, flags);
                         }
 
                         if (!ret)
@@ -1017,6 +1018,10 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev)
         } else
                 mmc->caps |= MMC_CAP_NEEDS_POLL;
 
+        /* platform may not be able to use all advertised caps */
+        if (host->platdata)
+                mmc->caps &= ~(host->platdata->mask_host_caps);
+
         tasklet_init(&host->data_task, au1xmmc_tasklet_data,
                         (unsigned long)host);
 
diff --git a/drivers/mmc/host/bfin_sdh.c b/drivers/mmc/host/bfin_sdh.c
new file mode 100644
index 000000000000..6919e844072c
--- /dev/null
+++ b/drivers/mmc/host/bfin_sdh.c
@@ -0,0 +1,644 @@
+/*
+ * bfin_sdh.c - Analog Devices Blackfin SDH Controller
+ *
+ * Copyright (C) 2007-2009 Analog Device Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#define DRIVER_NAME     "bfin-sdh"
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/mmc/host.h>
+#include <linux/proc_fs.h>
+#include <linux/gfp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+#include <asm/bfin_sdh.h>
+
+#if defined(CONFIG_BF51x)
+#define bfin_read_SDH_PWR_CTL           bfin_read_RSI_PWR_CTL
+#define bfin_write_SDH_PWR_CTL          bfin_write_RSI_PWR_CTL
+#define bfin_read_SDH_CLK_CTL           bfin_read_RSI_CLK_CTL
+#define bfin_write_SDH_CLK_CTL          bfin_write_RSI_CLK_CTL
+#define bfin_write_SDH_ARGUMENT         bfin_write_RSI_ARGUMENT
+#define bfin_write_SDH_COMMAND          bfin_write_RSI_COMMAND
+#define bfin_write_SDH_DATA_TIMER       bfin_write_RSI_DATA_TIMER
+#define bfin_read_SDH_RESPONSE0         bfin_read_RSI_RESPONSE0
+#define bfin_read_SDH_RESPONSE1         bfin_read_RSI_RESPONSE1
+#define bfin_read_SDH_RESPONSE2         bfin_read_RSI_RESPONSE2
+#define bfin_read_SDH_RESPONSE3         bfin_read_RSI_RESPONSE3
+#define bfin_write_SDH_DATA_LGTH        bfin_write_RSI_DATA_LGTH
+#define bfin_read_SDH_DATA_CTL          bfin_read_RSI_DATA_CTL
+#define bfin_write_SDH_DATA_CTL         bfin_write_RSI_DATA_CTL
+#define bfin_read_SDH_DATA_CNT          bfin_read_RSI_DATA_CNT
+#define bfin_write_SDH_STATUS_CLR       bfin_write_RSI_STATUS_CLR
+#define bfin_read_SDH_E_STATUS          bfin_read_RSI_E_STATUS
+#define bfin_write_SDH_E_STATUS         bfin_write_RSI_E_STATUS
+#define bfin_read_SDH_STATUS            bfin_read_RSI_STATUS
+#define bfin_write_SDH_MASK0            bfin_write_RSI_MASK0
+#define bfin_read_SDH_CFG               bfin_read_RSI_CFG
+#define bfin_write_SDH_CFG              bfin_write_RSI_CFG
+#endif
+
+struct dma_desc_array {
+        unsigned long   start_addr;
+        unsigned short  cfg;
+        unsigned short  x_count;
+        short           x_modify;
+} __packed;
+
+struct sdh_host {
+        struct mmc_host         *mmc;
+        spinlock_t              lock;
+        struct resource         *res;
+        void __iomem            *base;
+        int                     irq;
+        int                     stat_irq;
+        int                     dma_ch;
+        int                     dma_dir;
+        struct dma_desc_array   *sg_cpu;
+        dma_addr_t              sg_dma;
+        int                     dma_len;
+
+        unsigned int            imask;
+        unsigned int            power_mode;
+        unsigned int            clk_div;
+
+        struct mmc_request      *mrq;
+        struct mmc_command      *cmd;
+        struct mmc_data         *data;
+};
+
+static struct bfin_sd_host *get_sdh_data(struct platform_device *pdev)
+{
+        return pdev->dev.platform_data;
+}
+
+static void sdh_stop_clock(struct sdh_host *host)
+{
+        bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() & ~CLK_E);
+        SSYNC();
+}
+
+static void sdh_enable_stat_irq(struct sdh_host *host, unsigned int mask)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&host->lock, flags);
+        host->imask |= mask;
+        bfin_write_SDH_MASK0(mask);
+        SSYNC();
+        spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static void sdh_disable_stat_irq(struct sdh_host *host, unsigned int mask)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&host->lock, flags);
+        host->imask &= ~mask;
+        bfin_write_SDH_MASK0(host->imask);
+        SSYNC();
+        spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
+{
+        unsigned int length;
+        unsigned int data_ctl;
+        unsigned int dma_cfg;
+        unsigned int cycle_ns, timeout;
+
+        dev_dbg(mmc_dev(host->mmc), "%s enter flags: 0x%x\n", __func__, data->flags);
+        host->data = data;
+        data_ctl = 0;
+        dma_cfg = 0;
+
+        length = data->blksz * data->blocks;
+        bfin_write_SDH_DATA_LGTH(length);
+
+        if (data->flags & MMC_DATA_STREAM)
+                data_ctl |= DTX_MODE;
+
+        if (data->flags & MMC_DATA_READ)
+                data_ctl |= DTX_DIR;
+        /* Only supports power-of-2 block size */
+        if (data->blksz & (data->blksz - 1))
+                return -EINVAL;
+        data_ctl |= ((ffs(data->blksz) - 1) << 4);
+
+        bfin_write_SDH_DATA_CTL(data_ctl);
+        /* the time of a host clock period in ns */
+        cycle_ns = 1000000000 / (get_sclk() / (2 * (host->clk_div + 1)));
+        timeout = data->timeout_ns / cycle_ns;
+        timeout += data->timeout_clks;
+        bfin_write_SDH_DATA_TIMER(timeout);
+        SSYNC();
+
+        if (data->flags & MMC_DATA_READ) {
+                host->dma_dir = DMA_FROM_DEVICE;
+                dma_cfg |= WNR;
+        } else
+                host->dma_dir = DMA_TO_DEVICE;
+
+        sdh_enable_stat_irq(host, (DAT_CRC_FAIL | DAT_TIME_OUT | DAT_END));
+        host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma_dir);
+#if defined(CONFIG_BF54x)
+        dma_cfg |= DMAFLOW_ARRAY | NDSIZE_5 | RESTART | WDSIZE_32 | DMAEN;
+        {
+                struct scatterlist *sg;
+                int i;
+                for_each_sg(data->sg, sg, host->dma_len, i) {
+                        host->sg_cpu[i].start_addr = sg_dma_address(sg);
+                        host->sg_cpu[i].cfg = dma_cfg;
+                        host->sg_cpu[i].x_count = sg_dma_len(sg) / 4;
+                        host->sg_cpu[i].x_modify = 4;
+                        dev_dbg(mmc_dev(host->mmc), "%d: start_addr:0x%lx, "
+                                "cfg:0x%x, x_count:0x%x, x_modify:0x%x\n",
+                                i, host->sg_cpu[i].start_addr,
+                                host->sg_cpu[i].cfg, host->sg_cpu[i].x_count,
+                                host->sg_cpu[i].x_modify);
+                }
+        }
+        flush_dcache_range((unsigned int)host->sg_cpu,
+                (unsigned int)host->sg_cpu +
+                        host->dma_len * sizeof(struct dma_desc_array));
+        /* Set the last descriptor to stop mode */
+        host->sg_cpu[host->dma_len - 1].cfg &= ~(DMAFLOW | NDSIZE);
+        host->sg_cpu[host->dma_len - 1].cfg |= DI_EN;
+
+        set_dma_curr_desc_addr(host->dma_ch, (unsigned long *)host->sg_dma);
+        set_dma_x_count(host->dma_ch, 0);
+        set_dma_x_modify(host->dma_ch, 0);
+        set_dma_config(host->dma_ch, dma_cfg);
+#elif defined(CONFIG_BF51x)
+        /* RSI DMA doesn't work in array mode */
+        dma_cfg |= WDSIZE_32 | DMAEN;
+        set_dma_start_addr(host->dma_ch, sg_dma_address(&data->sg[0]));
+        set_dma_x_count(host->dma_ch, length / 4);
+        set_dma_x_modify(host->dma_ch, 4);
+        set_dma_config(host->dma_ch, dma_cfg);
+#endif
+        bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
+
+        SSYNC();
+
+        dev_dbg(mmc_dev(host->mmc), "%s exit\n", __func__);
+        return 0;
+}
+
+static void sdh_start_cmd(struct sdh_host *host, struct mmc_command *cmd)
+{
+        unsigned int sdh_cmd;
+        unsigned int stat_mask;
+
+        dev_dbg(mmc_dev(host->mmc), "%s enter cmd: 0x%p\n", __func__, cmd);
+        WARN_ON(host->cmd != NULL);
+        host->cmd = cmd;
+
+        sdh_cmd = 0;
+        stat_mask = 0;
+
+        sdh_cmd |= cmd->opcode;
+
+        if (cmd->flags & MMC_RSP_PRESENT) {
+                sdh_cmd |= CMD_RSP;
+                stat_mask |= CMD_RESP_END;
+        } else {
+                stat_mask |= CMD_SENT;
+        }
+
+        if (cmd->flags & MMC_RSP_136)
+                sdh_cmd |= CMD_L_RSP;
+
+        stat_mask |= CMD_CRC_FAIL | CMD_TIME_OUT;
+
+        sdh_enable_stat_irq(host, stat_mask);
+
+        bfin_write_SDH_ARGUMENT(cmd->arg);
+        bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
+        bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() | CLK_E);
+        SSYNC();
+}
+
+static void sdh_finish_request(struct sdh_host *host, struct mmc_request *mrq)
+{
+        dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
+        host->mrq = NULL;
+        host->cmd = NULL;
+        host->data = NULL;
+        mmc_request_done(host->mmc, mrq);
+}
+
+static int sdh_cmd_done(struct sdh_host *host, unsigned int stat)
+{
+        struct mmc_command *cmd = host->cmd;
+        int ret = 0;
+
+        dev_dbg(mmc_dev(host->mmc), "%s enter cmd: %p\n", __func__, cmd);
+        if (!cmd)
+                return 0;
+
+        host->cmd = NULL;
+
+        if (cmd->flags & MMC_RSP_PRESENT) {
+                cmd->resp[0] = bfin_read_SDH_RESPONSE0();
+                if (cmd->flags & MMC_RSP_136) {
+                        cmd->resp[1] = bfin_read_SDH_RESPONSE1();
+                        cmd->resp[2] = bfin_read_SDH_RESPONSE2();
+                        cmd->resp[3] = bfin_read_SDH_RESPONSE3();
+                }
+        }
+        if (stat & CMD_TIME_OUT)
+                cmd->error = -ETIMEDOUT;
+        else if (stat & CMD_CRC_FAIL && cmd->flags & MMC_RSP_CRC)
+                cmd->error = -EILSEQ;
+
+        sdh_disable_stat_irq(host, (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL));
+
+        if (host->data && !cmd->error) {
+                if (host->data->flags & MMC_DATA_WRITE) {
+                        ret = sdh_setup_data(host, host->data);
+                        if (ret)
+                                return 0;
+                }
+
+                sdh_enable_stat_irq(host, DAT_END | RX_OVERRUN | TX_UNDERRUN | DAT_TIME_OUT);
+        } else
+                sdh_finish_request(host, host->mrq);
+
+        return 1;
+}
+
+static int sdh_data_done(struct sdh_host *host, unsigned int stat)
+{
+        struct mmc_data *data = host->data;
+
+        dev_dbg(mmc_dev(host->mmc), "%s enter stat: 0x%x\n", __func__, stat);
+        if (!data)
+                return 0;
+
+        disable_dma(host->dma_ch);
+        dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
+                     host->dma_dir);
+
+        if (stat & DAT_TIME_OUT)
+                data->error = -ETIMEDOUT;
+        else if (stat & DAT_CRC_FAIL)
+                data->error = -EILSEQ;
+        else if (stat & (RX_OVERRUN | TX_UNDERRUN))
+                data->error = -EIO;
+
+        if (!data->error)
+                data->bytes_xfered = data->blocks * data->blksz;
+        else
+                data->bytes_xfered = 0;
+
+        sdh_disable_stat_irq(host, DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN);
+        bfin_write_SDH_STATUS_CLR(DAT_END_STAT | DAT_TIMEOUT_STAT | \
+                        DAT_CRC_FAIL_STAT | DAT_BLK_END_STAT | RX_OVERRUN | TX_UNDERRUN);
+        bfin_write_SDH_DATA_CTL(0);
+        SSYNC();
+
+        host->data = NULL;
+        if (host->mrq->stop) {
+                sdh_stop_clock(host);
+                sdh_start_cmd(host, host->mrq->stop);
+        } else {
+                sdh_finish_request(host, host->mrq);
+        }
+
+        return 1;
+}
+
+static void sdh_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+        struct sdh_host *host = mmc_priv(mmc);
+        int ret = 0;
+
+        dev_dbg(mmc_dev(host->mmc), "%s enter, mrp:%p, cmd:%p\n", __func__, mrq, mrq->cmd);
+        WARN_ON(host->mrq != NULL);
+
+        host->mrq = mrq;
+        host->data = mrq->data;
+
+        if (mrq->data && mrq->data->flags & MMC_DATA_READ) {
+                ret = sdh_setup_data(host, mrq->data);
+                if (ret)
+                        return;
+        }
+
+        sdh_start_cmd(host, mrq->cmd);
+}
+
+static void sdh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+        struct sdh_host *host;
+        unsigned long flags;
+        u16 clk_ctl = 0;
+        u16 pwr_ctl = 0;
+        u16 cfg;
+        host = mmc_priv(mmc);
+
+        spin_lock_irqsave(&host->lock, flags);
+        if (ios->clock) {
+                unsigned long  sys_clk, ios_clk;
+                unsigned char clk_div;
+                ios_clk = 2 * ios->clock;
+                sys_clk = get_sclk();
+                clk_div = sys_clk / ios_clk;
+                if (sys_clk % ios_clk == 0)
+                        clk_div -= 1;
+                clk_div = min_t(unsigned char, clk_div, 0xFF);
+                clk_ctl |= clk_div;
+                clk_ctl |= CLK_E;
+                host->clk_div = clk_div;
+        } else
+                sdh_stop_clock(host);
+
+        if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
+#ifdef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
+                pwr_ctl |= ROD_CTL;
+#else
+                pwr_ctl |= SD_CMD_OD | ROD_CTL;
+#endif
+
+        if (ios->bus_width == MMC_BUS_WIDTH_4) {
+                cfg = bfin_read_SDH_CFG();
+                cfg &= ~PD_SDDAT3;
+                cfg |= PUP_SDDAT3;
+                /* Enable 4 bit SDIO */
+                cfg |= (SD4E | MWE);
+                bfin_write_SDH_CFG(cfg);
+                clk_ctl |= WIDE_BUS;
+        } else {
+                cfg = bfin_read_SDH_CFG();
+                cfg |= MWE;
+                bfin_write_SDH_CFG(cfg);
+        }
+
+        bfin_write_SDH_CLK_CTL(clk_ctl);
+
+        host->power_mode = ios->power_mode;
+        if (ios->power_mode == MMC_POWER_ON)
+                pwr_ctl |= PWR_ON;
+
+        bfin_write_SDH_PWR_CTL(pwr_ctl);
+        SSYNC();
+
+        spin_unlock_irqrestore(&host->lock, flags);
+
+        dev_dbg(mmc_dev(host->mmc), "SDH: clk_div = 0x%x actual clock:%ld expected clock:%d\n",
+                host->clk_div,
+                host->clk_div ? get_sclk() / (2 * (host->clk_div + 1)) : 0,
+                ios->clock);
+}
+
+static const struct mmc_host_ops sdh_ops = {
+        .request        = sdh_request,
+        .set_ios        = sdh_set_ios,
+};
+
+static irqreturn_t sdh_dma_irq(int irq, void *devid)
+{
+        struct sdh_host *host = devid;
+
+        dev_dbg(mmc_dev(host->mmc), "%s enter, irq_stat: 0x%04x\n", __func__,
+                get_dma_curr_irqstat(host->dma_ch));
+        clear_dma_irqstat(host->dma_ch);
+        SSYNC();
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t sdh_stat_irq(int irq, void *devid)
+{
+        struct sdh_host *host = devid;
+        unsigned int status;
+        int handled = 0;
+
+        dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
+        status = bfin_read_SDH_E_STATUS();
+        if (status & SD_CARD_DET) {
+                mmc_detect_change(host->mmc, 0);
+                bfin_write_SDH_E_STATUS(SD_CARD_DET);
+        }
+        status = bfin_read_SDH_STATUS();
+        if (status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL)) {
+                handled |= sdh_cmd_done(host, status);
+                bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | \
+                                CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
+                SSYNC();
+        }
+
+        status = bfin_read_SDH_STATUS();
+        if (status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN))
+                handled |= sdh_data_done(host, status);
+
+        dev_dbg(mmc_dev(host->mmc), "%s exit\n\n", __func__);
+
+        return IRQ_RETVAL(handled);
+}
+
+static int __devinit sdh_probe(struct platform_device *pdev)
+{
+        struct mmc_host *mmc;
+        struct sdh_host *host;
+        struct bfin_sd_host *drv_data = get_sdh_data(pdev);
+        int ret;
+
+        if (!drv_data) {
+                dev_err(&pdev->dev, "missing platform driver data\n");
+                ret = -EINVAL;
+                goto out;
+        }
+
+        mmc = mmc_alloc_host(sizeof(*mmc), &pdev->dev);
+        if (!mmc) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        mmc->ops = &sdh_ops;
+        mmc->max_phys_segs = 32;
+        mmc->max_seg_size = 1 << 16;
+        mmc->max_blk_size = 1 << 11;
+        mmc->max_blk_count = 1 << 11;
+        mmc->max_req_size = PAGE_SIZE;
+        mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+        mmc->f_max = get_sclk();
+        mmc->f_min = mmc->f_max >> 9;
+        mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NEEDS_POLL;
+        host = mmc_priv(mmc);
+        host->mmc = mmc;
+
+        spin_lock_init(&host->lock);
+        host->irq = drv_data->irq_int0;
+        host->dma_ch = drv_data->dma_chan;
+
+        ret = request_dma(host->dma_ch, DRIVER_NAME "DMA");
+        if (ret) {
+                dev_err(&pdev->dev, "unable to request DMA channel\n");
+                goto out1;
+        }
+
+        ret = set_dma_callback(host->dma_ch, sdh_dma_irq, host);
+        if (ret) {
+                dev_err(&pdev->dev, "unable to request DMA irq\n");
+                goto out2;
+        }
+
+        host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
+        if (host->sg_cpu == NULL) {
+                ret = -ENOMEM;
+                goto out2;
+        }
+
+        platform_set_drvdata(pdev, mmc);
+        mmc_add_host(mmc);
+
+        ret = request_irq(host->irq, sdh_stat_irq, 0, "SDH Status IRQ", host);
+        if (ret) {
+                dev_err(&pdev->dev, "unable to request status irq\n");
+                goto out3;
+        }
+
+        ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
+        if (ret) {
+                dev_err(&pdev->dev, "unable to request peripheral pins\n");
+                goto out4;
+        }
+#if defined(CONFIG_BF54x)
+        /* Secure Digital Host shares DMA with Nand controller */
+        bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
+#endif
+
+        bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
+        SSYNC();
+
+        /* Disable card inserting detection pin. set MMC_CAP_NEES_POLL, and
+         * mmc stack will do the detection.
+         */
+        bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
+        SSYNC();
+
+        return 0;
+
+out4:
+        free_irq(host->irq, host);
+out3:
+        mmc_remove_host(mmc);
+        dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+out2:
+        free_dma(host->dma_ch);
+out1:
+        mmc_free_host(mmc);
+ out:
+        return ret;
+}
+
+static int __devexit sdh_remove(struct platform_device *pdev)
+{
+        struct mmc_host *mmc = platform_get_drvdata(pdev);
+
+        platform_set_drvdata(pdev, NULL);
+
+        if (mmc) {
+                struct sdh_host *host = mmc_priv(mmc);
+
+                mmc_remove_host(mmc);
+
+                sdh_stop_clock(host);
+                free_irq(host->irq, host);
+                free_dma(host->dma_ch);
+                dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+
+                mmc_free_host(mmc);
+        }
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int sdh_suspend(struct platform_device *dev, pm_message_t state)
+{
+        struct mmc_host *mmc = platform_get_drvdata(dev);
+        struct bfin_sd_host *drv_data = get_sdh_data(dev);
+        int ret = 0;
+
+        if (mmc)
+                ret = mmc_suspend_host(mmc, state);
+
+        bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() & ~PWR_ON);
+        peripheral_free_list(drv_data->pin_req);
+
+        return ret;
+}
+
+static int sdh_resume(struct platform_device *dev)
+{
+        struct mmc_host *mmc = platform_get_drvdata(dev);
+        struct bfin_sd_host *drv_data = get_sdh_data(dev);
+        int ret = 0;
+
+        ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
+        if (ret) {
+                dev_err(&dev->dev, "unable to request peripheral pins\n");
+                return ret;
+        }
+
+        bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() | PWR_ON);
+#if defined(CONFIG_BF54x)
+        /* Secure Digital Host shares DMA with Nand controller */
+        bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
+#endif
+        bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
+        SSYNC();
+
+        bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
+        SSYNC();
+
+        if (mmc)
+                ret = mmc_resume_host(mmc);
+
+        return ret;
+}
+#else
+# define sdh_suspend NULL
+# define sdh_resume  NULL
+#endif
+
+static struct platform_driver sdh_driver = {
+        .probe   = sdh_probe,
+        .remove  = __devexit_p(sdh_remove),
+        .suspend = sdh_suspend,
+        .resume  = sdh_resume,
+        .driver  = {
+                .name = DRIVER_NAME,
+        },
+};
+
+static int __init sdh_init(void)
+{
+        return platform_driver_register(&sdh_driver);
+}
+module_init(sdh_init);
+
+static void __exit sdh_exit(void)
+{
+        platform_driver_unregister(&sdh_driver);
+}
+module_exit(sdh_exit);
+
+MODULE_DESCRIPTION("Blackfin Secure Digital Host Driver");
+MODULE_AUTHOR("Cliff Cai, Roy Huang");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/cb710-mmc.c b/drivers/mmc/host/cb710-mmc.c
index 4e72964a7b43..92a324f7417c 100644
--- a/drivers/mmc/host/cb710-mmc.c
+++ b/drivers/mmc/host/cb710-mmc.c
@@ -9,7 +9,6 @@
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/slab.h>
 #include <linux/pci.h>
 #include <linux/delay.h>
 #include "cb710-mmc.h"
diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
new file mode 100644
index 000000000000..3bd0ba294e9d
--- /dev/null
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -0,0 +1,1374 @@
+/*
+ * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver
+ *
+ * Copyright (C) 2006 Texas Instruments.
+ *       Original author: Purushotam Kumar
+ * Copyright (C) 2009 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/cpufreq.h>
+#include <linux/mmc/host.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/mmc/mmc.h>
+
+#include <mach/mmc.h>
+#include <mach/edma.h>
+
+/*
+ * Register Definitions
+ */
+#define DAVINCI_MMCCTL       0x00 /* Control Register                  */
+#define DAVINCI_MMCCLK       0x04 /* Memory Clock Control Register     */
+#define DAVINCI_MMCST0       0x08 /* Status Register 0                 */
+#define DAVINCI_MMCST1       0x0C /* Status Register 1                 */
+#define DAVINCI_MMCIM        0x10 /* Interrupt Mask Register           */
+#define DAVINCI_MMCTOR       0x14 /* Response Time-Out Register        */
+#define DAVINCI_MMCTOD       0x18 /* Data Read Time-Out Register       */
+#define DAVINCI_MMCBLEN      0x1C /* Block Length Register             */
+#define DAVINCI_MMCNBLK      0x20 /* Number of Blocks Register         */
+#define DAVINCI_MMCNBLC      0x24 /* Number of Blocks Counter Register */
+#define DAVINCI_MMCDRR       0x28 /* Data Receive Register             */
+#define DAVINCI_MMCDXR       0x2C /* Data Transmit Register            */
+#define DAVINCI_MMCCMD       0x30 /* Command Register                  */
+#define DAVINCI_MMCARGHL     0x34 /* Argument Register                 */
+#define DAVINCI_MMCRSP01     0x38 /* Response Register 0 and 1         */
+#define DAVINCI_MMCRSP23     0x3C /* Response Register 0 and 1         */
+#define DAVINCI_MMCRSP45     0x40 /* Response Register 0 and 1         */
+#define DAVINCI_MMCRSP67     0x44 /* Response Register 0 and 1         */
+#define DAVINCI_MMCDRSP      0x48 /* Data Response Register            */
+#define DAVINCI_MMCETOK      0x4C
+#define DAVINCI_MMCCIDX      0x50 /* Command Index Register            */
+#define DAVINCI_MMCCKC       0x54
+#define DAVINCI_MMCTORC      0x58
+#define DAVINCI_MMCTODC      0x5C
+#define DAVINCI_MMCBLNC      0x60
+#define DAVINCI_SDIOCTL      0x64
+#define DAVINCI_SDIOST0      0x68
+#define DAVINCI_SDIOEN       0x6C
+#define DAVINCI_SDIOST       0x70
+#define DAVINCI_MMCFIFOCTL   0x74 /* FIFO Control Register             */
+
+/* DAVINCI_MMCCTL definitions */
+#define MMCCTL_DATRST         (1 << 0)
+#define MMCCTL_CMDRST         (1 << 1)
+#define MMCCTL_WIDTH_8_BIT    (1 << 8)
+#define MMCCTL_WIDTH_4_BIT    (1 << 2)
+#define MMCCTL_DATEG_DISABLED (0 << 6)
+#define MMCCTL_DATEG_RISING   (1 << 6)
+#define MMCCTL_DATEG_FALLING  (2 << 6)
+#define MMCCTL_DATEG_BOTH     (3 << 6)
+#define MMCCTL_PERMDR_LE      (0 << 9)
+#define MMCCTL_PERMDR_BE      (1 << 9)
+#define MMCCTL_PERMDX_LE      (0 << 10)
+#define MMCCTL_PERMDX_BE      (1 << 10)
+
+/* DAVINCI_MMCCLK definitions */
+#define MMCCLK_CLKEN          (1 << 8)
+#define MMCCLK_CLKRT_MASK     (0xFF << 0)
+
+/* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
+#define MMCST0_DATDNE         BIT(0)    /* data done */
+#define MMCST0_BSYDNE         BIT(1)    /* busy done */
+#define MMCST0_RSPDNE         BIT(2)    /* command done */
+#define MMCST0_TOUTRD         BIT(3)    /* data read timeout */
+#define MMCST0_TOUTRS         BIT(4)    /* command response timeout */
+#define MMCST0_CRCWR          BIT(5)    /* data write CRC error */
+#define MMCST0_CRCRD          BIT(6)    /* data read CRC error */
+#define MMCST0_CRCRS          BIT(7)    /* command response CRC error */
+#define MMCST0_DXRDY          BIT(9)    /* data transmit ready (fifo empty) */
+#define MMCST0_DRRDY          BIT(10)   /* data receive ready (data in fifo)*/
+#define MMCST0_DATED          BIT(11)   /* DAT3 edge detect */
+#define MMCST0_TRNDNE         BIT(12)   /* transfer done */
+
+/* DAVINCI_MMCST1 definitions */
+#define MMCST1_BUSY           (1 << 0)
+
+/* DAVINCI_MMCCMD definitions */
+#define MMCCMD_CMD_MASK       (0x3F << 0)
+#define MMCCMD_PPLEN          (1 << 7)
+#define MMCCMD_BSYEXP         (1 << 8)
+#define MMCCMD_RSPFMT_MASK    (3 << 9)
+#define MMCCMD_RSPFMT_NONE    (0 << 9)
+#define MMCCMD_RSPFMT_R1456   (1 << 9)
+#define MMCCMD_RSPFMT_R2      (2 << 9)
+#define MMCCMD_RSPFMT_R3      (3 << 9)
+#define MMCCMD_DTRW           (1 << 11)
+#define MMCCMD_STRMTP         (1 << 12)
+#define MMCCMD_WDATX          (1 << 13)
+#define MMCCMD_INITCK         (1 << 14)
+#define MMCCMD_DCLR           (1 << 15)
+#define MMCCMD_DMATRIG        (1 << 16)
+
+/* DAVINCI_MMCFIFOCTL definitions */
+#define MMCFIFOCTL_FIFORST    (1 << 0)
+#define MMCFIFOCTL_FIFODIR_WR (1 << 1)
+#define MMCFIFOCTL_FIFODIR_RD (0 << 1)
+#define MMCFIFOCTL_FIFOLEV    (1 << 2) /* 0 = 128 bits, 1 = 256 bits */
+#define MMCFIFOCTL_ACCWD_4    (0 << 3) /* access width of 4 bytes    */
+#define MMCFIFOCTL_ACCWD_3    (1 << 3) /* access width of 3 bytes    */
+#define MMCFIFOCTL_ACCWD_2    (2 << 3) /* access width of 2 bytes    */
+#define MMCFIFOCTL_ACCWD_1    (3 << 3) /* access width of 1 byte     */
+
+
+/* MMCSD Init clock in Hz in opendrain mode */
+#define MMCSD_INIT_CLOCK                200000
+
+/*
+ * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units,
+ * and we handle up to NR_SG segments.  MMC_BLOCK_BOUNCE kicks in only
+ * for drivers with max_hw_segs == 1, making the segments bigger (64KB)
+ * than the page or two that's otherwise typical.  NR_SG == 16 gives at
+ * least the same throughput boost, using EDMA transfer linkage instead
+ * of spending CPU time copying pages.
+ */
+#define MAX_CCNT        ((1 << 16) - 1)
+
+#define NR_SG           16
+
+static unsigned rw_threshold = 32;
+module_param(rw_threshold, uint, S_IRUGO);
+MODULE_PARM_DESC(rw_threshold,
+                "Read/Write threshold. Default = 32");
+
+static unsigned __initdata use_dma = 1;
+module_param(use_dma, uint, 0);
+MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1");
+
+struct mmc_davinci_host {
+        struct mmc_command *cmd;
+        struct mmc_data *data;
+        struct mmc_host *mmc;
+        struct clk *clk;
+        unsigned int mmc_input_clk;
+        void __iomem *base;
+        struct resource *mem_res;
+        int irq;
+        unsigned char bus_mode;
+
+#define DAVINCI_MMC_DATADIR_NONE        0
+#define DAVINCI_MMC_DATADIR_READ        1
+#define DAVINCI_MMC_DATADIR_WRITE       2
+        unsigned char data_dir;
+
+        /* buffer is used during PIO of one scatterlist segment, and
+         * is updated along with buffer_bytes_left.  bytes_left applies
+         * to all N blocks of the PIO transfer.
+         */
+        u8 *buffer;
+        u32 buffer_bytes_left;
+        u32 bytes_left;
+
+        u32 rxdma, txdma;
+        bool use_dma;
+        bool do_dma;
+
+        /* Scatterlist DMA uses one or more parameter RAM entries:
+         * the main one (associated with rxdma or txdma) plus zero or
+         * more links.  The entries for a given transfer differ only
+         * by memory buffer (address, length) and link field.
+         */
+        struct edmacc_param     tx_template;
+        struct edmacc_param     rx_template;
+        unsigned                n_link;
+        u32                     links[NR_SG - 1];
+
+        /* For PIO we walk scatterlists one segment at a time. */
+        unsigned int            sg_len;
+        struct scatterlist *sg;
+
+        /* Version of the MMC/SD controller */
+        u8 version;
+        /* for ns in one cycle calculation */
+        unsigned ns_in_one_cycle;
+#ifdef CONFIG_CPU_FREQ
+        struct notifier_block   freq_transition;
+#endif
+};
+
+
+/* PIO only */
+static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host)
+{
+        host->buffer_bytes_left = sg_dma_len(host->sg);
+        host->buffer = sg_virt(host->sg);
+        if (host->buffer_bytes_left > host->bytes_left)
+                host->buffer_bytes_left = host->bytes_left;
+}
+
+static void davinci_fifo_data_trans(struct mmc_davinci_host *host,
+                                        unsigned int n)
+{
+        u8 *p;
+        unsigned int i;
+
+        if (host->buffer_bytes_left == 0) {
+                host->sg = sg_next(host->data->sg);
+                mmc_davinci_sg_to_buf(host);
+        }
+
+        p = host->buffer;
+        if (n > host->buffer_bytes_left)
+                n = host->buffer_bytes_left;
+        host->buffer_bytes_left -= n;
+        host->bytes_left -= n;
+
+        /* NOTE:  we never transfer more than rw_threshold bytes
+         * to/from the fifo here; there's no I/O overlap.
+         * This also assumes that access width( i.e. ACCWD) is 4 bytes
+         */
+        if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
+                for (i = 0; i < (n >> 2); i++) {
+                        writel(*((u32 *)p), host->base + DAVINCI_MMCDXR);
+                        p = p + 4;
+                }
+                if (n & 3) {
+                        iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3));
+                        p = p + (n & 3);
+                }
+        } else {
+                for (i = 0; i < (n >> 2); i++) {
+                        *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR);
+                        p  = p + 4;
+                }
+                if (n & 3) {
+                        ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3));
+                        p = p + (n & 3);
+                }
+        }
+        host->buffer = p;
+}
+
+static void mmc_davinci_start_command(struct mmc_davinci_host *host,
+                struct mmc_command *cmd)
+{
+        u32 cmd_reg = 0;
+        u32 im_val;
+
+        dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n",
+                cmd->opcode, cmd->arg,
+                ({ char *s;
+                switch (mmc_resp_type(cmd)) {
+                case MMC_RSP_R1:
+                        s = ", R1/R5/R6/R7 response";
+                        break;
+                case MMC_RSP_R1B:
+                        s = ", R1b response";
+                        break;
+                case MMC_RSP_R2:
+                        s = ", R2 response";
+                        break;
+                case MMC_RSP_R3:
+                        s = ", R3/R4 response";
+                        break;
+                default:
+                        s = ", (R? response)";
+                        break;
+                }; s; }));
+        host->cmd = cmd;
+
+        switch (mmc_resp_type(cmd)) {
+        case MMC_RSP_R1B:
+                /* There's some spec confusion about when R1B is
+                 * allowed, but if the card doesn't issue a BUSY
+                 * then it's harmless for us to allow it.
+                 */
+                cmd_reg |= MMCCMD_BSYEXP;
+                /* FALLTHROUGH */
+        case MMC_RSP_R1:                /* 48 bits, CRC */
+                cmd_reg |= MMCCMD_RSPFMT_R1456;
+                break;
+        case MMC_RSP_R2:                /* 136 bits, CRC */
+                cmd_reg |= MMCCMD_RSPFMT_R2;
+                break;
+        case MMC_RSP_R3:                /* 48 bits, no CRC */
+                cmd_reg |= MMCCMD_RSPFMT_R3;
+                break;
+        default:
+                cmd_reg |= MMCCMD_RSPFMT_NONE;
+                dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n",
+                        mmc_resp_type(cmd));
+                break;
+        }
+
+        /* Set command index */
+        cmd_reg |= cmd->opcode;
+
+        /* Enable EDMA transfer triggers */
+        if (host->do_dma)
+                cmd_reg |= MMCCMD_DMATRIG;
+
+        if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL &&
+                        host->data_dir == DAVINCI_MMC_DATADIR_READ)
+                cmd_reg |= MMCCMD_DMATRIG;
+
+        /* Setting whether command involves data transfer or not */
+        if (cmd->data)
+                cmd_reg |= MMCCMD_WDATX;
+
+        /* Setting whether stream or block transfer */
+        if (cmd->flags & MMC_DATA_STREAM)
+                cmd_reg |= MMCCMD_STRMTP;
+
+        /* Setting whether data read or write */
+        if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
+                cmd_reg |= MMCCMD_DTRW;
+
+        if (host->bus_mode == MMC_BUSMODE_PUSHPULL)
+                cmd_reg |= MMCCMD_PPLEN;
+
+        /* set Command timeout */
+        writel(0x1FFF, host->base + DAVINCI_MMCTOR);
+
+        /* Enable interrupt (calculate here, defer until FIFO is stuffed). */
+        im_val =  MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS;
+        if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
+                im_val |= MMCST0_DATDNE | MMCST0_CRCWR;
+
+                if (!host->do_dma)
+                        im_val |= MMCST0_DXRDY;
+        } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) {
+                im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD;
+
+                if (!host->do_dma)
+                        im_val |= MMCST0_DRRDY;
+        }
+
+        /*
+         * Before non-DMA WRITE commands the controller needs priming:
+         * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size
+         */
+        if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE))
+                davinci_fifo_data_trans(host, rw_threshold);
+
+        writel(cmd->arg, host->base + DAVINCI_MMCARGHL);
+        writel(cmd_reg,  host->base + DAVINCI_MMCCMD);
+        writel(im_val, host->base + DAVINCI_MMCIM);
+}
+
+/*----------------------------------------------------------------------*/
+
+/* DMA infrastructure */
+
+static void davinci_abort_dma(struct mmc_davinci_host *host)
+{
+        int sync_dev;
+
+        if (host->data_dir == DAVINCI_MMC_DATADIR_READ)
+                sync_dev = host->rxdma;
+        else
+                sync_dev = host->txdma;
+
+        edma_stop(sync_dev);
+        edma_clean_channel(sync_dev);
+}
+
+static void
+mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data);
+
+static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data)
+{
+        if (DMA_COMPLETE != ch_status) {
+                struct mmc_davinci_host *host = data;
+
+                /* Currently means:  DMA Event Missed, or "null" transfer
+                 * request was seen.  In the future, TC errors (like bad
+                 * addresses) might be presented too.
+                 */
+                dev_warn(mmc_dev(host->mmc), "DMA %s error\n",
+                        (host->data->flags & MMC_DATA_WRITE)
+                                ? "write" : "read");
+                host->data->error = -EIO;
+                mmc_davinci_xfer_done(host, host->data);
+        }
+}
+
+/* Set up tx or rx template, to be modified and updated later */
+static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host,
+                bool tx, struct edmacc_param *template)
+{
+        unsigned        sync_dev;
+        const u16       acnt = 4;
+        const u16       bcnt = rw_threshold >> 2;
+        const u16       ccnt = 0;
+        u32             src_port = 0;
+        u32             dst_port = 0;
+        s16             src_bidx, dst_bidx;
+        s16             src_cidx, dst_cidx;
+
+        /*
+         * A-B Sync transfer:  each DMA request is for one "frame" of
+         * rw_threshold bytes, broken into "acnt"-size chunks repeated
+         * "bcnt" times.  Each segment needs "ccnt" such frames; since
+         * we tell the block layer our mmc->max_seg_size limit, we can
+         * trust (later) that it's within bounds.
+         *
+         * The FIFOs are read/written in 4-byte chunks (acnt == 4) and
+         * EDMA will optimize memory operations to use larger bursts.
+         */
+        if (tx) {
+                sync_dev = host->txdma;
+
+                /* src_prt, ccnt, and link to be set up later */
+                src_bidx = acnt;
+                src_cidx = acnt * bcnt;
+
+                dst_port = host->mem_res->start + DAVINCI_MMCDXR;
+                dst_bidx = 0;
+                dst_cidx = 0;
+        } else {
+                sync_dev = host->rxdma;
+
+                src_port = host->mem_res->start + DAVINCI_MMCDRR;
+                src_bidx = 0;
+                src_cidx = 0;
+
+                /* dst_prt, ccnt, and link to be set up later */
+                dst_bidx = acnt;
+                dst_cidx = acnt * bcnt;
+        }
+
+        /*
+         * We can't use FIFO mode for the FIFOs because MMC FIFO addresses
+         * are not 256-bit (32-byte) aligned.  So we use INCR, and the W8BIT
+         * parameter is ignored.
+         */
+        edma_set_src(sync_dev, src_port, INCR, W8BIT);
+        edma_set_dest(sync_dev, dst_port, INCR, W8BIT);
+
+        edma_set_src_index(sync_dev, src_bidx, src_cidx);
+        edma_set_dest_index(sync_dev, dst_bidx, dst_cidx);
+
+        edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC);
+
+        edma_read_slot(sync_dev, template);
+
+        /* don't bother with irqs or chaining */
+        template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12;
+}
+
+static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
+                struct mmc_data *data)
+{
+        struct edmacc_param     *template;
+        int                     channel, slot;
+        unsigned                link;
+        struct scatterlist      *sg;
+        unsigned                sg_len;
+        unsigned                bytes_left = host->bytes_left;
+        const unsigned          shift = ffs(rw_threshold) - 1;;
+
+        if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
+                template = &host->tx_template;
+                channel = host->txdma;
+        } else {
+                template = &host->rx_template;
+                channel = host->rxdma;
+        }
+
+        /* We know sg_len and ccnt will never be out of range because
+         * we told the mmc layer which in turn tells the block layer
+         * to ensure that it only hands us one scatterlist segment
+         * per EDMA PARAM entry.  Update the PARAM
+         * entries needed for each segment of this scatterlist.
+         */
+        for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len;
+                        sg_len-- != 0 && bytes_left;
+                        sg = sg_next(sg), slot = host->links[link++]) {
+                u32             buf = sg_dma_address(sg);
+                unsigned        count = sg_dma_len(sg);
+
+                template->link_bcntrld = sg_len
+                                ? (EDMA_CHAN_SLOT(host->links[link]) << 5)
+                                : 0xffff;
+
+                if (count > bytes_left)
+                        count = bytes_left;
+                bytes_left -= count;
+
+                if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
+                        template->src = buf;
+                else
+                        template->dst = buf;
+                template->ccnt = count >> shift;
+
+                edma_write_slot(slot, template);
+        }
+
+        if (host->version == MMC_CTLR_VERSION_2)
+                edma_clear_event(channel);
+
+        edma_start(channel);
+}
+
+static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
+                struct mmc_data *data)
+{
+        int i;
+        int mask = rw_threshold - 1;
+
+        host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
+                                ((data->flags & MMC_DATA_WRITE)
+                                ? DMA_TO_DEVICE
+                                : DMA_FROM_DEVICE));
+
+        /* no individual DMA segment should need a partial FIFO */
+        for (i = 0; i < host->sg_len; i++) {
+                if (sg_dma_len(data->sg + i) & mask) {
+                        dma_unmap_sg(mmc_dev(host->mmc),
+                                        data->sg, data->sg_len,
+                                        (data->flags & MMC_DATA_WRITE)
+                                        ? DMA_TO_DEVICE
+                                        : DMA_FROM_DEVICE);
+                        return -1;
+                }
+        }
+
+        host->do_dma = 1;
+        mmc_davinci_send_dma_request(host, data);
+
+        return 0;
+}
+
+static void __init_or_module
+davinci_release_dma_channels(struct mmc_davinci_host *host)
+{
+        unsigned        i;
+
+        if (!host->use_dma)
+                return;
+
+        for (i = 0; i < host->n_link; i++)
+                edma_free_slot(host->links[i]);
+
+        edma_free_channel(host->txdma);
+        edma_free_channel(host->rxdma);
+}
+
+static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host)
+{
+        int r, i;
+
+        /* Acquire master DMA write channel */
+        r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host,
+                        EVENTQ_DEFAULT);
+        if (r < 0) {
+                dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
+                                "tx", r);
+                return r;
+        }
+        mmc_davinci_dma_setup(host, true, &host->tx_template);
+
+        /* Acquire master DMA read channel */
+        r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host,
+                        EVENTQ_DEFAULT);
+        if (r < 0) {
+                dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
+                                "rx", r);
+                goto free_master_write;
+        }
+        mmc_davinci_dma_setup(host, false, &host->rx_template);
+
+        /* Allocate parameter RAM slots, which will later be bound to a
+         * channel as needed to handle a scatterlist.
+         */
+        for (i = 0; i < ARRAY_SIZE(host->links); i++) {
+                r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY);
+                if (r < 0) {
+                        dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n",
+                                r);
+                        break;
+                }
+                host->links[i] = r;
+        }
+        host->n_link = i;
+
+        return 0;
+
+free_master_write:
+        edma_free_channel(host->txdma);
+
+        return r;
+}
+
+/*----------------------------------------------------------------------*/
+
+static void
+mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req)
+{
+        int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0;
+        int timeout;
+        struct mmc_data *data = req->data;
+
+        if (host->version == MMC_CTLR_VERSION_2)
+                fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0;
+
+        host->data = data;
+        if (data == NULL) {
+                host->data_dir = DAVINCI_MMC_DATADIR_NONE;
+                writel(0, host->base + DAVINCI_MMCBLEN);
+                writel(0, host->base + DAVINCI_MMCNBLK);
+                return;
+        }
+
+        dev_dbg(mmc_dev(host->mmc), "%s %s, %d blocks of %d bytes\n",
+                (data->flags & MMC_DATA_STREAM) ? "stream" : "block",
+                (data->flags & MMC_DATA_WRITE) ? "write" : "read",
+                data->blocks, data->blksz);
+        dev_dbg(mmc_dev(host->mmc), "  DTO %d cycles + %d ns\n",
+                data->timeout_clks, data->timeout_ns);
+        timeout = data->timeout_clks +
+                (data->timeout_ns / host->ns_in_one_cycle);
+        if (timeout > 0xffff)
+                timeout = 0xffff;
+
+        writel(timeout, host->base + DAVINCI_MMCTOD);
+        writel(data->blocks, host->base + DAVINCI_MMCNBLK);
+        writel(data->blksz, host->base + DAVINCI_MMCBLEN);
+
+        /* Configure the FIFO */
+        switch (data->flags & MMC_DATA_WRITE) {
+        case MMC_DATA_WRITE:
+                host->data_dir = DAVINCI_MMC_DATADIR_WRITE;
+                writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST,
+                        host->base + DAVINCI_MMCFIFOCTL);
+                writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR,
+                        host->base + DAVINCI_MMCFIFOCTL);
+                break;
+
+        default:
+                host->data_dir = DAVINCI_MMC_DATADIR_READ;
+                writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST,
+                        host->base + DAVINCI_MMCFIFOCTL);
+                writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD,
+                        host->base + DAVINCI_MMCFIFOCTL);
+                break;
+        }
+
+        host->buffer = NULL;
+        host->bytes_left = data->blocks * data->blksz;
+
+        /* For now we try to use DMA whenever we won't need partial FIFO
+         * reads or writes, either for the whole transfer (as tested here)
+         * or for any individual scatterlist segment (tested when we call
+         * start_dma_transfer).
+         *
+         * While we *could* change that, unusual block sizes are rarely
+         * used.  The occasional fallback to PIO should't hurt.
+         */
+        if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0
+                        && mmc_davinci_start_dma_transfer(host, data) == 0) {
+                /* zero this to ensure we take no PIO paths */
+                host->bytes_left = 0;
+        } else {
+                /* Revert to CPU Copy */
+                host->sg_len = data->sg_len;
+                host->sg = host->data->sg;
+                mmc_davinci_sg_to_buf(host);
+        }
+}
+
+static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req)
+{
+        struct mmc_davinci_host *host = mmc_priv(mmc);
+        unsigned long timeout = jiffies + msecs_to_jiffies(900);
+        u32 mmcst1 = 0;
+
+        /* Card may still be sending BUSY after a previous operation,
+         * typically some kind of write.  If so, we can't proceed yet.
+         */
+        while (time_before(jiffies, timeout)) {
+                mmcst1  = readl(host->base + DAVINCI_MMCST1);
+                if (!(mmcst1 & MMCST1_BUSY))
+                        break;
+                cpu_relax();
+        }
+        if (mmcst1 & MMCST1_BUSY) {
+                dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n");
+                req->cmd->error = -ETIMEDOUT;
+                mmc_request_done(mmc, req);
+                return;
+        }
+
+        host->do_dma = 0;
+        mmc_davinci_prepare_data(host, req);
+        mmc_davinci_start_command(host, req->cmd);
+}
+
+static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host,
+        unsigned int mmc_req_freq)
+{
+        unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0;
+
+        mmc_pclk = host->mmc_input_clk;
+        if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq))
+                mmc_push_pull_divisor = ((unsigned int)mmc_pclk
+                                / (2 * mmc_req_freq)) - 1;
+        else
+                mmc_push_pull_divisor = 0;
+
+        mmc_freq = (unsigned int)mmc_pclk
+                / (2 * (mmc_push_pull_divisor + 1));
+
+        if (mmc_freq > mmc_req_freq)
+                mmc_push_pull_divisor = mmc_push_pull_divisor + 1;
+        /* Convert ns to clock cycles */
+        if (mmc_req_freq <= 400000)
+                host->ns_in_one_cycle = (1000000) / (((mmc_pclk
+                                / (2 * (mmc_push_pull_divisor + 1)))/1000));
+        else
+                host->ns_in_one_cycle = (1000000) / (((mmc_pclk
+                                / (2 * (mmc_push_pull_divisor + 1)))/1000000));
+
+        return mmc_push_pull_divisor;
+}
+
+static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+        unsigned int open_drain_freq = 0, mmc_pclk = 0;
+        unsigned int mmc_push_pull_freq = 0;
+        struct mmc_davinci_host *host = mmc_priv(mmc);
+
+        if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
+                u32 temp;
+
+                /* Ignoring the init clock value passed for fixing the inter
+                 * operability with different cards.
+                 */
+                open_drain_freq = ((unsigned int)mmc_pclk
+                                / (2 * MMCSD_INIT_CLOCK)) - 1;
+
+                if (open_drain_freq > 0xFF)
+                        open_drain_freq = 0xFF;
+
+                temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
+                temp |= open_drain_freq;
+                writel(temp, host->base + DAVINCI_MMCCLK);
+
+                /* Convert ns to clock cycles */
+                host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000);
+        } else {
+                u32 temp;
+                mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock);
+
+                if (mmc_push_pull_freq > 0xFF)
+                        mmc_push_pull_freq = 0xFF;
+
+                temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN;
+                writel(temp, host->base + DAVINCI_MMCCLK);
+
+                udelay(10);
+
+                temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
+                temp |= mmc_push_pull_freq;
+                writel(temp, host->base + DAVINCI_MMCCLK);
+
+                writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
+
+                udelay(10);
+        }
+}
+
+static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+        struct mmc_davinci_host *host = mmc_priv(mmc);
+
+        dev_dbg(mmc_dev(host->mmc),
+                "clock %dHz busmode %d powermode %d Vdd %04x\n",
+                ios->clock, ios->bus_mode, ios->power_mode,
+                ios->vdd);
+
+        switch (ios->bus_width) {
+        case MMC_BUS_WIDTH_8:
+                dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n");
+                writel((readl(host->base + DAVINCI_MMCCTL) &
+                        ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT,
+                        host->base + DAVINCI_MMCCTL);
+                break;
+        case MMC_BUS_WIDTH_4:
+                dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n");
+                if (host->version == MMC_CTLR_VERSION_2)
+                        writel((readl(host->base + DAVINCI_MMCCTL) &
+                                ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT,
+                                host->base + DAVINCI_MMCCTL);
+                else
+                        writel(readl(host->base + DAVINCI_MMCCTL) |
+                                MMCCTL_WIDTH_4_BIT,
+                                host->base + DAVINCI_MMCCTL);
+                break;
+        case MMC_BUS_WIDTH_1:
+                dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n");
+                if (host->version == MMC_CTLR_VERSION_2)
+                        writel(readl(host->base + DAVINCI_MMCCTL) &
+                                ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT),
+                                host->base + DAVINCI_MMCCTL);
+                else
+                        writel(readl(host->base + DAVINCI_MMCCTL) &
+                                ~MMCCTL_WIDTH_4_BIT,
+                                host->base + DAVINCI_MMCCTL);
+                break;
+        }
+
+        calculate_clk_divider(mmc, ios);
+
+        host->bus_mode = ios->bus_mode;
+        if (ios->power_mode == MMC_POWER_UP) {
+                unsigned long timeout = jiffies + msecs_to_jiffies(50);
+                bool lose = true;
+
+                /* Send clock cycles, poll completion */
+                writel(0, host->base + DAVINCI_MMCARGHL);
+                writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD);
+                while (time_before(jiffies, timeout)) {
+                        u32 tmp = readl(host->base + DAVINCI_MMCST0);
+
+                        if (tmp & MMCST0_RSPDNE) {
+                                lose = false;
+                                break;
+                        }
+                        cpu_relax();
+                }
+                if (lose)
+                        dev_warn(mmc_dev(host->mmc), "powerup timeout\n");
+        }
+
+        /* FIXME on power OFF, reset things ... */
+}
+
+static void
+mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data)
+{
+        host->data = NULL;
+
+        if (host->do_dma) {
+                davinci_abort_dma(host);
+
+                dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
+                             (data->flags & MMC_DATA_WRITE)
+                             ? DMA_TO_DEVICE
+                             : DMA_FROM_DEVICE);
+                host->do_dma = false;
+        }
+        host->data_dir = DAVINCI_MMC_DATADIR_NONE;
+
+        if (!data->stop || (host->cmd && host->cmd->error)) {
+                mmc_request_done(host->mmc, data->mrq);
+                writel(0, host->base + DAVINCI_MMCIM);
+        } else
+                mmc_davinci_start_command(host, data->stop);
+}
+
+static void mmc_davinci_cmd_done(struct mmc_davinci_host *host,
+                                 struct mmc_command *cmd)
+{
+        host->cmd = NULL;
+
+        if (cmd->flags & MMC_RSP_PRESENT) {
+                if (cmd->flags & MMC_RSP_136) {
+                        /* response type 2 */
+                        cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01);
+                        cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23);
+                        cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45);
+                        cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
+                } else {
+                        /* response types 1, 1b, 3, 4, 5, 6 */
+                        cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
+                }
+        }
+
+        if (host->data == NULL || cmd->error) {
+                if (cmd->error == -ETIMEDOUT)
+                        cmd->mrq->cmd->retries = 0;
+                mmc_request_done(host->mmc, cmd->mrq);
+                writel(0, host->base + DAVINCI_MMCIM);
+        }
+}
+
+static void
+davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data)
+{
+        u32 temp;
+
+        /* reset command and data state machines */
+        temp = readl(host->base + DAVINCI_MMCCTL);
+        writel(temp | MMCCTL_CMDRST | MMCCTL_DATRST,
+                host->base + DAVINCI_MMCCTL);
+
+        temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST);
+        udelay(10);
+        writel(temp, host->base + DAVINCI_MMCCTL);
+}
+
+static irqreturn_t mmc_davinci_irq(int irq, void *dev_id)
+{
+        struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
+        unsigned int status, qstatus;
+        int end_command = 0;
+        int end_transfer = 0;
+        struct mmc_data *data = host->data;
+
+        if (host->cmd == NULL && host->data == NULL) {
+                status = readl(host->base + DAVINCI_MMCST0);
+                dev_dbg(mmc_dev(host->mmc),
+                        "Spurious interrupt 0x%04x\n", status);
+                /* Disable the interrupt from mmcsd */
+                writel(0, host->base + DAVINCI_MMCIM);
+                return IRQ_NONE;
+        }
+
+        status = readl(host->base + DAVINCI_MMCST0);
+        qstatus = status;
+
+        /* handle FIFO first when using PIO for data.
+         * bytes_left will decrease to zero as I/O progress and status will
+         * read zero over iteration because this controller status
+         * register(MMCST0) reports any status only once and it is cleared
+         * by read. So, it is not unbouned loop even in the case of
+         * non-dma.
+         */
+        while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) {
+                davinci_fifo_data_trans(host, rw_threshold);
+                status = readl(host->base + DAVINCI_MMCST0);
+                if (!status)
+                        break;
+                qstatus |= status;
+        }
+
+        if (qstatus & MMCST0_DATDNE) {
+                /* All blocks sent/received, and CRC checks passed */
+                if (data != NULL) {
+                        if ((host->do_dma == 0) && (host->bytes_left > 0)) {
+                                /* if datasize < rw_threshold
+                                 * no RX ints are generated
+                                 */
+                                davinci_fifo_data_trans(host, host->bytes_left);
+                        }
+                        end_transfer = 1;
+                        data->bytes_xfered = data->blocks * data->blksz;
+                } else {
+                        dev_err(mmc_dev(host->mmc),
+                                        "DATDNE with no host->data\n");
+                }
+        }
+
+        if (qstatus & MMCST0_TOUTRD) {
+                /* Read data timeout */
+                data->error = -ETIMEDOUT;
+                end_transfer = 1;
+
+                dev_dbg(mmc_dev(host->mmc),
+                        "read data timeout, status %x\n",
+                        qstatus);
+
+                davinci_abort_data(host, data);
+        }
+
+        if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) {
+                /* Data CRC error */
+                data->error = -EILSEQ;
+                end_transfer = 1;
+
+                /* NOTE:  this controller uses CRCWR to report both CRC
+                 * errors and timeouts (on writes).  MMCDRSP values are
+                 * only weakly documented, but 0x9f was clearly a timeout
+                 * case and the two three-bit patterns in various SD specs
+                 * (101, 010) aren't part of it ...
+                 */
+                if (qstatus & MMCST0_CRCWR) {
+                        u32 temp = readb(host->base + DAVINCI_MMCDRSP);
+
+                        if (temp == 0x9f)
+                                data->error = -ETIMEDOUT;
+                }
+                dev_dbg(mmc_dev(host->mmc), "data %s %s error\n",
+                        (qstatus & MMCST0_CRCWR) ? "write" : "read",
+                        (data->error == -ETIMEDOUT) ? "timeout" : "CRC");
+
+                davinci_abort_data(host, data);
+        }
+
+        if (qstatus & MMCST0_TOUTRS) {
+                /* Command timeout */
+                if (host->cmd) {
+                        dev_dbg(mmc_dev(host->mmc),
+                                "CMD%d timeout, status %x\n",
+                                host->cmd->opcode, qstatus);
+                        host->cmd->error = -ETIMEDOUT;
+                        if (data) {
+                                end_transfer = 1;
+                                davinci_abort_data(host, data);
+                        } else
+                                end_command = 1;
+                }
+        }
+
+        if (qstatus & MMCST0_CRCRS) {
+                /* Command CRC error */
+                dev_dbg(mmc_dev(host->mmc), "Command CRC error\n");
+                if (host->cmd) {
+                        host->cmd->error = -EILSEQ;
+                        end_command = 1;
+                }
+        }
+
+        if (qstatus & MMCST0_RSPDNE) {
+                /* End of command phase */
+                end_command = (int) host->cmd;
+        }
+
+        if (end_command)
+                mmc_davinci_cmd_done(host, host->cmd);
+        if (end_transfer)
+                mmc_davinci_xfer_done(host, data);
+        return IRQ_HANDLED;
+}
+
+static int mmc_davinci_get_cd(struct mmc_host *mmc)
+{
+        struct platform_device *pdev = to_platform_device(mmc->parent);
+        struct davinci_mmc_config *config = pdev->dev.platform_data;
+
+        if (!config || !config->get_cd)
+                return -ENOSYS;
+        return config->get_cd(pdev->id);
+}
+
+static int mmc_davinci_get_ro(struct mmc_host *mmc)
+{
+        struct platform_device *pdev = to_platform_device(mmc->parent);
+        struct davinci_mmc_config *config = pdev->dev.platform_data;
+
+        if (!config || !config->get_ro)
+                return -ENOSYS;
+        return config->get_ro(pdev->id);
+}
+
+static struct mmc_host_ops mmc_davinci_ops = {
+        .request        = mmc_davinci_request,
+        .set_ios        = mmc_davinci_set_ios,
+        .get_cd         = mmc_davinci_get_cd,
+        .get_ro         = mmc_davinci_get_ro,
+};
+
+/*----------------------------------------------------------------------*/
+
+#ifdef CONFIG_CPU_FREQ
+static int mmc_davinci_cpufreq_transition(struct notifier_block *nb,
+                                     unsigned long val, void *data)
+{
+        struct mmc_davinci_host *host;
+        unsigned int mmc_pclk;
+        struct mmc_host *mmc;
+        unsigned long flags;
+
+        host = container_of(nb, struct mmc_davinci_host, freq_transition);
+        mmc = host->mmc;
+        mmc_pclk = clk_get_rate(host->clk);
+
+        if (val == CPUFREQ_POSTCHANGE) {
+                spin_lock_irqsave(&mmc->lock, flags);
+                host->mmc_input_clk = mmc_pclk;
+                calculate_clk_divider(mmc, &mmc->ios);
+                spin_unlock_irqrestore(&mmc->lock, flags);
+        }
+
+        return 0;
+}
+
+static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
+{
+        host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition;
+
+        return cpufreq_register_notifier(&host->freq_transition,
+                                         CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
+{
+        cpufreq_unregister_notifier(&host->freq_transition,
+                                    CPUFREQ_TRANSITION_NOTIFIER);
+}
+#else
+static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
+{
+        return 0;
+}
+
+static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
+{
+}
+#endif
+static void __init init_mmcsd_host(struct mmc_davinci_host *host)
+{
+        /* DAT line portion is diabled and in reset state */
+        writel(readl(host->base + DAVINCI_MMCCTL) | MMCCTL_DATRST,
+                host->base + DAVINCI_MMCCTL);
+
+        /* CMD line portion is diabled and in reset state */
+        writel(readl(host->base + DAVINCI_MMCCTL) | MMCCTL_CMDRST,
+                host->base + DAVINCI_MMCCTL);
+
+        udelay(10);
+
+        writel(0, host->base + DAVINCI_MMCCLK);
+        writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
+
+        writel(0x1FFF, host->base + DAVINCI_MMCTOR);
+        writel(0xFFFF, host->base + DAVINCI_MMCTOD);
+
+        writel(readl(host->base + DAVINCI_MMCCTL) & ~MMCCTL_DATRST,
+                host->base + DAVINCI_MMCCTL);
+        writel(readl(host->base + DAVINCI_MMCCTL) & ~MMCCTL_CMDRST,
+                host->base + DAVINCI_MMCCTL);
+
+        udelay(10);
+}
+
+static int __init davinci_mmcsd_probe(struct platform_device *pdev)
+{
+        struct davinci_mmc_config *pdata = pdev->dev.platform_data;
+        struct mmc_davinci_host *host = NULL;
+        struct mmc_host *mmc = NULL;
+        struct resource *r, *mem = NULL;
+        int ret = 0, irq = 0;
+        size_t mem_size;
+
+        /* REVISIT:  when we're fully converted, fail if pdata is NULL */
+
+        ret = -ENODEV;
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        irq = platform_get_irq(pdev, 0);
+        if (!r || irq == NO_IRQ)
+                goto out;
+
+        ret = -EBUSY;
+        mem_size = resource_size(r);
+        mem = request_mem_region(r->start, mem_size, pdev->name);
+        if (!mem)
+                goto out;
+
+        ret = -ENOMEM;
+        mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev);
+        if (!mmc)
+                goto out;
+
+        host = mmc_priv(mmc);
+        host->mmc = mmc;        /* Important */
+
+        r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+        if (!r)
+                goto out;
+        host->rxdma = r->start;
+
+        r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
+        if (!r)
+                goto out;
+        host->txdma = r->start;
+
+        host->mem_res = mem;
+        host->base = ioremap(mem->start, mem_size);
+        if (!host->base)
+                goto out;
+
+        ret = -ENXIO;
+        host->clk = clk_get(&pdev->dev, "MMCSDCLK");
+        if (IS_ERR(host->clk)) {
+                ret = PTR_ERR(host->clk);
+                goto out;
+        }
+        clk_enable(host->clk);
+        host->mmc_input_clk = clk_get_rate(host->clk);
+
+        init_mmcsd_host(host);
+
+        host->use_dma = use_dma;
+        host->irq = irq;
+
+        if (host->use_dma && davinci_acquire_dma_channels(host) != 0)
+                host->use_dma = 0;
+
+        /* REVISIT:  someday, support IRQ-driven card detection.  */
+        mmc->caps |= MMC_CAP_NEEDS_POLL;
+        mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
+
+        if (pdata && (pdata->wires == 4 || pdata->wires == 0))
+                mmc->caps |= MMC_CAP_4_BIT_DATA;
+
+        if (pdata && (pdata->wires == 8))
+                mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
+
+        host->version = pdata->version;
+
+        mmc->ops = &mmc_davinci_ops;
+        mmc->f_min = 312500;
+        mmc->f_max = 25000000;
+        if (pdata && pdata->max_freq)
+                mmc->f_max = pdata->max_freq;
+        if (pdata && pdata->caps)
+                mmc->caps |= pdata->caps;
+        mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+        /* With no iommu coalescing pages, each phys_seg is a hw_seg.
+         * Each hw_seg uses one EDMA parameter RAM slot, always one
+         * channel and then usually some linked slots.
+         */
+        mmc->max_hw_segs        = 1 + host->n_link;
+        mmc->max_phys_segs      = mmc->max_hw_segs;
+
+        /* EDMA limit per hw segment (one or two MBytes) */
+        mmc->max_seg_size       = MAX_CCNT * rw_threshold;
+
+        /* MMC/SD controller limits for multiblock requests */
+        mmc->max_blk_size       = 4095;  /* BLEN is 12 bits */
+        mmc->max_blk_count      = 65535; /* NBLK is 16 bits */
+        mmc->max_req_size       = mmc->max_blk_size * mmc->max_blk_count;
+
+        dev_dbg(mmc_dev(host->mmc), "max_phys_segs=%d\n", mmc->max_phys_segs);
+        dev_dbg(mmc_dev(host->mmc), "max_hw_segs=%d\n", mmc->max_hw_segs);
+        dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size);
+        dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size);
+        dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size);
+
+        platform_set_drvdata(pdev, host);
+
+        ret = mmc_davinci_cpufreq_register(host);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register cpufreq\n");
+                goto cpu_freq_fail;
+        }
+
+        ret = mmc_add_host(mmc);
+        if (ret < 0)
+                goto out;
+
+        ret = request_irq(irq, mmc_davinci_irq, 0, mmc_hostname(mmc), host);
+        if (ret)
+                goto out;
+
+        rename_region(mem, mmc_hostname(mmc));
+
+        dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n",
+                host->use_dma ? "DMA" : "PIO",
+                (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
+
+        return 0;
+
+out:
+        mmc_davinci_cpufreq_deregister(host);
+cpu_freq_fail:
+        if (host) {
+                davinci_release_dma_channels(host);
+
+                if (host->clk) {
+                        clk_disable(host->clk);
+                        clk_put(host->clk);
+                }
+
+                if (host->base)
+                        iounmap(host->base);
+        }
+
+        if (mmc)
+                mmc_free_host(mmc);
+
+        if (mem)
+                release_resource(mem);
+
+        dev_dbg(&pdev->dev, "probe err %d\n", ret);
+
+        return ret;
+}
+
+static int __exit davinci_mmcsd_remove(struct platform_device *pdev)
+{
+        struct mmc_davinci_host *host = platform_get_drvdata(pdev);
+
+        platform_set_drvdata(pdev, NULL);
+        if (host) {
+                mmc_davinci_cpufreq_deregister(host);
+
+                mmc_remove_host(host->mmc);
+                free_irq(host->irq, host);
+
+                davinci_release_dma_channels(host);
+
+                clk_disable(host->clk);
+                clk_put(host->clk);
+
+                iounmap(host->base);
+
+                release_resource(host->mem_res);
+
+                mmc_free_host(host->mmc);
+        }
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int davinci_mmcsd_suspend(struct platform_device *pdev, pm_message_t msg)
+{
+        struct mmc_davinci_host *host = platform_get_drvdata(pdev);
+
+        return mmc_suspend_host(host->mmc, msg);
+}
+
+static int davinci_mmcsd_resume(struct platform_device *pdev)
+{
+        struct mmc_davinci_host *host = platform_get_drvdata(pdev);
+
+        return mmc_resume_host(host->mmc);
+}
+#else
+#define davinci_mmcsd_suspend   NULL
+#define davinci_mmcsd_resume    NULL
+#endif
+
+static struct platform_driver davinci_mmcsd_driver = {
+        .driver         = {
+                .name   = "davinci_mmc",
+                .owner  = THIS_MODULE,
+        },
+        .remove         = __exit_p(davinci_mmcsd_remove),
+        .suspend        = davinci_mmcsd_suspend,
+        .resume         = davinci_mmcsd_resume,
+};
+
+static int __init davinci_mmcsd_init(void)
+{
+        return platform_driver_probe(&davinci_mmcsd_driver,
+                                     davinci_mmcsd_probe);
+}
+module_init(davinci_mmcsd_init);
+
+static void __exit davinci_mmcsd_exit(void)
+{
+        platform_driver_unregister(&davinci_mmcsd_driver);
+}
+module_exit(davinci_mmcsd_exit);
+
+MODULE_AUTHOR("Texas Instruments India");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller");
+
diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c
index d55fe4fb7935..ad847a24a675 100644
--- a/drivers/mmc/host/mmc_spi.c
+++ b/drivers/mmc/host/mmc_spi.c
@@ -26,6 +26,7 @@
  */
 #include <linux/sched.h>
 #include <linux/delay.h>
+#include <linux/slab.h>
 #include <linux/bio.h>
 #include <linux/dma-mapping.h>
 #include <linux/crc7.h>
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 705a5894a6bb..84c103a7ee13 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -2,6 +2,7 @@
  *  linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
  *
  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
+ *  Copyright (C) 2010 ST-Ericsson AB.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -34,9 +35,6 @@
 
 #define DRIVER_NAME "mmci-pl18x"
 
-#define DBG(host,fmt,args...)   \
-        pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
-
 static unsigned int fmax = 515633;
 
 /*
@@ -56,7 +54,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
                                 clk = 255;
                         host->cclk = host->mclk / (2 * (clk + 1));
                 }
-                if (host->hw_designer == 0x80)
+                if (host->hw_designer == AMBA_VENDOR_ST)
                         clk |= MCI_FCEN; /* Bug fix in ST IP block */
                 clk |= MCI_CLK_ENABLE;
                 /* This hasn't proven to be worthwhile */
@@ -105,8 +103,8 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
         void __iomem *base;
         int blksz_bits;
 
-        DBG(host, "blksz %04x blks %04x flags %08x\n",
-            data->blksz, data->blocks, data->flags);
+        dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
+                data->blksz, data->blocks, data->flags);
 
         host->data = data;
         host->size = data->blksz;
@@ -155,7 +153,7 @@ mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
 {
         void __iomem *base = host->base;
 
-        DBG(host, "op %02x arg %08x flags %08x\n",
+        dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
             cmd->opcode, cmd->arg, cmd->flags);
 
         if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
@@ -184,8 +182,20 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
 {
         if (status & MCI_DATABLOCKEND) {
                 host->data_xfered += data->blksz;
+#ifdef CONFIG_ARCH_U300
+                /*
+                 * On the U300 some signal or other is
+                 * badly routed so that a data write does
+                 * not properly terminate with a MCI_DATAEND
+                 * status flag. This quirk will make writes
+                 * work again.
+                 */
+                if (data->flags & MMC_DATA_WRITE)
+                        status |= MCI_DATAEND;
+#endif
         }
         if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
+                dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status);
                 if (status & MCI_DATACRCFAIL)
                         data->error = -EILSEQ;
                 else if (status & MCI_DATATIMEOUT)
@@ -307,7 +317,7 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
 
         status = readl(base + MMCISTATUS);
 
-        DBG(host, "irq1 %08x\n", status);
+        dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
 
         do {
                 unsigned long flags;
@@ -401,7 +411,7 @@ static irqreturn_t mmci_irq(int irq, void *dev_id)
                 status &= readl(host->base + MMCIMASK0);
                 writel(status, host->base + MMCICLEAR);
 
-                DBG(host, "irq0 %08x\n", status);
+                dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
 
                 data = host->data;
                 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
@@ -428,8 +438,8 @@ static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
         WARN_ON(host->mrq != NULL);
 
         if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
-                printk(KERN_ERR "%s: Unsupported block size (%d bytes)\n",
-                        mmc_hostname(mmc), mrq->data->blksz);
+                dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
+                        mrq->data->blksz);
                 mrq->cmd->error = -EINVAL;
                 mmc_request_done(mmc, mrq);
                 return;
@@ -582,8 +592,8 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 
         host->hw_designer = amba_manf(dev);
         host->hw_revision = amba_rev(dev);
-        DBG(host, "designer ID = 0x%02x\n", host->hw_designer);
-        DBG(host, "revision = 0x%01x\n", host->hw_revision);
+        dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
+        dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
 
         host->clk = clk_get(&dev->dev, NULL);
         if (IS_ERR(host->clk)) {
@@ -608,7 +618,8 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
                 if (ret < 0)
                         goto clk_disable;
                 host->mclk = clk_get_rate(host->clk);
-                DBG(host, "eventual mclk rate: %u Hz\n", host->mclk);
+                dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
+                        host->mclk);
         }
         host->base = ioremap(dev->res.start, resource_size(&dev->res));
         if (!host->base) {
@@ -619,6 +630,8 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
         mmc->ops = &mmci_ops;
         mmc->f_min = (host->mclk + 511) / 512;
         mmc->f_max = min(host->mclk, fmax);
+        dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
+
 #ifdef CONFIG_REGULATOR
         /* If we're using the regulator framework, try to fetch a regulator */
         host->vcc = regulator_get(&dev->dev, "vmmc");
@@ -712,7 +725,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 
         mmc_add_host(mmc);
 
-        printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
+        dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
                 mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
                 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
 
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index dba4600bcdb4..04ae884383f6 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -33,15 +33,15 @@
 #include <linux/debugfs.h>
 #include <linux/io.h>
 #include <linux/memory.h>
+#include <linux/gfp.h>
 
 #include <asm/cacheflush.h>
 #include <asm/div64.h>
 #include <asm/sizes.h>
 
-#include <asm/mach/mmc.h>
+#include <mach/mmc.h>
 #include <mach/msm_iomap.h>
 #include <mach/dma.h>
-#include <mach/htc_pwrsink.h>
 
 #include "msm_sdcc.h"
 
@@ -775,13 +775,11 @@ msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
         switch (ios->power_mode) {
         case MMC_POWER_OFF:
-                htc_pwrsink_set(PWRSINK_SDCARD, 0);
                 break;
         case MMC_POWER_UP:
                 pwr |= MCI_PWR_UP;
                 break;
         case MMC_POWER_ON:
-                htc_pwrsink_set(PWRSINK_SDCARD, 100);
                 pwr |= MCI_PWR_ON;
                 break;
         }
@@ -1253,9 +1251,7 @@ msmsdcc_resume(struct platform_device *dev)
 
                 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
                         mmc_resume_host(mmc);
-                        if (host->stat_irq)
-                                enable_irq(host->stat_irq);
-                else if (host->stat_irq)
+                if (host->stat_irq)
                         enable_irq(host->stat_irq);
         }
         return 0;
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index 88671529c45d..2df90412abb5 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -4,7 +4,7 @@
  *  This is a driver for the SDHC controller found in Freescale MX2/MX3
  *  SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
  *  Unlike the hardware found on MX1, this hardware just works and does
- *  not need all the quirks found in imxmmc.c, hence the seperate driver.
+ *  not need all the quirks found in imxmmc.c, hence the separate driver.
  *
  *  Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  *  Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
@@ -679,17 +679,17 @@ static int mxcmci_probe(struct platform_device *pdev)
 {
         struct mmc_host *mmc;
         struct mxcmci_host *host = NULL;
-        struct resource *r;
+        struct resource *iores, *r;
         int ret = 0, irq;
 
         printk(KERN_INFO "i.MX SDHC driver\n");
 
-        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         irq = platform_get_irq(pdev, 0);
-        if (!r || irq < 0)
+        if (!iores || irq < 0)
                 return -EINVAL;
 
-        r = request_mem_region(r->start, resource_size(r), pdev->name);
+        r = request_mem_region(iores->start, resource_size(iores), pdev->name);
         if (!r)
                 return -EBUSY;
 
@@ -708,7 +708,7 @@ static int mxcmci_probe(struct platform_device *pdev)
         mmc->max_blk_size = 2048;
         mmc->max_blk_count = 65535;
         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
-        mmc->max_seg_size = mmc->max_seg_size;
+        mmc->max_seg_size = mmc->max_req_size;
 
         host = mmc_priv(mmc);
         host->base = ioremap(r->start, resource_size(r));
@@ -809,7 +809,7 @@ out_iounmap:
 out_free:
         mmc_free_host(mmc);
 out_release_mem:
-        release_mem_region(host->res->start, resource_size(host->res));
+        release_mem_region(iores->start, resource_size(iores));
         return ret;
 }
 
diff --git a/drivers/mmc/host/of_mmc_spi.c b/drivers/mmc/host/of_mmc_spi.c
index 0c44d560bf1a..bb6cc54b558e 100644
--- a/drivers/mmc/host/of_mmc_spi.c
+++ b/drivers/mmc/host/of_mmc_spi.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/device.h>
+#include <linux/slab.h>
 #include <linux/gpio.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
@@ -22,6 +23,8 @@
 #include <linux/mmc/core.h>
 #include <linux/mmc/host.h>
 
+MODULE_LICENSE("GPL");
+
 enum {
         CD_GPIO = 0,
         WP_GPIO,
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c
index b8fd7af1ceeb..84d280406341 100644
--- a/drivers/mmc/host/omap.c
+++ b/drivers/mmc/host/omap.c
@@ -26,16 +26,17 @@
 #include <linux/clk.h>
 #include <linux/scatterlist.h>
 #include <linux/i2c/tps65010.h>
+#include <linux/slab.h>
 
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <mach/board.h>
-#include <mach/mmc.h>
+#include <plat/board.h>
+#include <plat/mmc.h>
 #include <mach/gpio.h>
-#include <mach/dma.h>
-#include <mach/mux.h>
-#include <mach/fpga.h>
+#include <plat/dma.h>
+#include <plat/mux.h>
+#include <plat/fpga.h>
 
 #define OMAP_MMC_REG_CMD        0x00
 #define OMAP_MMC_REG_ARGL       0x04
@@ -1459,8 +1460,10 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
                 goto err_ioremap;
 
         host->iclk = clk_get(&pdev->dev, "ick");
-        if (IS_ERR(host->iclk))
+        if (IS_ERR(host->iclk)) {
+                ret = PTR_ERR(host->iclk);
                 goto err_free_mmc_host;
+        }
         clk_enable(host->iclk);
 
         host->fclk = clk_get(&pdev->dev, "fck");
@@ -1500,10 +1503,8 @@ err_free_irq:
 err_free_fclk:
         clk_put(host->fclk);
 err_free_iclk:
-        if (host->iclk != NULL) {
-                clk_disable(host->iclk);
-                clk_put(host->iclk);
-        }
+        clk_disable(host->iclk);
+        clk_put(host->iclk);
 err_free_mmc_host:
         iounmap(host->virt_base);
 err_ioremap:
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 0aecaaebef3d..e9caf694c59e 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -30,11 +30,13 @@
 #include <linux/mmc/core.h>
 #include <linux/io.h>
 #include <linux/semaphore.h>
-#include <mach/dma.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <plat/dma.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/mmc.h>
-#include <mach/cpu.h>
+#include <plat/board.h>
+#include <plat/mmc.h>
+#include <plat/cpu.h>
 
 /* OMAP HSMMC Host Controller Registers */
 #define OMAP_HSMMC_SYSCONFIG    0x0010
@@ -146,6 +148,15 @@ struct omap_hsmmc_host {
         struct  clk             *fclk;
         struct  clk             *iclk;
         struct  clk             *dbclk;
+        /*
+         * vcc == configured supply
+         * vcc_aux == optional
+         *   -  MMC1, supply for DAT4..DAT7
+         *   -  MMC2/MMC2, external level shifter voltage supply, for
+         *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
+         */
+        struct  regulator       *vcc;
+        struct  regulator       *vcc_aux;
         struct  semaphore       sem;
         struct  work_struct     mmc_carddetect_work;
         void    __iomem         *base;
@@ -171,10 +182,337 @@ struct omap_hsmmc_host {
         int                     vdd;
         int                     protect_card;
         int                     reqs_blocked;
+        int                     use_reg;
 
         struct  omap_mmc_platform_data  *pdata;
 };
 
+static int omap_hsmmc_card_detect(struct device *dev, int slot)
+{
+        struct omap_mmc_platform_data *mmc = dev->platform_data;
+
+        /* NOTE: assumes card detect signal is active-low */
+        return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
+}
+
+static int omap_hsmmc_get_wp(struct device *dev, int slot)
+{
+        struct omap_mmc_platform_data *mmc = dev->platform_data;
+
+        /* NOTE: assumes write protect signal is active-high */
+        return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
+}
+
+static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
+{
+        struct omap_mmc_platform_data *mmc = dev->platform_data;
+
+        /* NOTE: assumes card detect signal is active-low */
+        return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
+}
+
+#ifdef CONFIG_PM
+
+static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
+{
+        struct omap_mmc_platform_data *mmc = dev->platform_data;
+
+        disable_irq(mmc->slots[0].card_detect_irq);
+        return 0;
+}
+
+static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
+{
+        struct omap_mmc_platform_data *mmc = dev->platform_data;
+
+        enable_irq(mmc->slots[0].card_detect_irq);
+        return 0;
+}
+
+#else
+
+#define omap_hsmmc_suspend_cdirq        NULL
+#define omap_hsmmc_resume_cdirq         NULL
+
+#endif
+
+#ifdef CONFIG_REGULATOR
+
+static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
+                                  int vdd)
+{
+        struct omap_hsmmc_host *host =
+                platform_get_drvdata(to_platform_device(dev));
+        int ret;
+
+        if (mmc_slot(host).before_set_reg)
+                mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
+
+        if (power_on)
+                ret = mmc_regulator_set_ocr(host->vcc, vdd);
+        else
+                ret = mmc_regulator_set_ocr(host->vcc, 0);
+
+        if (mmc_slot(host).after_set_reg)
+                mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
+
+        return ret;
+}
+
+static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
+                                   int vdd)
+{
+        struct omap_hsmmc_host *host =
+                platform_get_drvdata(to_platform_device(dev));
+        int ret = 0;
+
+        /*
+         * If we don't see a Vcc regulator, assume it's a fixed
+         * voltage always-on regulator.
+         */
+        if (!host->vcc)
+                return 0;
+
+        if (mmc_slot(host).before_set_reg)
+                mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
+
+        /*
+         * Assume Vcc regulator is used only to power the card ... OMAP
+         * VDDS is used to power the pins, optionally with a transceiver to
+         * support cards using voltages other than VDDS (1.8V nominal).  When a
+         * transceiver is used, DAT3..7 are muxed as transceiver control pins.
+         *
+         * In some cases this regulator won't support enable/disable;
+         * e.g. it's a fixed rail for a WLAN chip.
+         *
+         * In other cases vcc_aux switches interface power.  Example, for
+         * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
+         * chips/cards need an interface voltage rail too.
+         */
+        if (power_on) {
+                ret = mmc_regulator_set_ocr(host->vcc, vdd);
+                /* Enable interface voltage rail, if needed */
+                if (ret == 0 && host->vcc_aux) {
+                        ret = regulator_enable(host->vcc_aux);
+                        if (ret < 0)
+                                ret = mmc_regulator_set_ocr(host->vcc, 0);
+                }
+        } else {
+                if (host->vcc_aux)
+                        ret = regulator_disable(host->vcc_aux);
+                if (ret == 0)
+                        ret = mmc_regulator_set_ocr(host->vcc, 0);
+        }
+
+        if (mmc_slot(host).after_set_reg)
+                mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
+
+        return ret;
+}
+
+static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
+                                  int vdd, int cardsleep)
+{
+        struct omap_hsmmc_host *host =
+                platform_get_drvdata(to_platform_device(dev));
+        int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
+
+        return regulator_set_mode(host->vcc, mode);
+}
+
+static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
+                                   int vdd, int cardsleep)
+{
+        struct omap_hsmmc_host *host =
+                platform_get_drvdata(to_platform_device(dev));
+        int err, mode;
+
+        /*
+         * If we don't see a Vcc regulator, assume it's a fixed
+         * voltage always-on regulator.
+         */
+        if (!host->vcc)
+                return 0;
+
+        mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
+
+        if (!host->vcc_aux)
+                return regulator_set_mode(host->vcc, mode);
+
+        if (cardsleep) {
+                /* VCC can be turned off if card is asleep */
+                if (sleep)
+                        err = mmc_regulator_set_ocr(host->vcc, 0);
+                else
+                        err = mmc_regulator_set_ocr(host->vcc, vdd);
+        } else
+                err = regulator_set_mode(host->vcc, mode);
+        if (err)
+                return err;
+
+        if (!mmc_slot(host).vcc_aux_disable_is_sleep)
+                return regulator_set_mode(host->vcc_aux, mode);
+
+        if (sleep)
+                return regulator_disable(host->vcc_aux);
+        else
+                return regulator_enable(host->vcc_aux);
+}
+
+static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
+{
+        struct regulator *reg;
+        int ret = 0;
+
+        switch (host->id) {
+        case OMAP_MMC1_DEVID:
+                /* On-chip level shifting via PBIAS0/PBIAS1 */
+                mmc_slot(host).set_power = omap_hsmmc_1_set_power;
+                mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
+                break;
+        case OMAP_MMC2_DEVID:
+        case OMAP_MMC3_DEVID:
+                /* Off-chip level shifting, or none */
+                mmc_slot(host).set_power = omap_hsmmc_23_set_power;
+                mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
+                break;
+        default:
+                pr_err("MMC%d configuration not supported!\n", host->id);
+                return -EINVAL;
+        }
+
+        reg = regulator_get(host->dev, "vmmc");
+        if (IS_ERR(reg)) {
+                dev_dbg(host->dev, "vmmc regulator missing\n");
+                /*
+                * HACK: until fixed.c regulator is usable,
+                * we don't require a main regulator
+                * for MMC2 or MMC3
+                */
+                if (host->id == OMAP_MMC1_DEVID) {
+                        ret = PTR_ERR(reg);
+                        goto err;
+                }
+        } else {
+                host->vcc = reg;
+                mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
+
+                /* Allow an aux regulator */
+                reg = regulator_get(host->dev, "vmmc_aux");
+                host->vcc_aux = IS_ERR(reg) ? NULL : reg;
+
+                /*
+                * UGLY HACK:  workaround regulator framework bugs.
+                * When the bootloader leaves a supply active, it's
+                * initialized with zero usecount ... and we can't
+                * disable it without first enabling it.  Until the
+                * framework is fixed, we need a workaround like this
+                * (which is safe for MMC, but not in general).
+                */
+                if (regulator_is_enabled(host->vcc) > 0) {
+                        regulator_enable(host->vcc);
+                        regulator_disable(host->vcc);
+                }
+                if (host->vcc_aux) {
+                        if (regulator_is_enabled(reg) > 0) {
+                                regulator_enable(reg);
+                                regulator_disable(reg);
+                        }
+                }
+        }
+
+        return 0;
+
+err:
+        mmc_slot(host).set_power = NULL;
+        mmc_slot(host).set_sleep = NULL;
+        return ret;
+}
+
+static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
+{
+        regulator_put(host->vcc);
+        regulator_put(host->vcc_aux);
+        mmc_slot(host).set_power = NULL;
+        mmc_slot(host).set_sleep = NULL;
+}
+
+static inline int omap_hsmmc_have_reg(void)
+{
+        return 1;
+}
+
+#else
+
+static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
+{
+        return -EINVAL;
+}
+
+static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
+{
+}
+
+static inline int omap_hsmmc_have_reg(void)
+{
+        return 0;
+}
+
+#endif
+
+static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
+{
+        int ret;
+
+        if (gpio_is_valid(pdata->slots[0].switch_pin)) {
+                pdata->suspend = omap_hsmmc_suspend_cdirq;
+                pdata->resume = omap_hsmmc_resume_cdirq;
+                if (pdata->slots[0].cover)
+                        pdata->slots[0].get_cover_state =
+                                        omap_hsmmc_get_cover_state;
+                else
+                        pdata->slots[0].card_detect = omap_hsmmc_card_detect;
+                pdata->slots[0].card_detect_irq =
+                                gpio_to_irq(pdata->slots[0].switch_pin);
+                ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
+                if (ret)
+                        return ret;
+                ret = gpio_direction_input(pdata->slots[0].switch_pin);
+                if (ret)
+                        goto err_free_sp;
+        } else
+                pdata->slots[0].switch_pin = -EINVAL;
+
+        if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
+                pdata->slots[0].get_ro = omap_hsmmc_get_wp;
+                ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
+                if (ret)
+                        goto err_free_cd;
+                ret = gpio_direction_input(pdata->slots[0].gpio_wp);
+                if (ret)
+                        goto err_free_wp;
+        } else
+                pdata->slots[0].gpio_wp = -EINVAL;
+
+        return 0;
+
+err_free_wp:
+        gpio_free(pdata->slots[0].gpio_wp);
+err_free_cd:
+        if (gpio_is_valid(pdata->slots[0].switch_pin))
+err_free_sp:
+                gpio_free(pdata->slots[0].switch_pin);
+        return ret;
+}
+
+static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
+{
+        if (gpio_is_valid(pdata->slots[0].gpio_wp))
+                gpio_free(pdata->slots[0].gpio_wp);
+        if (gpio_is_valid(pdata->slots[0].switch_pin))
+                gpio_free(pdata->slots[0].switch_pin);
+}
+
 /*
  * Stop clock to the card
  */
@@ -835,21 +1173,16 @@ static void omap_hsmmc_detect(struct work_struct *work)
         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 
         if (slot->card_detect)
-                carddetect = slot->card_detect(slot->card_detect_irq);
+                carddetect = slot->card_detect(host->dev, host->slot_id);
         else {
                 omap_hsmmc_protect_card(host);
                 carddetect = -ENOSYS;
         }
 
-        if (carddetect) {
+        if (carddetect)
                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
-        } else {
-                mmc_host_enable(host->mmc);
-                omap_hsmmc_reset_controller_fsm(host, SRD);
-                mmc_host_lazy_disable(host->mmc);
-
+        else
                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
-        }
 }
 
 /*
@@ -1242,7 +1575,7 @@ static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 
         if (!mmc_slot(host).card_detect)
                 return -ENOSYS;
-        return mmc_slot(host).card_detect(mmc_slot(host).card_detect_irq);
+        return mmc_slot(host).card_detect(host->dev, host->slot_id);
 }
 
 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
@@ -1311,7 +1644,7 @@ static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
         if (host->power_mode == MMC_POWER_OFF)
                 return 0;
 
-        return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT);
+        return OMAP_MMC_SLEEP_TIMEOUT;
 }
 
 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
@@ -1347,11 +1680,14 @@ static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
         dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
                 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
 
+        if (mmc_slot(host).no_off)
+                return 0;
+
         if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
             mmc_slot(host).card_detect ||
             (mmc_slot(host).get_cover_state &&
              mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
-                return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT);
+                return OMAP_MMC_OFF_TIMEOUT;
 
         return 0;
 }
@@ -1362,6 +1698,9 @@ static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
         if (!mmc_try_claim_host(host->mmc))
                 return 0;
 
+        if (mmc_slot(host).no_off)
+                return 0;
+
         if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
               mmc_slot(host).card_detect ||
               (mmc_slot(host).get_cover_state &&
@@ -1616,7 +1955,7 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
         struct mmc_host *mmc;
         struct omap_hsmmc_host *host = NULL;
         struct resource *res;
-        int ret = 0, irq;
+        int ret, irq;
 
         if (pdata == NULL) {
                 dev_err(&pdev->dev, "Platform Data is missing\n");
@@ -1638,10 +1977,14 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
         if (res == NULL)
                 return -EBUSY;
 
+        ret = omap_hsmmc_gpio_init(pdata);
+        if (ret)
+                goto err;
+
         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
         if (!mmc) {
                 ret = -ENOMEM;
-                goto err;
+                goto err_alloc;
         }
 
         host            = mmc_priv(mmc);
@@ -1656,7 +1999,7 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
         host->slot_id   = 0;
         host->mapbase   = res->start;
         host->base      = ioremap(host->mapbase, SZ_4K);
-        host->power_mode = -1;
+        host->power_mode = MMC_POWER_OFF;
 
         platform_set_drvdata(pdev, host);
         INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
@@ -1666,6 +2009,13 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
         else
                 mmc->ops        = &omap_hsmmc_ops;
 
+        /*
+         * If regulator_disable can only put vcc_aux to sleep then there is
+         * no off state.
+         */
+        if (mmc_slot(host).vcc_aux_disable_is_sleep)
+                mmc_slot(host).no_off = 1;
+
         mmc->f_min      = 400000;
         mmc->f_max      = 52000000;
 
@@ -1781,7 +2131,6 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
                 goto err_irq;
         }
 
-        /* initialize power supplies, gpios, etc */
         if (pdata->init != NULL) {
                 if (pdata->init(&pdev->dev) != 0) {
                         dev_dbg(mmc_dev(host->mmc),
@@ -1789,6 +2138,14 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
                         goto err_irq_cd_init;
                 }
         }
+
+        if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
+                ret = omap_hsmmc_reg_get(host);
+                if (ret)
+                        goto err_reg;
+                host->use_reg = 1;
+        }
+
         mmc->ocr_avail = mmc_slot(host).ocr_mask;
 
         /* Request IRQ for card detect */
@@ -1823,19 +2180,22 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
                 ret = device_create_file(&mmc->class_dev,
                                         &dev_attr_cover_switch);
                 if (ret < 0)
-                        goto err_cover_switch;
+                        goto err_slot_name;
         }
 
         omap_hsmmc_debugfs(mmc);
 
         return 0;
 
-err_cover_switch:
-        device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
 err_slot_name:
         mmc_remove_host(mmc);
-err_irq_cd:
         free_irq(mmc_slot(host).card_detect_irq, host);
+err_irq_cd:
+        if (host->use_reg)
+                omap_hsmmc_reg_put(host);
+err_reg:
+        if (host->pdata->cleanup)
+                host->pdata->cleanup(&pdev->dev);
 err_irq_cd_init:
         free_irq(host->irq, host);
 err_irq:
@@ -1847,14 +2207,14 @@ err_irq:
                 clk_disable(host->dbclk);
                 clk_put(host->dbclk);
         }
-
 err1:
         iounmap(host->base);
+        platform_set_drvdata(pdev, NULL);
+        mmc_free_host(mmc);
+err_alloc:
+        omap_hsmmc_gpio_free(pdata);
 err:
-        dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
         release_mem_region(res->start, res->end - res->start + 1);
-        if (host)
-                mmc_free_host(mmc);
         return ret;
 }
 
@@ -1866,6 +2226,8 @@ static int omap_hsmmc_remove(struct platform_device *pdev)
         if (host) {
                 mmc_host_enable(host->mmc);
                 mmc_remove_host(host->mmc);
+                if (host->use_reg)
+                        omap_hsmmc_reg_put(host);
                 if (host->pdata->cleanup)
                         host->pdata->cleanup(&pdev->dev);
                 free_irq(host->irq, host);
@@ -1884,6 +2246,7 @@ static int omap_hsmmc_remove(struct platform_device *pdev)
 
                 mmc_free_host(host->mmc);
                 iounmap(host->base);
+                omap_hsmmc_gpio_free(pdev->dev.platform_data);
         }
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index 9fb480bb0e0a..0ed48959b590 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/regulator/consumer.h>
 #include <linux/gpio.h>
+#include <linux/gfp.h>
 
 #include <asm/sizes.h>
 
@@ -43,6 +44,9 @@
 #define NR_SG   1
 #define CLKRT_OFF       (~0)
 
+#define mmc_has_26MHz()         (cpu_is_pxa300() || cpu_is_pxa310() \
+                                || cpu_is_pxa935())
+
 struct pxamci_host {
         struct mmc_host         *mmc;
         spinlock_t              lock;
@@ -457,7 +461,7 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
                         clk_enable(host->clk);
 
                 if (ios->clock == 26000000) {
-                        /* to support 26MHz on pxa300/pxa310 */
+                        /* to support 26MHz */
                         host->clkrt = 7;
                 } else {
                         /* to handle (19.5MHz, 26MHz) */
@@ -608,8 +612,7 @@ static int pxamci_probe(struct platform_device *pdev)
          * Calculate minimum clock rate, rounding up.
          */
         mmc->f_min = (host->clkrate + 63) / 64;
-        mmc->f_max = (cpu_is_pxa300() || cpu_is_pxa310()) ? 26000000
-                                                          : host->clkrate;
+        mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate;
 
         pxamci_init_ocr(host);
 
@@ -618,7 +621,7 @@ static int pxamci_probe(struct platform_device *pdev)
         if (!cpu_is_pxa25x()) {
                 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
                 host->cmdat |= CMDAT_SDIO_INT_EN;
-                if (cpu_is_pxa300() || cpu_is_pxa310())
+                if (mmc_has_26MHz())
                         mmc->caps |= MMC_CAP_MMC_HIGHSPEED |
                                      MMC_CAP_SD_HIGHSPEED;
         }
@@ -826,7 +829,7 @@ static int pxamci_resume(struct device *dev)
         return ret;
 }
 
-static struct dev_pm_ops pxamci_pm_ops = {
+static const struct dev_pm_ops pxamci_pm_ops = {
         .suspend        = pxamci_suspend,
         .resume         = pxamci_resume,
 };
diff --git a/drivers/mmc/host/ricoh_mmc.c b/drivers/mmc/host/ricoh_mmc.c
deleted file mode 100644
index f62790513322..000000000000
--- a/drivers/mmc/host/ricoh_mmc.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- *  ricoh_mmc.c - Dummy driver to disable the Rioch MMC controller.
- *
- *  Copyright (C) 2007 Philip Langdale, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-
-/*
- * This is a conceptually ridiculous driver, but it is required by the way
- * the Ricoh multi-function chips (R5CXXX) work. These chips implement
- * the four main memory card controllers (SD, MMC, MS, xD) and one or both
- * of cardbus or firewire. It happens that they implement SD and MMC
- * support as separate controllers (and PCI functions). The linux SDHCI
- * driver supports MMC cards but the chip detects MMC cards in hardware
- * and directs them to the MMC controller - so the SDHCI driver never sees
- * them. To get around this, we must disable the useless MMC controller.
- * At that point, the SDHCI controller will start seeing them. As a bonus,
- * a detection event occurs immediately, even if the MMC card is already
- * in the reader.
- *
- * It seems to be the case that the relevant PCI registers to deactivate the
- * MMC controller live on PCI function 0, which might be the cardbus controller
- * or the firewire controller, depending on the particular chip in question. As
- * such, it makes what this driver has to do unavoidably ugly. Such is life.
- */
-
-#include <linux/pci.h>
-
-#define DRIVER_NAME "ricoh-mmc"
-
-static const struct pci_device_id pci_ids[] __devinitdata = {
-        {
-                .vendor         = PCI_VENDOR_ID_RICOH,
-                .device         = PCI_DEVICE_ID_RICOH_R5C843,
-                .subvendor      = PCI_ANY_ID,
-                .subdevice      = PCI_ANY_ID,
-        },
-        { /* end: all zeroes */ },
-};
-
-MODULE_DEVICE_TABLE(pci, pci_ids);
-
-static int ricoh_mmc_disable(struct pci_dev *fw_dev)
-{
-        u8 write_enable;
-        u8 write_target;
-        u8 disable;
-
-        if (fw_dev->device == PCI_DEVICE_ID_RICOH_RL5C476) {
-                /* via RL5C476 */
-
-                pci_read_config_byte(fw_dev, 0xB7, &disable);
-                if (disable & 0x02) {
-                        printk(KERN_INFO DRIVER_NAME
-                                ": Controller already disabled. " \
-                                "Nothing to do.\n");
-                        return -ENODEV;
-                }
-
-                pci_read_config_byte(fw_dev, 0x8E, &write_enable);
-                pci_write_config_byte(fw_dev, 0x8E, 0xAA);
-                pci_read_config_byte(fw_dev, 0x8D, &write_target);
-                pci_write_config_byte(fw_dev, 0x8D, 0xB7);
-                pci_write_config_byte(fw_dev, 0xB7, disable | 0x02);
-                pci_write_config_byte(fw_dev, 0x8E, write_enable);
-                pci_write_config_byte(fw_dev, 0x8D, write_target);
-        } else {
-                /* via R5C832 */
-
-                pci_read_config_byte(fw_dev, 0xCB, &disable);
-                if (disable & 0x02) {
-                        printk(KERN_INFO DRIVER_NAME
-                               ": Controller already disabled. " \
-                                "Nothing to do.\n");
-                        return -ENODEV;
-                }
-
-                pci_read_config_byte(fw_dev, 0xCA, &write_enable);
-                pci_write_config_byte(fw_dev, 0xCA, 0x57);
-                pci_write_config_byte(fw_dev, 0xCB, disable | 0x02);
-                pci_write_config_byte(fw_dev, 0xCA, write_enable);
-        }
-
-        printk(KERN_INFO DRIVER_NAME
-               ": Controller is now disabled.\n");
-
-        return 0;
-}
-
-static int ricoh_mmc_enable(struct pci_dev *fw_dev)
-{
-        u8 write_enable;
-        u8 write_target;
-        u8 disable;
-
-        if (fw_dev->device == PCI_DEVICE_ID_RICOH_RL5C476) {
-                /* via RL5C476 */
-
-                pci_read_config_byte(fw_dev, 0x8E, &write_enable);
-                pci_write_config_byte(fw_dev, 0x8E, 0xAA);
-                pci_read_config_byte(fw_dev, 0x8D, &write_target);
-                pci_write_config_byte(fw_dev, 0x8D, 0xB7);
-                pci_read_config_byte(fw_dev, 0xB7, &disable);
-                pci_write_config_byte(fw_dev, 0xB7, disable & ~0x02);
-                pci_write_config_byte(fw_dev, 0x8E, write_enable);
-                pci_write_config_byte(fw_dev, 0x8D, write_target);
-        } else {
-                /* via R5C832 */
-
-                pci_read_config_byte(fw_dev, 0xCA, &write_enable);
-                pci_read_config_byte(fw_dev, 0xCB, &disable);
-                pci_write_config_byte(fw_dev, 0xCA, 0x57);
-                pci_write_config_byte(fw_dev, 0xCB, disable & ~0x02);
-                pci_write_config_byte(fw_dev, 0xCA, write_enable);
-        }
-
-        printk(KERN_INFO DRIVER_NAME
-               ": Controller is now re-enabled.\n");
-
-        return 0;
-}
-
-static int __devinit ricoh_mmc_probe(struct pci_dev *pdev,
-                                     const struct pci_device_id *ent)
-{
-        u8 rev;
-        u8 ctrlfound = 0;
-
-        struct pci_dev *fw_dev = NULL;
-
-        BUG_ON(pdev == NULL);
-        BUG_ON(ent == NULL);
-
-        pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
-
-        printk(KERN_INFO DRIVER_NAME
-                ": Ricoh MMC controller found at %s [%04x:%04x] (rev %x)\n",
-                pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
-                (int)rev);
-
-        while ((fw_dev =
-                pci_get_device(PCI_VENDOR_ID_RICOH,
-                        PCI_DEVICE_ID_RICOH_RL5C476, fw_dev))) {
-                if (PCI_SLOT(pdev->devfn) == PCI_SLOT(fw_dev->devfn) &&
-                    PCI_FUNC(fw_dev->devfn) == 0 &&
-                    pdev->bus == fw_dev->bus) {
-                        if (ricoh_mmc_disable(fw_dev) != 0)
-                                return -ENODEV;
-
-                        pci_set_drvdata(pdev, fw_dev);
-
-                        ++ctrlfound;
-                        break;
-                }
-        }
-
-        fw_dev = NULL;
-
-        while (!ctrlfound &&
-            (fw_dev = pci_get_device(PCI_VENDOR_ID_RICOH,
-                                        PCI_DEVICE_ID_RICOH_R5C832, fw_dev))) {
-                if (PCI_SLOT(pdev->devfn) == PCI_SLOT(fw_dev->devfn) &&
-                    PCI_FUNC(fw_dev->devfn) == 0 &&
-                    pdev->bus == fw_dev->bus) {
-                        if (ricoh_mmc_disable(fw_dev) != 0)
-                                return -ENODEV;
-
-                        pci_set_drvdata(pdev, fw_dev);
-
-                        ++ctrlfound;
-                }
-        }
-
-        if (!ctrlfound) {
-                printk(KERN_WARNING DRIVER_NAME
-                       ": Main Ricoh function not found. Cannot disable controller.\n");
-                return -ENODEV;
-        }
-
-        return 0;
-}
-
-static void __devexit ricoh_mmc_remove(struct pci_dev *pdev)
-{
-        struct pci_dev *fw_dev = NULL;
-
-        fw_dev = pci_get_drvdata(pdev);
-        BUG_ON(fw_dev == NULL);
-
-        ricoh_mmc_enable(fw_dev);
-
-        pci_set_drvdata(pdev, NULL);
-}
-
-static int ricoh_mmc_suspend_late(struct pci_dev *pdev, pm_message_t state)
-{
-        struct pci_dev *fw_dev = NULL;
-
-        fw_dev = pci_get_drvdata(pdev);
-        BUG_ON(fw_dev == NULL);
-
-        printk(KERN_INFO DRIVER_NAME ": Suspending.\n");
-
-        ricoh_mmc_enable(fw_dev);
-
-        return 0;
-}
-
-static int ricoh_mmc_resume_early(struct pci_dev *pdev)
-{
-        struct pci_dev *fw_dev = NULL;
-
-        fw_dev = pci_get_drvdata(pdev);
-        BUG_ON(fw_dev == NULL);
-
-        printk(KERN_INFO DRIVER_NAME ": Resuming.\n");
-
-        ricoh_mmc_disable(fw_dev);
-
-        return 0;
-}
-
-static struct pci_driver ricoh_mmc_driver = {
-        .name =         DRIVER_NAME,
-        .id_table =     pci_ids,
-        .probe =        ricoh_mmc_probe,
-        .remove =       __devexit_p(ricoh_mmc_remove),
-        .suspend_late = ricoh_mmc_suspend_late,
-        .resume_early = ricoh_mmc_resume_early,
-};
-
-/*****************************************************************************\
- *                                                                           *
- * Driver init/exit                                                          *
- *                                                                           *
-\*****************************************************************************/
-
-static int __init ricoh_mmc_drv_init(void)
-{
-        printk(KERN_INFO DRIVER_NAME
-                ": Ricoh MMC Controller disabling driver\n");
-        printk(KERN_INFO DRIVER_NAME ": Copyright(c) Philip Langdale\n");
-
-        return pci_register_driver(&ricoh_mmc_driver);
-}
-
-static void __exit ricoh_mmc_drv_exit(void)
-{
-        pci_unregister_driver(&ricoh_mmc_driver);
-}
-
-module_init(ricoh_mmc_drv_init);
-module_exit(ricoh_mmc_drv_exit);
-
-MODULE_AUTHOR("Philip Langdale <philipl@alumni.utexas.net>");
-MODULE_DESCRIPTION("Ricoh MMC Controller disabling driver");
-MODULE_LICENSE("GPL");
-
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index 99b74a351020..2fdf7689ae6c 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -820,7 +820,7 @@ fail_request:
 static void finalize_request(struct s3cmci_host *host)
 {
         struct mmc_request *mrq = host->mrq;
-        struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
+        struct mmc_command *cmd;
         int debug_as_failure = 0;
 
         if (host->complete_what != COMPLETION_FINALIZE)
@@ -828,6 +828,7 @@ static void finalize_request(struct s3cmci_host *host)
 
         if (!mrq)
                 return;
+        cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 
         if (cmd->data && (cmd->error == 0) &&
             (cmd->data->error == 0)) {
@@ -1178,7 +1179,7 @@ static int s3cmci_card_present(struct mmc_host *mmc)
         struct s3c24xx_mci_pdata *pdata = host->pdata;
         int ret;
 
-        if (pdata->gpio_detect == 0)
+        if (pdata->no_detect)
                 return -ENOSYS;
 
         ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
@@ -1302,10 +1303,8 @@ static int s3cmci_get_ro(struct mmc_host *mmc)
         if (pdata->no_wprotect)
                 return 0;
 
-        ret = s3c2410_gpio_getpin(pdata->gpio_wprotect);
-
-        if (pdata->wprotect_invert)
-                ret = !ret;
+        ret = gpio_get_value(pdata->gpio_wprotect) ? 1 : 0;
+        ret ^= pdata->wprotect_invert;
 
         return ret;
 }
@@ -1360,7 +1359,9 @@ static struct mmc_host_ops s3cmci_ops = {
 
 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
         /* This is currently here to avoid a number of if (host->pdata)
-         * checks. Any zero fields to ensure reaonable defaults are picked. */
+         * checks. Any zero fields to ensure reasonable defaults are picked. */
+         .no_wprotect = 1,
+         .no_detect = 1,
 };
 
 #ifdef CONFIG_CPU_FREQ
@@ -1654,7 +1655,7 @@ static int __devinit s3cmci_probe(struct platform_device *pdev)
                         goto probe_free_irq;
                 }
 
-                host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect);
+                host->irq_cd = gpio_to_irq(host->pdata->gpio_detect);
 
                 if (host->irq_cd >= 0) {
                         if (request_irq(host->irq_cd, s3cmci_irq_cd,
@@ -1892,7 +1893,7 @@ static int s3cmci_resume(struct device *dev)
         return mmc_resume_host(mmc);
 }
 
-static struct dev_pm_ops s3cmci_pm = {
+static const struct dev_pm_ops s3cmci_pm = {
         .suspend        = s3cmci_suspend,
         .resume         = s3cmci_resume,
 };
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of-core.c
index 01ab916c2802..55e33135edb4 100644
--- a/drivers/mmc/host/sdhci-of.c
+++ b/drivers/mmc/host/sdhci-of-core.c
@@ -22,62 +22,37 @@
 #include <linux/of_platform.h>
 #include <linux/mmc/host.h>
 #include <asm/machdep.h>
+#include "sdhci-of.h"
 #include "sdhci.h"
 
-struct sdhci_of_data {
-        unsigned int quirks;
-        struct sdhci_ops ops;
-};
-
-struct sdhci_of_host {
-        unsigned int clock;
-        u16 xfer_mode_shadow;
-};
+#ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
 
 /*
- * Ops and quirks for the Freescale eSDHC controller.
+ * These accessors are designed for big endian hosts doing I/O to
+ * little endian controllers incorporating a 32-bit hardware byte swapper.
  */
 
-#define ESDHC_DMA_SYSCTL        0x40c
-#define ESDHC_DMA_SNOOP         0x00000040
-
-#define ESDHC_SYSTEM_CONTROL    0x2c
-#define ESDHC_CLOCK_MASK        0x0000fff0
-#define ESDHC_PREDIV_SHIFT      8
-#define ESDHC_DIVIDER_SHIFT     4
-#define ESDHC_CLOCK_PEREN       0x00000004
-#define ESDHC_CLOCK_HCKEN       0x00000002
-#define ESDHC_CLOCK_IPGEN       0x00000001
-
-#define ESDHC_HOST_CONTROL_RES  0x05
-
-static u32 esdhc_readl(struct sdhci_host *host, int reg)
+u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg)
 {
         return in_be32(host->ioaddr + reg);
 }
 
-static u16 esdhc_readw(struct sdhci_host *host, int reg)
+u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg)
 {
-        u16 ret;
-
-        if (unlikely(reg == SDHCI_HOST_VERSION))
-                ret = in_be16(host->ioaddr + reg);
-        else
-                ret = in_be16(host->ioaddr + (reg ^ 0x2));
-        return ret;
+        return in_be16(host->ioaddr + (reg ^ 0x2));
 }
 
-static u8 esdhc_readb(struct sdhci_host *host, int reg)
+u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg)
 {
         return in_8(host->ioaddr + (reg ^ 0x3));
 }
 
-static void esdhc_writel(struct sdhci_host *host, u32 val, int reg)
+void sdhci_be32bs_writel(struct sdhci_host *host, u32 val, int reg)
 {
         out_be32(host->ioaddr + reg, val);
 }
 
-static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
+void sdhci_be32bs_writew(struct sdhci_host *host, u16 val, int reg)
 {
         struct sdhci_of_host *of_host = sdhci_priv(host);
         int base = reg & ~0x3;
@@ -92,106 +67,21 @@ static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
                 of_host->xfer_mode_shadow = val;
                 return;
         case SDHCI_COMMAND:
-                esdhc_writel(host, val << 16 | of_host->xfer_mode_shadow,
-                             SDHCI_TRANSFER_MODE);
+                sdhci_be32bs_writel(host, val << 16 | of_host->xfer_mode_shadow,
+                                    SDHCI_TRANSFER_MODE);
                 return;
-        case SDHCI_BLOCK_SIZE:
-                /*
-                 * Two last DMA bits are reserved, and first one is used for
-                 * non-standard blksz of 4096 bytes that we don't support
-                 * yet. So clear the DMA boundary bits.
-                 */
-                val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
-                /* fall through */
         }
         clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
 }
 
-static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
+void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
 {
         int base = reg & ~0x3;
         int shift = (reg & 0x3) * 8;
 
-        /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
-        if (reg == SDHCI_HOST_CONTROL)
-                val &= ~ESDHC_HOST_CONTROL_RES;
-
         clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
 }
-
-static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
-{
-        int pre_div = 2;
-        int div = 1;
-
-        clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
-                  ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
-
-        if (clock == 0)
-                goto out;
-
-        while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
-                pre_div *= 2;
-
-        while (host->max_clk / pre_div / div > clock && div < 16)
-                div++;
-
-        dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
-                clock, host->max_clk / pre_div / div);
-
-        pre_div >>= 1;
-        div--;
-
-        setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
-                  ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
-                  div << ESDHC_DIVIDER_SHIFT | pre_div << ESDHC_PREDIV_SHIFT);
-        mdelay(100);
-out:
-        host->clock = clock;
-}
-
-static int esdhc_enable_dma(struct sdhci_host *host)
-{
-        setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
-        return 0;
-}
-
-static unsigned int esdhc_get_max_clock(struct sdhci_host *host)
-{
-        struct sdhci_of_host *of_host = sdhci_priv(host);
-
-        return of_host->clock;
-}
-
-static unsigned int esdhc_get_min_clock(struct sdhci_host *host)
-{
-        struct sdhci_of_host *of_host = sdhci_priv(host);
-
-        return of_host->clock / 256 / 16;
-}
-
-static struct sdhci_of_data sdhci_esdhc = {
-        .quirks = SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
-                  SDHCI_QUIRK_BROKEN_CARD_DETECTION |
-                  SDHCI_QUIRK_NO_BUSY_IRQ |
-                  SDHCI_QUIRK_NONSTANDARD_CLOCK |
-                  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
-                  SDHCI_QUIRK_PIO_NEEDS_DELAY |
-                  SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |
-                  SDHCI_QUIRK_NO_CARD_NO_RESET,
-        .ops = {
-                .readl = esdhc_readl,
-                .readw = esdhc_readw,
-                .readb = esdhc_readb,
-                .writel = esdhc_writel,
-                .writew = esdhc_writew,
-                .writeb = esdhc_writeb,
-                .set_clock = esdhc_set_clock,
-                .enable_dma = esdhc_enable_dma,
-                .get_max_clock = esdhc_get_max_clock,
-                .get_min_clock = esdhc_get_min_clock,
-        },
-};
+#endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */
 
 #ifdef CONFIG_PM
 
@@ -301,9 +191,14 @@ static int __devexit sdhci_of_remove(struct of_device *ofdev)
 }
 
 static const struct of_device_id sdhci_of_match[] = {
+#ifdef CONFIG_MMC_SDHCI_OF_ESDHC
         { .compatible = "fsl,mpc8379-esdhc", .data = &sdhci_esdhc, },
         { .compatible = "fsl,mpc8536-esdhc", .data = &sdhci_esdhc, },
         { .compatible = "fsl,esdhc", .data = &sdhci_esdhc, },
+#endif
+#ifdef CONFIG_MMC_SDHCI_OF_HLWD
+        { .compatible = "nintendo,hollywood-sdhci", .data = &sdhci_hlwd, },
+#endif
         { .compatible = "generic-sdhci", },
         {},
 };
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
new file mode 100644
index 000000000000..d5b11a17e648
--- /dev/null
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -0,0 +1,143 @@
+/*
+ * Freescale eSDHC controller driver.
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ *
+ * Authors: Xiaobo Xie <X.Xie@freescale.com>
+ *          Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/mmc/host.h>
+#include "sdhci-of.h"
+#include "sdhci.h"
+
+/*
+ * Ops and quirks for the Freescale eSDHC controller.
+ */
+
+#define ESDHC_DMA_SYSCTL        0x40c
+#define ESDHC_DMA_SNOOP         0x00000040
+
+#define ESDHC_SYSTEM_CONTROL    0x2c
+#define ESDHC_CLOCK_MASK        0x0000fff0
+#define ESDHC_PREDIV_SHIFT      8
+#define ESDHC_DIVIDER_SHIFT     4
+#define ESDHC_CLOCK_PEREN       0x00000004
+#define ESDHC_CLOCK_HCKEN       0x00000002
+#define ESDHC_CLOCK_IPGEN       0x00000001
+
+#define ESDHC_HOST_CONTROL_RES  0x05
+
+static u16 esdhc_readw(struct sdhci_host *host, int reg)
+{
+        u16 ret;
+
+        if (unlikely(reg == SDHCI_HOST_VERSION))
+                ret = in_be16(host->ioaddr + reg);
+        else
+                ret = sdhci_be32bs_readw(host, reg);
+        return ret;
+}
+
+static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
+{
+        if (reg == SDHCI_BLOCK_SIZE) {
+                /*
+                 * Two last DMA bits are reserved, and first one is used for
+                 * non-standard blksz of 4096 bytes that we don't support
+                 * yet. So clear the DMA boundary bits.
+                 */
+                val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
+        }
+        sdhci_be32bs_writew(host, val, reg);
+}
+
+static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+        /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
+        if (reg == SDHCI_HOST_CONTROL)
+                val &= ~ESDHC_HOST_CONTROL_RES;
+        sdhci_be32bs_writeb(host, val, reg);
+}
+
+static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+        int pre_div = 2;
+        int div = 1;
+
+        clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
+                  ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
+
+        if (clock == 0)
+                goto out;
+
+        while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
+                pre_div *= 2;
+
+        while (host->max_clk / pre_div / div > clock && div < 16)
+                div++;
+
+        dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
+                clock, host->max_clk / pre_div / div);
+
+        pre_div >>= 1;
+        div--;
+
+        setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
+                  ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
+                  div << ESDHC_DIVIDER_SHIFT | pre_div << ESDHC_PREDIV_SHIFT);
+        mdelay(100);
+out:
+        host->clock = clock;
+}
+
+static int esdhc_enable_dma(struct sdhci_host *host)
+{
+        setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
+        return 0;
+}
+
+static unsigned int esdhc_get_max_clock(struct sdhci_host *host)
+{
+        struct sdhci_of_host *of_host = sdhci_priv(host);
+
+        return of_host->clock;
+}
+
+static unsigned int esdhc_get_min_clock(struct sdhci_host *host)
+{
+        struct sdhci_of_host *of_host = sdhci_priv(host);
+
+        return of_host->clock / 256 / 16;
+}
+
+struct sdhci_of_data sdhci_esdhc = {
+        .quirks = SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
+                  SDHCI_QUIRK_BROKEN_CARD_DETECTION |
+                  SDHCI_QUIRK_NO_BUSY_IRQ |
+                  SDHCI_QUIRK_NONSTANDARD_CLOCK |
+                  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
+                  SDHCI_QUIRK_PIO_NEEDS_DELAY |
+                  SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |
+                  SDHCI_QUIRK_NO_CARD_NO_RESET,
+        .ops = {
+                .readl = sdhci_be32bs_readl,
+                .readw = esdhc_readw,
+                .readb = sdhci_be32bs_readb,
+                .writel = sdhci_be32bs_writel,
+                .writew = esdhc_writew,
+                .writeb = esdhc_writeb,
+                .set_clock = esdhc_set_clock,
+                .enable_dma = esdhc_enable_dma,
+                .get_max_clock = esdhc_get_max_clock,
+                .get_min_clock = esdhc_get_min_clock,
+        },
+};
diff --git a/drivers/mmc/host/sdhci-of-hlwd.c b/drivers/mmc/host/sdhci-of-hlwd.c
new file mode 100644
index 000000000000..35117f3ed757
--- /dev/null
+++ b/drivers/mmc/host/sdhci-of-hlwd.c
@@ -0,0 +1,65 @@
+/*
+ * drivers/mmc/host/sdhci-of-hlwd.c
+ *
+ * Nintendo Wii Secure Digital Host Controller Interface.
+ * Copyright (C) 2009 The GameCube Linux Team
+ * Copyright (C) 2009 Albert Herranz
+ *
+ * Based on sdhci-of-esdhc.c
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ *
+ * Authors: Xiaobo Xie <X.Xie@freescale.com>
+ *          Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#include <linux/delay.h>
+#include <linux/mmc/host.h>
+#include "sdhci-of.h"
+#include "sdhci.h"
+
+/*
+ * Ops and quirks for the Nintendo Wii SDHCI controllers.
+ */
+
+/*
+ * We need a small delay after each write, or things go horribly wrong.
+ */
+#define SDHCI_HLWD_WRITE_DELAY  5 /* usecs */
+
+static void sdhci_hlwd_writel(struct sdhci_host *host, u32 val, int reg)
+{
+        sdhci_be32bs_writel(host, val, reg);
+        udelay(SDHCI_HLWD_WRITE_DELAY);
+}
+
+static void sdhci_hlwd_writew(struct sdhci_host *host, u16 val, int reg)
+{
+        sdhci_be32bs_writew(host, val, reg);
+        udelay(SDHCI_HLWD_WRITE_DELAY);
+}
+
+static void sdhci_hlwd_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+        sdhci_be32bs_writeb(host, val, reg);
+        udelay(SDHCI_HLWD_WRITE_DELAY);
+}
+
+struct sdhci_of_data sdhci_hlwd = {
+        .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
+                  SDHCI_QUIRK_32BIT_DMA_SIZE,
+        .ops = {
+                .readl = sdhci_be32bs_readl,
+                .readw = sdhci_be32bs_readw,
+                .readb = sdhci_be32bs_readb,
+                .writel = sdhci_hlwd_writel,
+                .writew = sdhci_hlwd_writew,
+                .writeb = sdhci_hlwd_writeb,
+        },
+};
diff --git a/drivers/mmc/host/sdhci-of.h b/drivers/mmc/host/sdhci-of.h
new file mode 100644
index 000000000000..ad09ad9915d8
--- /dev/null
+++ b/drivers/mmc/host/sdhci-of.h
@@ -0,0 +1,42 @@
+/*
+ * OpenFirmware bindings for Secure Digital Host Controller Interface.
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ *
+ * Authors: Xiaobo Xie <X.Xie@freescale.com>
+ *          Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#ifndef __SDHCI_OF_H
+#define __SDHCI_OF_H
+
+#include <linux/types.h>
+#include "sdhci.h"
+
+struct sdhci_of_data {
+        unsigned int quirks;
+        struct sdhci_ops ops;
+};
+
+struct sdhci_of_host {
+        unsigned int clock;
+        u16 xfer_mode_shadow;
+};
+
+extern u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg);
+extern u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg);
+extern u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg);
+extern void sdhci_be32bs_writel(struct sdhci_host *host, u32 val, int reg);
+extern void sdhci_be32bs_writew(struct sdhci_host *host, u16 val, int reg);
+extern void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg);
+
+extern struct sdhci_of_data sdhci_esdhc;
+extern struct sdhci_of_data sdhci_hlwd;
+
+#endif /* __SDHCI_OF_H */
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index e0356644d1aa..6701af629c30 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -16,6 +16,7 @@
 #include <linux/highmem.h>
 #include <linux/pci.h>
 #include <linux/dma-mapping.h>
+#include <linux/slab.h>
 
 #include <linux/mmc/host.h>
 
@@ -80,9 +81,6 @@ struct sdhci_pci_chip {
 
 static int ricoh_probe(struct sdhci_pci_chip *chip)
 {
-        if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_IBM)
-                chip->quirks |= SDHCI_QUIRK_CLOCK_BEFORE_RESET;
-
         if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
             chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
                 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
@@ -92,7 +90,9 @@ static int ricoh_probe(struct sdhci_pci_chip *chip)
 
 static const struct sdhci_pci_fixes sdhci_ricoh = {
         .probe          = ricoh_probe,
-        .quirks         = SDHCI_QUIRK_32BIT_DMA_ADDR,
+        .quirks         = SDHCI_QUIRK_32BIT_DMA_ADDR |
+                          SDHCI_QUIRK_FORCE_DMA |
+                          SDHCI_QUIRK_CLOCK_BEFORE_RESET,
 };
 
 static const struct sdhci_pci_fixes sdhci_ene_712 = {
@@ -285,6 +285,73 @@ static const struct sdhci_pci_fixes sdhci_jmicron = {
         .resume         = jmicron_resume,
 };
 
+/* SysKonnect CardBus2SDIO extra registers */
+#define SYSKT_CTRL              0x200
+#define SYSKT_RDFIFO_STAT       0x204
+#define SYSKT_WRFIFO_STAT       0x208
+#define SYSKT_POWER_DATA        0x20c
+#define   SYSKT_POWER_330       0xef
+#define   SYSKT_POWER_300       0xf8
+#define   SYSKT_POWER_184       0xcc
+#define SYSKT_POWER_CMD         0x20d
+#define   SYSKT_POWER_START     (1 << 7)
+#define SYSKT_POWER_STATUS      0x20e
+#define   SYSKT_POWER_STATUS_OK (1 << 0)
+#define SYSKT_BOARD_REV         0x210
+#define SYSKT_CHIP_REV          0x211
+#define SYSKT_CONF_DATA         0x212
+#define   SYSKT_CONF_DATA_1V8   (1 << 2)
+#define   SYSKT_CONF_DATA_2V5   (1 << 1)
+#define   SYSKT_CONF_DATA_3V3   (1 << 0)
+
+static int syskt_probe(struct sdhci_pci_chip *chip)
+{
+        if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
+                chip->pdev->class &= ~0x0000FF;
+                chip->pdev->class |= PCI_SDHCI_IFDMA;
+        }
+        return 0;
+}
+
+static int syskt_probe_slot(struct sdhci_pci_slot *slot)
+{
+        int tm, ps;
+
+        u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
+        u8  chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
+        dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
+                                         "board rev %d.%d, chip rev %d.%d\n",
+                                         board_rev >> 4, board_rev & 0xf,
+                                         chip_rev >> 4,  chip_rev & 0xf);
+        if (chip_rev >= 0x20)
+                slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
+
+        writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
+        writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
+        udelay(50);
+        tm = 10;  /* Wait max 1 ms */
+        do {
+                ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
+                if (ps & SYSKT_POWER_STATUS_OK)
+                        break;
+                udelay(100);
+        } while (--tm);
+        if (!tm) {
+                dev_err(&slot->chip->pdev->dev,
+                        "power regulator never stabilized");
+                writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
+static const struct sdhci_pci_fixes sdhci_syskt = {
+        .quirks         = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
+        .probe          = syskt_probe,
+        .probe_slot     = syskt_probe_slot,
+};
+
 static int via_probe(struct sdhci_pci_chip *chip)
 {
         if (chip->pdev->revision == 0x10)
@@ -363,6 +430,14 @@ static const struct pci_device_id pci_ids[] __devinitdata = {
         },
 
         {
+                .vendor         = PCI_VENDOR_ID_SYSKONNECT,
+                .device         = 0x8000,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_syskt,
+        },
+
+        {
                 .vendor         = PCI_VENDOR_ID_VIA,
                 .device         = 0x95d0,
                 .subvendor      = PCI_ANY_ID,
@@ -426,6 +501,7 @@ static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state)
 {
         struct sdhci_pci_chip *chip;
         struct sdhci_pci_slot *slot;
+        mmc_pm_flag_t pm_flags = 0;
         int i, ret;
 
         chip = pci_get_drvdata(pdev);
@@ -444,6 +520,8 @@ static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state)
                                 sdhci_resume_host(chip->slots[i]->host);
                         return ret;
                 }
+
+                pm_flags |= slot->host->mmc->pm_flags;
         }
 
         if (chip->fixes && chip->fixes->suspend) {
@@ -456,9 +534,15 @@ static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state)
         }
 
         pci_save_state(pdev);
-        pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
-        pci_disable_device(pdev);
-        pci_set_power_state(pdev, pci_choose_state(pdev, state));
+        if (pm_flags & MMC_PM_KEEP_POWER) {
+                if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
+                        pci_enable_wake(pdev, PCI_D3hot, 1);
+                pci_set_power_state(pdev, PCI_D3hot);
+        } else {
+                pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
+                pci_disable_device(pdev);
+                pci_set_power_state(pdev, pci_choose_state(pdev, state));
+        }
 
         return 0;
 }
@@ -578,6 +662,8 @@ static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
                         goto unmap;
         }
 
+        host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
+
         ret = sdhci_add_host(host);
         if (ret)
                 goto remove;
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 50997d2a63e7..2136794c0cfa 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -15,6 +15,7 @@
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index c279fbc4c2e5..9d4fdfa685e5 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -17,6 +17,7 @@
 #include <linux/highmem.h>
 #include <linux/io.h>
 #include <linux/dma-mapping.h>
+#include <linux/slab.h>
 #include <linux/scatterlist.h>
 
 #include <linux/leds.h>
@@ -174,20 +175,31 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 }
 
-static void sdhci_init(struct sdhci_host *host)
+static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
+
+static void sdhci_init(struct sdhci_host *host, int soft)
 {
-        sdhci_reset(host, SDHCI_RESET_ALL);
+        if (soft)
+                sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
+        else
+                sdhci_reset(host, SDHCI_RESET_ALL);
 
         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
+
+        if (soft) {
+                /* force clock reconfiguration */
+                host->clock = 0;
+                sdhci_set_ios(host->mmc, &host->mmc->ios);
+        }
 }
 
 static void sdhci_reinit(struct sdhci_host *host)
 {
-        sdhci_init(host);
+        sdhci_init(host, 0);
         sdhci_enable_card_detection(host);
 }
 
@@ -376,6 +388,20 @@ static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
         local_irq_restore(*flags);
 }
 
+static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
+{
+        __le32 *dataddr = (__le32 __force *)(desc + 4);
+        __le16 *cmdlen = (__le16 __force *)desc;
+
+        /* SDHCI specification says ADMA descriptors should be 4 byte
+         * aligned, so using 16 or 32bit operations should be safe. */
+
+        cmdlen[0] = cpu_to_le16(cmd);
+        cmdlen[1] = cpu_to_le16(len);
+
+        dataddr[0] = cpu_to_le32(addr);
+}
+
 static int sdhci_adma_table_pre(struct sdhci_host *host,
         struct mmc_data *data)
 {
@@ -443,19 +469,11 @@ static int sdhci_adma_table_pre(struct sdhci_host *host,
                                 sdhci_kunmap_atomic(buffer, &flags);
                         }
 
-                        desc[7] = (align_addr >> 24) & 0xff;
-                        desc[6] = (align_addr >> 16) & 0xff;
-                        desc[5] = (align_addr >> 8) & 0xff;
-                        desc[4] = (align_addr >> 0) & 0xff;
+                        /* tran, valid */
+                        sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 
                         BUG_ON(offset > 65536);
 
-                        desc[3] = (offset >> 8) & 0xff;
-                        desc[2] = (offset >> 0) & 0xff;
-
-                        desc[1] = 0x00;
-                        desc[0] = 0x21; /* tran, valid */
-
                         align += 4;
                         align_addr += 4;
 
@@ -465,19 +483,10 @@ static int sdhci_adma_table_pre(struct sdhci_host *host,
                         len -= offset;
                 }
 
-                desc[7] = (addr >> 24) & 0xff;
-                desc[6] = (addr >> 16) & 0xff;
-                desc[5] = (addr >> 8) & 0xff;
-                desc[4] = (addr >> 0) & 0xff;
-
                 BUG_ON(len > 65536);
 
-                desc[3] = (len >> 8) & 0xff;
-                desc[2] = (len >> 0) & 0xff;
-
-                desc[1] = 0x00;
-                desc[0] = 0x21; /* tran, valid */
-
+                /* tran, valid */
+                sdhci_set_adma_desc(desc, addr, len, 0x21);
                 desc += 8;
 
                 /*
@@ -490,16 +499,9 @@ static int sdhci_adma_table_pre(struct sdhci_host *host,
         /*
          * Add a terminating entry.
          */
-        desc[7] = 0;
-        desc[6] = 0;
-        desc[5] = 0;
-        desc[4] = 0;
 
-        desc[3] = 0;
-        desc[2] = 0;
-
-        desc[1] = 0x00;
-        desc[0] = 0x03; /* nop, end, valid */
+        /* nop, end, valid */
+        sdhci_set_adma_desc(desc, 0, 0, 0x3);
 
         /*
          * Resync align buffer as we might have changed it.
@@ -1610,16 +1612,13 @@ int sdhci_resume_host(struct sdhci_host *host)
         if (ret)
                 return ret;
 
-        sdhci_init(host);
+        sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
         mmiowb();
 
         ret = mmc_resume_host(host->mmc);
-        if (ret)
-                return ret;
-
         sdhci_enable_card_detection(host);
 
-        return 0;
+        return ret;
 }
 
 EXPORT_SYMBOL_GPL(sdhci_resume_host);
@@ -1874,7 +1873,7 @@ int sdhci_add_host(struct sdhci_host *host)
         if (ret)
                 goto untasklet;
 
-        sdhci_init(host);
+        sdhci_init(host, 0);
 
 #ifdef CONFIG_MMC_DEBUG
         sdhci_dumpregs(host);
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index ce5f1d73dc04..842f46f94284 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -8,6 +8,8 @@
  * the Free Software Foundation; either version 2 of the License, or (at
  * your option) any later version.
  */
+#ifndef __SDHCI_H
+#define __SDHCI_H
 
 #include <linux/scatterlist.h>
 #include <linux/compiler.h>
@@ -408,3 +410,5 @@ extern void sdhci_remove_host(struct sdhci_host *host, int dead);
 extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
 extern int sdhci_resume_host(struct sdhci_host *host);
 #endif
+
+#endif /* __SDHCI_H */
diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
index 91991b460c45..b2b577f6afd4 100644
--- a/drivers/mmc/host/tmio_mmc.c
+++ b/drivers/mmc/host/tmio_mmc.c
@@ -46,7 +46,9 @@ static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
                 clk |= 0x100;
         }
 
-        sd_config_write8(host, CNF_SD_CLK_MODE, clk >> 22);
+        if (host->set_clk_div)
+                host->set_clk_div(host->pdev, (clk>>22) & 1);
+
         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
 }
 
@@ -321,7 +323,7 @@ static irqreturn_t tmio_mmc_irq(int irq, void *devid)
                 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
                         ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
                                 TMIO_STAT_CARD_REMOVE);
-                        mmc_detect_change(host->mmc, 0);
+                        mmc_detect_change(host->mmc, msecs_to_jiffies(100));
                 }
 
                 /* CRC and other errors */
@@ -427,12 +429,13 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
         /* Power sequence - OFF -> ON -> UP */
         switch (ios->power_mode) {
         case MMC_POWER_OFF: /* power down SD bus */
-                sd_config_write8(host, CNF_PWR_CTL_2, 0x00);
+                if (host->set_pwr)
+                        host->set_pwr(host->pdev, 0);
                 tmio_mmc_clk_stop(host);
                 break;
         case MMC_POWER_ON: /* power up SD bus */
-
-                sd_config_write8(host, CNF_PWR_CTL_2, 0x02);
+                if (host->set_pwr)
+                        host->set_pwr(host->pdev, 1);
                 break;
         case MMC_POWER_UP: /* start bus clock */
                 tmio_mmc_clk_start(host);
@@ -485,21 +488,15 @@ static int tmio_mmc_resume(struct platform_device *dev)
 {
         struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
         struct mmc_host *mmc = platform_get_drvdata(dev);
-        struct tmio_mmc_host *host = mmc_priv(mmc);
         int ret = 0;
 
         /* Tell the MFD core we are ready to be enabled */
-        if (cell->enable) {
-                ret = cell->enable(dev);
+        if (cell->resume) {
+                ret = cell->resume(dev);
                 if (ret)
                         goto out;
         }
 
-        /* Enable the MMC/SD Control registers */
-        sd_config_write16(host, CNF_CMD, SDCREN);
-        sd_config_write32(host, CNF_CTL_BASE,
-                (dev->resource[0].start >> host->bus_shift) & 0xfffe);
-
         mmc_resume_host(mmc);
 
 out:
@@ -514,17 +511,16 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
 {
         struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
         struct tmio_mmc_data *pdata;
-        struct resource *res_ctl, *res_cnf;
+        struct resource *res_ctl;
         struct tmio_mmc_host *host;
         struct mmc_host *mmc;
         int ret = -EINVAL;
 
-        if (dev->num_resources != 3)
+        if (dev->num_resources != 2)
                 goto out;
 
         res_ctl = platform_get_resource(dev, IORESOURCE_MEM, 0);
-        res_cnf = platform_get_resource(dev, IORESOURCE_MEM, 1);
-        if (!res_ctl || !res_cnf)
+        if (!res_ctl)
                 goto out;
 
         pdata = cell->driver_data;
@@ -539,8 +535,12 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
 
         host = mmc_priv(mmc);
         host->mmc = mmc;
+        host->pdev = dev;
         platform_set_drvdata(dev, mmc);
 
+        host->set_pwr = pdata->set_pwr;
+        host->set_clk_div = pdata->set_clk_div;
+
         /* SD control register space size is 0x200, 0x400 for bus_shift=1 */
         host->bus_shift = resource_size(res_ctl) >> 10;
 
@@ -548,12 +548,9 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
         if (!host->ctl)
                 goto host_free;
 
-        host->cnf = ioremap(res_cnf->start, resource_size(res_cnf));
-        if (!host->cnf)
-                goto unmap_ctl;
-
         mmc->ops = &tmio_mmc_ops;
         mmc->caps = MMC_CAP_4_BIT_DATA;
+        mmc->caps |= pdata->capabilities;
         mmc->f_max = pdata->hclk;
         mmc->f_min = mmc->f_max / 512;
         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
@@ -562,23 +559,9 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
         if (cell->enable) {
                 ret = cell->enable(dev);
                 if (ret)
-                        goto unmap_cnf;
+                        goto unmap_ctl;
         }
 
-        /* Enable the MMC/SD Control registers */
-        sd_config_write16(host, CNF_CMD, SDCREN);
-        sd_config_write32(host, CNF_CTL_BASE,
-                (dev->resource[0].start >> host->bus_shift) & 0xfffe);
-
-        /* Disable SD power during suspend */
-        sd_config_write8(host, CNF_PWR_CTL_3, 0x01);
-
-        /* The below is required but why? FIXME */
-        sd_config_write8(host, CNF_STOP_CLK_CTL, 0x1f);
-
-        /* Power down SD bus*/
-        sd_config_write8(host, CNF_PWR_CTL_2, 0x00);
-
         tmio_mmc_clk_stop(host);
         reset(host);
 
@@ -586,14 +569,14 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
         if (ret >= 0)
                 host->irq = ret;
         else
-                goto unmap_cnf;
+                goto cell_disable;
 
         disable_mmc_irqs(host, TMIO_MASK_ALL);
 
         ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED |
-                IRQF_TRIGGER_FALLING, "tmio-mmc", host);
+                IRQF_TRIGGER_FALLING, dev_name(&dev->dev), host);
         if (ret)
-                goto unmap_cnf;
+                goto cell_disable;
 
         mmc_add_host(mmc);
 
@@ -605,8 +588,9 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
 
         return 0;
 
-unmap_cnf:
-        iounmap(host->cnf);
+cell_disable:
+        if (cell->disable)
+                cell->disable(dev);
 unmap_ctl:
         iounmap(host->ctl);
 host_free:
@@ -617,6 +601,7 @@ out:
 
 static int __devexit tmio_mmc_remove(struct platform_device *dev)
 {
+        struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
         struct mmc_host *mmc = platform_get_drvdata(dev);
 
         platform_set_drvdata(dev, NULL);
@@ -625,8 +610,9 @@ static int __devexit tmio_mmc_remove(struct platform_device *dev)
                 struct tmio_mmc_host *host = mmc_priv(mmc);
                 mmc_remove_host(mmc);
                 free_irq(host->irq, host);
+                if (cell->disable)
+                        cell->disable(dev);
                 iounmap(host->ctl);
-                iounmap(host->cnf);
                 mmc_free_host(mmc);
         }
 
diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index 9fa998594974..dafecfbcd91a 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -11,26 +11,6 @@
 
 #include <linux/highmem.h>
 
-#define CNF_CMD     0x04
-#define CNF_CTL_BASE   0x10
-#define CNF_INT_PIN  0x3d
-#define CNF_STOP_CLK_CTL 0x40
-#define CNF_GCLK_CTL 0x41
-#define CNF_SD_CLK_MODE 0x42
-#define CNF_PIN_STATUS 0x44
-#define CNF_PWR_CTL_1 0x48
-#define CNF_PWR_CTL_2 0x49
-#define CNF_PWR_CTL_3 0x4a
-#define CNF_CARD_DETECT_MODE 0x4c
-#define CNF_SD_SLOT 0x50
-#define CNF_EXT_GCLK_CTL_1 0xf0
-#define CNF_EXT_GCLK_CTL_2 0xf1
-#define CNF_EXT_GCLK_CTL_3 0xf9
-#define CNF_SD_LED_EN_1 0xfa
-#define CNF_SD_LED_EN_2 0xfe
-
-#define   SDCREN 0x2   /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
-
 #define CTL_SD_CMD 0x00
 #define CTL_ARG_REG 0x04
 #define CTL_STOP_INTERNAL_ACTION 0x08
@@ -75,10 +55,8 @@
 /* Define some IRQ masks */
 /* This is the mask used at reset by the chip */
 #define TMIO_MASK_ALL           0x837f031d
-#define TMIO_MASK_READOP  (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND | \
-                TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
-#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND | \
-                TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
+#define TMIO_MASK_READOP  (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
+#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
 #define TMIO_MASK_CMD     (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
                 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
 #define TMIO_MASK_IRQ     (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
@@ -110,7 +88,6 @@
 
 
 struct tmio_mmc_host {
-        void __iomem *cnf;
         void __iomem *ctl;
         unsigned long bus_shift;
         struct mmc_command      *cmd;
@@ -119,10 +96,16 @@ struct tmio_mmc_host {
         struct mmc_host         *mmc;
         int                     irq;
 
+        /* Callbacks for clock / power control */
+        void (*set_pwr)(struct platform_device *host, int state);
+        void (*set_clk_div)(struct platform_device *host, int state);
+
         /* pio related stuff */
         struct scatterlist      *sg_ptr;
         unsigned int            sg_len;
         unsigned int            sg_off;
+
+        struct platform_device *pdev;
 };
 
 #include <linux/io.h>
@@ -163,25 +146,6 @@ static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr,
         writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
 }
 
-static inline void sd_config_write8(struct tmio_mmc_host *host, int addr,
-                u8 val)
-{
-        writeb(val, host->cnf + (addr << host->bus_shift));
-}
-
-static inline void sd_config_write16(struct tmio_mmc_host *host, int addr,
-                u16 val)
-{
-        writew(val, host->cnf + (addr << host->bus_shift));
-}
-
-static inline void sd_config_write32(struct tmio_mmc_host *host, int addr,
-                u32 val)
-{
-        writew(val, host->cnf + (addr << host->bus_shift));
-        writew(val >> 16, host->cnf + ((addr + 2) << host->bus_shift));
-}
-
 #include <linux/scatterlist.h>
 #include <linux/blkdev.h>
 
diff --git a/drivers/mmc/host/wbsd.c b/drivers/mmc/host/wbsd.c
index 89bf8cd25cac..69efe01eece8 100644
--- a/drivers/mmc/host/wbsd.c
+++ b/drivers/mmc/host/wbsd.c
@@ -34,6 +34,7 @@
 #include <linux/highmem.h>
 #include <linux/mmc/host.h>
 #include <linux/scatterlist.h>
+#include <linux/slab.h>
 
 #include <asm/io.h>
 #include <asm/dma.h>