Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

1 files changed, 87 insertions, 135 deletions

diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index d316bc79b636..745c42fa41ed 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -1,6 +1,8 @@
 /*
  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
  *
+ * Header file for Host Controller registers and I/O accessors.
+ *
  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -8,19 +10,22 @@
  * the Free Software Foundation; either version 2 of the License, or (at
  * your option) any later version.
  */
-#ifndef __SDHCI_H
-#define __SDHCI_H
+#ifndef __SDHCI_HW_H
+#define __SDHCI_HW_H
 
 #include <linux/scatterlist.h>
 #include <linux/compiler.h>
 #include <linux/types.h>
 #include <linux/io.h>
 
+#include <linux/mmc/sdhci.h>
+
 /*
  * Controller registers
  */
 
 #define SDHCI_DMA_ADDRESS       0x00
+#define SDHCI_ARGUMENT2         SDHCI_DMA_ADDRESS
 
 #define SDHCI_BLOCK_SIZE        0x04
 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
@@ -32,7 +37,8 @@
 #define SDHCI_TRANSFER_MODE     0x0C
 #define  SDHCI_TRNS_DMA         0x01
 #define  SDHCI_TRNS_BLK_CNT_EN  0x02
-#define  SDHCI_TRNS_ACMD12      0x04
+#define  SDHCI_TRNS_AUTO_CMD12  0x04
+#define  SDHCI_TRNS_AUTO_CMD23  0x08
 #define  SDHCI_TRNS_READ        0x10
 #define  SDHCI_TRNS_MULTI       0x20
 
@@ -41,6 +47,7 @@
 #define  SDHCI_CMD_CRC          0x08
 #define  SDHCI_CMD_INDEX        0x10
 #define  SDHCI_CMD_DATA         0x20
+#define  SDHCI_CMD_ABORTCMD     0xC0
 
 #define  SDHCI_CMD_RESP_NONE    0x00
 #define  SDHCI_CMD_RESP_LONG    0x01
@@ -48,6 +55,7 @@
 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
 
 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
+#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
 
 #define SDHCI_RESPONSE          0x10
 
@@ -62,8 +70,10 @@
 #define  SDHCI_DATA_AVAILABLE   0x00000800
 #define  SDHCI_CARD_PRESENT     0x00010000
 #define  SDHCI_WRITE_PROTECT    0x00080000
+#define  SDHCI_DATA_LVL_MASK    0x00F00000
+#define   SDHCI_DATA_LVL_SHIFT  20
 
-#define SDHCI_HOST_CONTROL      0x28
+#define SDHCI_HOST_CONTROL      0x28
 #define  SDHCI_CTRL_LED         0x01
 #define  SDHCI_CTRL_4BITBUS     0x02
 #define  SDHCI_CTRL_HISPD       0x04
@@ -72,7 +82,7 @@
 #define   SDHCI_CTRL_ADMA1      0x08
 #define   SDHCI_CTRL_ADMA32     0x10
 #define   SDHCI_CTRL_ADMA64     0x18
-#define  SDHCI_CTRL_8BITBUS     0x20
+#define   SDHCI_CTRL_8BITBUS    0x20
 
 #define SDHCI_POWER_CONTROL     0x29
 #define  SDHCI_POWER_ON         0x01
@@ -83,9 +93,17 @@
 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
 
 #define SDHCI_WAKE_UP_CONTROL   0x2B
+#define  SDHCI_WAKE_ON_INT      0x01
+#define  SDHCI_WAKE_ON_INSERT   0x02
+#define  SDHCI_WAKE_ON_REMOVE   0x04
 
 #define SDHCI_CLOCK_CONTROL     0x2C
 #define  SDHCI_DIVIDER_SHIFT    8
+#define  SDHCI_DIVIDER_HI_SHIFT 6
+#define  SDHCI_DIV_MASK 0xFF
+#define  SDHCI_DIV_MASK_LEN     8
+#define  SDHCI_DIV_HI_MASK      0x300
+#define  SDHCI_PROG_CLOCK_MODE  0x0020
 #define  SDHCI_CLOCK_CARD_EN    0x0004
 #define  SDHCI_CLOCK_INT_STABLE 0x0002
 #define  SDHCI_CLOCK_INT_EN     0x0001
@@ -133,16 +151,33 @@
 
 #define SDHCI_ACMD12_ERR        0x3C
 
-/* 3E-3F reserved */
+#define SDHCI_HOST_CONTROL2             0x3E
+#define  SDHCI_CTRL_UHS_MASK            0x0007
+#define   SDHCI_CTRL_UHS_SDR12          0x0000
+#define   SDHCI_CTRL_UHS_SDR25          0x0001
+#define   SDHCI_CTRL_UHS_SDR50          0x0002
+#define   SDHCI_CTRL_UHS_SDR104         0x0003
+#define   SDHCI_CTRL_UHS_DDR50          0x0004
+#define  SDHCI_CTRL_VDD_180             0x0008
+#define  SDHCI_CTRL_DRV_TYPE_MASK       0x0030
+#define   SDHCI_CTRL_DRV_TYPE_B         0x0000
+#define   SDHCI_CTRL_DRV_TYPE_A         0x0010
+#define   SDHCI_CTRL_DRV_TYPE_C         0x0020
+#define   SDHCI_CTRL_DRV_TYPE_D         0x0030
+#define  SDHCI_CTRL_EXEC_TUNING         0x0040
+#define  SDHCI_CTRL_TUNED_CLK           0x0080
+#define  SDHCI_CTRL_PRESET_VAL_ENABLE   0x8000
 
 #define SDHCI_CAPABILITIES      0x40
 #define  SDHCI_TIMEOUT_CLK_MASK 0x0000003F
 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
 #define  SDHCI_CLOCK_BASE_MASK  0x00003F00
+#define  SDHCI_CLOCK_V3_BASE_MASK       0x0000FF00
 #define  SDHCI_CLOCK_BASE_SHIFT 8
 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
 #define  SDHCI_MAX_BLOCK_SHIFT  16
+#define  SDHCI_CAN_DO_8BIT      0x00040000
 #define  SDHCI_CAN_DO_ADMA2     0x00080000
 #define  SDHCI_CAN_DO_ADMA1     0x00100000
 #define  SDHCI_CAN_DO_HISPD     0x00200000
@@ -152,9 +187,30 @@
 #define  SDHCI_CAN_VDD_180      0x04000000
 #define  SDHCI_CAN_64BIT        0x10000000
 
-/* 44-47 reserved for more caps */
-
-#define SDHCI_MAX_CURRENT       0x48
+#define  SDHCI_SUPPORT_SDR50    0x00000001
+#define  SDHCI_SUPPORT_SDR104   0x00000002
+#define  SDHCI_SUPPORT_DDR50    0x00000004
+#define  SDHCI_DRIVER_TYPE_A    0x00000010
+#define  SDHCI_DRIVER_TYPE_C    0x00000020
+#define  SDHCI_DRIVER_TYPE_D    0x00000040
+#define  SDHCI_RETUNING_TIMER_COUNT_MASK        0x00000F00
+#define  SDHCI_RETUNING_TIMER_COUNT_SHIFT       8
+#define  SDHCI_USE_SDR50_TUNING                 0x00002000
+#define  SDHCI_RETUNING_MODE_MASK               0x0000C000
+#define  SDHCI_RETUNING_MODE_SHIFT              14
+#define  SDHCI_CLOCK_MUL_MASK   0x00FF0000
+#define  SDHCI_CLOCK_MUL_SHIFT  16
+
+#define SDHCI_CAPABILITIES_1    0x44
+
+#define SDHCI_MAX_CURRENT               0x48
+#define  SDHCI_MAX_CURRENT_330_MASK     0x0000FF
+#define  SDHCI_MAX_CURRENT_330_SHIFT    0
+#define  SDHCI_MAX_CURRENT_300_MASK     0x00FF00
+#define  SDHCI_MAX_CURRENT_300_SHIFT    8
+#define  SDHCI_MAX_CURRENT_180_MASK     0xFF0000
+#define  SDHCI_MAX_CURRENT_180_SHIFT    16
+#define   SDHCI_MAX_CURRENT_MULTIPLIER  4
 
 /* 4C-4F reserved for more max current */
 
@@ -178,134 +234,20 @@
 #define  SDHCI_SPEC_VER_SHIFT   0
 #define   SDHCI_SPEC_100        0
 #define   SDHCI_SPEC_200        1
+#define   SDHCI_SPEC_300        2
 
-struct sdhci_ops;
-
-struct sdhci_host {
-        /* Data set by hardware interface driver */
-        const char              *hw_name;       /* Hardware bus name */
-
-        unsigned int            quirks;         /* Deviations from spec. */
-
-/* Controller doesn't honor resets unless we touch the clock register */
-#define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
-/* Controller has bad caps bits, but really supports DMA */
-#define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
-/* Controller doesn't like to be reset when there is no card inserted. */
-#define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
-/* Controller doesn't like clearing the power reg before a change */
-#define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
-/* Controller has flaky internal state so reset it on each ios change */
-#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1<<4)
-/* Controller has an unusable DMA engine */
-#define SDHCI_QUIRK_BROKEN_DMA                          (1<<5)
-/* Controller has an unusable ADMA engine */
-#define SDHCI_QUIRK_BROKEN_ADMA                         (1<<6)
-/* Controller can only DMA from 32-bit aligned addresses */
-#define SDHCI_QUIRK_32BIT_DMA_ADDR                      (1<<7)
-/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
-#define SDHCI_QUIRK_32BIT_DMA_SIZE                      (1<<8)
-/* Controller can only ADMA chunks that are a multiple of 32 bits */
-#define SDHCI_QUIRK_32BIT_ADMA_SIZE                     (1<<9)
-/* Controller needs to be reset after each request to stay stable */
-#define SDHCI_QUIRK_RESET_AFTER_REQUEST                 (1<<10)
-/* Controller needs voltage and power writes to happen separately */
-#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER             (1<<11)
-/* Controller provides an incorrect timeout value for transfers */
-#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL                  (1<<12)
-/* Controller has an issue with buffer bits for small transfers */
-#define SDHCI_QUIRK_BROKEN_SMALL_PIO                    (1<<13)
-/* Controller does not provide transfer-complete interrupt when not busy */
-#define SDHCI_QUIRK_NO_BUSY_IRQ                         (1<<14)
-/* Controller has unreliable card detection */
-#define SDHCI_QUIRK_BROKEN_CARD_DETECTION               (1<<15)
-/* Controller reports inverted write-protect state */
-#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT              (1<<16)
-/* Controller has nonstandard clock management */
-#define SDHCI_QUIRK_NONSTANDARD_CLOCK                   (1<<17)
-/* Controller does not like fast PIO transfers */
-#define SDHCI_QUIRK_PIO_NEEDS_DELAY                     (1<<18)
-/* Controller losing signal/interrupt enable states after reset */
-#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET            (1<<19)
-/* Controller has to be forced to use block size of 2048 bytes */
-#define SDHCI_QUIRK_FORCE_BLK_SZ_2048                   (1<<20)
-/* Controller cannot do multi-block transfers */
-#define SDHCI_QUIRK_NO_MULTIBLOCK                       (1<<21)
-/* Controller can only handle 1-bit data transfers */
-#define SDHCI_QUIRK_FORCE_1_BIT_DATA                    (1<<22)
-/* Controller needs 10ms delay between applying power and clock */
-#define SDHCI_QUIRK_DELAY_AFTER_POWER                   (1<<23)
-/* Controller uses SDCLK instead of TMCLK for data timeouts */
-#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK             (1<<24)
-/* Controller reports wrong base clock capability */
-#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN               (1<<25)
-/* Controller cannot support End Attribute in NOP ADMA descriptor */
-#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC               (1<<26)
-/* Controller is missing device caps. Use caps provided by host */
-#define SDHCI_QUIRK_MISSING_CAPS                        (1<<27)
-/* Controller uses Auto CMD12 command to stop the transfer */
-#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12              (1<<28)
-/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
-#define SDHCI_QUIRK_NO_HISPD_BIT                        (1<<29)
-
-        int                     irq;            /* Device IRQ */
-        void __iomem *          ioaddr;         /* Mapped address */
-
-        const struct sdhci_ops  *ops;           /* Low level hw interface */
-
-        struct regulator        *vmmc;          /* Power regulator */
-
-        /* Internal data */
-        struct mmc_host         *mmc;           /* MMC structure */
-        u64                     dma_mask;       /* custom DMA mask */
-
-#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
-        struct led_classdev     led;            /* LED control */
-        char   led_name[32];
-#endif
-
-        spinlock_t              lock;           /* Mutex */
-
-        int                     flags;          /* Host attributes */
-#define SDHCI_USE_SDMA          (1<<0)          /* Host is SDMA capable */
-#define SDHCI_USE_ADMA          (1<<1)          /* Host is ADMA capable */
-#define SDHCI_REQ_USE_DMA       (1<<2)          /* Use DMA for this req. */
-#define SDHCI_DEVICE_DEAD       (1<<3)          /* Device unresponsive */
-
-        unsigned int            version;        /* SDHCI spec. version */
-
-        unsigned int            max_clk;        /* Max possible freq (MHz) */
-        unsigned int            timeout_clk;    /* Timeout freq (KHz) */
-
-        unsigned int            clock;          /* Current clock (MHz) */
-        u8                      pwr;            /* Current voltage */
-
-        struct mmc_request      *mrq;           /* Current request */
-        struct mmc_command      *cmd;           /* Current command */
-        struct mmc_data         *data;          /* Current data request */
-        unsigned int            data_early:1;   /* Data finished before cmd */
-
-        struct sg_mapping_iter  sg_miter;       /* SG state for PIO */
-        unsigned int            blocks;         /* remaining PIO blocks */
-
-        int                     sg_count;       /* Mapped sg entries */
-
-        u8                      *adma_desc;     /* ADMA descriptor table */
-        u8                      *align_buffer;  /* Bounce buffer */
-
-        dma_addr_t              adma_addr;      /* Mapped ADMA descr. table */
-        dma_addr_t              align_addr;     /* Mapped bounce buffer */
-
-        struct tasklet_struct   card_tasklet;   /* Tasklet structures */
-        struct tasklet_struct   finish_tasklet;
-
-        struct timer_list       timer;          /* Timer for timeouts */
-
-        unsigned int            caps;           /* Alternative capabilities */
+/*
+ * End of controller registers.
+ */
 
-        unsigned long           private[0] ____cacheline_aligned;
-};
+#define SDHCI_MAX_DIV_SPEC_200  256
+#define SDHCI_MAX_DIV_SPEC_300  2046
 
+/*
+ * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
+ */
+#define SDHCI_DEFAULT_BOUNDARY_SIZE  (512 * 1024)
+#define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
 
 struct sdhci_ops {
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
@@ -323,6 +265,15 @@ struct sdhci_ops {
         unsigned int    (*get_max_clock)(struct sdhci_host *host);
         unsigned int    (*get_min_clock)(struct sdhci_host *host);
         unsigned int    (*get_timeout_clock)(struct sdhci_host *host);
+        int             (*platform_8bit_width)(struct sdhci_host *host,
+                                               int width);
+        void (*platform_send_init_74_clocks)(struct sdhci_host *host,
+                                             u8 power_mode);
+        unsigned int    (*get_ro)(struct sdhci_host *host);
+        void    (*platform_reset_enter)(struct sdhci_host *host, u8 mask);
+        void    (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
+        int     (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
+
 };
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
@@ -425,6 +376,7 @@ extern void sdhci_remove_host(struct sdhci_host *host, int dead);
 #ifdef CONFIG_PM
 extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
 extern int sdhci_resume_host(struct sdhci_host *host);
+extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
 #endif
 
-#endif /* __SDHCI_H */
+#endif /* __SDHCI_HW_H */