Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

1 files changed, 913 insertions, 103 deletions

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 401527d273b5..58d5436ff649 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -23,6 +23,7 @@
 
 #include <linux/leds.h>
 
+#include <linux/mmc/mmc.h>
 #include <linux/mmc/host.h>
 
 #include "sdhci.h"
@@ -37,17 +38,21 @@
 #define SDHCI_USE_LEDS_CLASS
 #endif
 
+#define MAX_TUNING_LOOP 40
+
 static unsigned int debug_quirks = 0;
 
-static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
 static void sdhci_finish_data(struct sdhci_host *);
 
 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
 static void sdhci_finish_command(struct sdhci_host *);
+static int sdhci_execute_tuning(struct mmc_host *mmc);
+static void sdhci_tuning_timer(unsigned long data);
 
 static void sdhci_dumpregs(struct sdhci_host *host)
 {
-        printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
+        printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
+                mmc_hostname(host->mmc));
 
         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
@@ -76,9 +81,14 @@ static void sdhci_dumpregs(struct sdhci_host *host)
         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
                 sdhci_readw(host, SDHCI_ACMD12_ERR),
                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
-        printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
+        printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
                 sdhci_readl(host, SDHCI_CAPABILITIES),
+                sdhci_readl(host, SDHCI_CAPABILITIES_1));
+        printk(KERN_DEBUG DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
+                sdhci_readw(host, SDHCI_COMMAND),
                 sdhci_readl(host, SDHCI_MAX_CURRENT));
+        printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
+                sdhci_readw(host, SDHCI_HOST_CONTROL2));
 
         if (host->flags & SDHCI_USE_ADMA)
                 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
@@ -152,6 +162,9 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 
+        if (host->ops->platform_reset_enter)
+                host->ops->platform_reset_enter(host, mask);
+
         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 
         if (mask & SDHCI_RESET_ALL)
@@ -172,6 +185,9 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
                 mdelay(1);
         }
 
+        if (host->ops->platform_reset_exit)
+                host->ops->platform_reset_exit(host, mask);
+
         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 }
@@ -586,9 +602,10 @@ static void sdhci_adma_table_post(struct sdhci_host *host,
                 data->sg_len, direction);
 }
 
-static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
+static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 {
         u8 count;
+        struct mmc_data *data = cmd->data;
         unsigned target_timeout, current_timeout;
 
         /*
@@ -600,9 +617,16 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
                 return 0xE;
 
+        /* Unspecified timeout, assume max */
+        if (!data && !cmd->cmd_timeout_ms)
+                return 0xE;
+
         /* timeout in us */
-        target_timeout = data->timeout_ns / 1000 +
-                data->timeout_clks / host->clock;
+        if (!data)
+                target_timeout = cmd->cmd_timeout_ms * 1000;
+        else
+                target_timeout = data->timeout_ns / 1000 +
+                        data->timeout_clks / host->clock;
 
         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
                 host->timeout_clk = host->clock / 1000;
@@ -617,6 +641,7 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
          *     =>
          *     (1) / (2) > 2^6
          */
+        BUG_ON(!host->timeout_clk);
         count = 0;
         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
         while (current_timeout < target_timeout) {
@@ -627,8 +652,8 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
         }
 
         if (count >= 0xF) {
-                printk(KERN_WARNING "%s: Too large timeout requested!\n",
-                        mmc_hostname(host->mmc));
+                printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
+                       mmc_hostname(host->mmc), cmd->opcode);
                 count = 0xE;
         }
 
@@ -646,15 +671,21 @@ static void sdhci_set_transfer_irqs(struct sdhci_host *host)
                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 }
 
-static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
+static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 {
         u8 count;
         u8 ctrl;
+        struct mmc_data *data = cmd->data;
         int ret;
 
         WARN_ON(host->data);
 
-        if (data == NULL)
+        if (data || (cmd->flags & MMC_RSP_BUSY)) {
+                count = sdhci_calc_timeout(host, cmd);
+                sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
+        }
+
+        if (!data)
                 return;
 
         /* Sanity checks */
@@ -664,9 +695,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 
         host->data = data;
         host->data_early = 0;
-
-        count = sdhci_calc_timeout(host, data);
-        sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
+        host->data->bytes_xfered = 0;
 
         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
                 host->flags |= SDHCI_REQ_USE_DMA;
@@ -802,15 +831,17 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 
         sdhci_set_transfer_irqs(host);
 
-        /* We do not handle DMA boundaries, so set it to max (512 KiB) */
-        sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
+        /* Set the DMA boundary value and block size */
+        sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
+                data->blksz), SDHCI_BLOCK_SIZE);
         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 }
 
 static void sdhci_set_transfer_mode(struct sdhci_host *host,
-        struct mmc_data *data)
+        struct mmc_command *cmd)
 {
         u16 mode;
+        struct mmc_data *data = cmd->data;
 
         if (data == NULL)
                 return;
@@ -818,12 +849,20 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
         WARN_ON(!host->data);
 
         mode = SDHCI_TRNS_BLK_CNT_EN;
-        if (data->blocks > 1) {
-                if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
-                        mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
-                else
-                        mode |= SDHCI_TRNS_MULTI;
+        if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
+                mode |= SDHCI_TRNS_MULTI;
+                /*
+                 * If we are sending CMD23, CMD12 never gets sent
+                 * on successful completion (so no Auto-CMD12).
+                 */
+                if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
+                        mode |= SDHCI_TRNS_AUTO_CMD12;
+                else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
+                        mode |= SDHCI_TRNS_AUTO_CMD23;
+                        sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
+                }
         }
+
         if (data->flags & MMC_DATA_READ)
                 mode |= SDHCI_TRNS_READ;
         if (host->flags & SDHCI_REQ_USE_DMA)
@@ -863,7 +902,15 @@ static void sdhci_finish_data(struct sdhci_host *host)
         else
                 data->bytes_xfered = data->blksz * data->blocks;
 
-        if (data->stop) {
+        /*
+         * Need to send CMD12 if -
+         * a) open-ended multiblock transfer (no CMD23)
+         * b) error in multiblock transfer
+         */
+        if (data->stop &&
+            (data->error ||
+             !host->mrq->sbc)) {
+
                 /*
                  * The controller needs a reset of internal state machines
                  * upon error conditions.
@@ -915,11 +962,11 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 
         host->cmd = cmd;
 
-        sdhci_prepare_data(host, cmd->data);
+        sdhci_prepare_data(host, cmd);
 
         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 
-        sdhci_set_transfer_mode(host, cmd->data);
+        sdhci_set_transfer_mode(host, cmd);
 
         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
                 printk(KERN_ERR "%s: Unsupported response type!\n",
@@ -942,7 +989,9 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
                 flags |= SDHCI_CMD_CRC;
         if (cmd->flags & MMC_RSP_OPCODE)
                 flags |= SDHCI_CMD_INDEX;
-        if (cmd->data)
+
+        /* CMD19 is special in that the Data Present Select should be set */
+        if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
                 flags |= SDHCI_CMD_DATA;
 
         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
@@ -972,19 +1021,27 @@ static void sdhci_finish_command(struct sdhci_host *host)
 
         host->cmd->error = 0;
 
-        if (host->data && host->data_early)
-                sdhci_finish_data(host);
+        /* Finished CMD23, now send actual command. */
+        if (host->cmd == host->mrq->sbc) {
+                host->cmd = NULL;
+                sdhci_send_command(host, host->mrq->cmd);
+        } else {
 
-        if (!host->cmd->data)
-                tasklet_schedule(&host->finish_tasklet);
+                /* Processed actual command. */
+                if (host->data && host->data_early)
+                        sdhci_finish_data(host);
 
-        host->cmd = NULL;
+                if (!host->cmd->data)
+                        tasklet_schedule(&host->finish_tasklet);
+
+                host->cmd = NULL;
+        }
 }
 
 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 {
-        int div;
-        u16 clk;
+        int div = 0; /* Initialized for compiler warning */
+        u16 clk = 0;
         unsigned long timeout;
 
         if (clock == host->clock)
@@ -1001,13 +1058,59 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
         if (clock == 0)
                 goto out;
 
-        for (div = 1;div < 256;div *= 2) {
-                if ((host->max_clk / div) <= clock)
-                        break;
+        if (host->version >= SDHCI_SPEC_300) {
+                /*
+                 * Check if the Host Controller supports Programmable Clock
+                 * Mode.
+                 */
+                if (host->clk_mul) {
+                        u16 ctrl;
+
+                        /*
+                         * We need to figure out whether the Host Driver needs
+                         * to select Programmable Clock Mode, or the value can
+                         * be set automatically by the Host Controller based on
+                         * the Preset Value registers.
+                         */
+                        ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+                        if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
+                                for (div = 1; div <= 1024; div++) {
+                                        if (((host->max_clk * host->clk_mul) /
+                                              div) <= clock)
+                                                break;
+                                }
+                                /*
+                                 * Set Programmable Clock Mode in the Clock
+                                 * Control register.
+                                 */
+                                clk = SDHCI_PROG_CLOCK_MODE;
+                                div--;
+                        }
+                } else {
+                        /* Version 3.00 divisors must be a multiple of 2. */
+                        if (host->max_clk <= clock)
+                                div = 1;
+                        else {
+                                for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
+                                     div += 2) {
+                                        if ((host->max_clk / div) <= clock)
+                                                break;
+                                }
+                        }
+                        div >>= 1;
+                }
+        } else {
+                /* Version 2.00 divisors must be a power of 2. */
+                for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
+                        if ((host->max_clk / div) <= clock)
+                                break;
+                }
+                div >>= 1;
         }
-        div >>= 1;
 
-        clk = div << SDHCI_DIVIDER_SHIFT;
+        clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
+        clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
+                << SDHCI_DIVIDER_HI_SHIFT;
         clk |= SDHCI_CLOCK_INT_EN;
         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 
@@ -1034,11 +1137,9 @@ out:
 
 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 {
-        u8 pwr;
+        u8 pwr = 0;
 
-        if (power == (unsigned short)-1)
-                pwr = 0;
-        else {
+        if (power != (unsigned short)-1) {
                 switch (1 << power) {
                 case MMC_VDD_165_195:
                         pwr = SDHCI_POWER_180;
@@ -1113,7 +1214,12 @@ static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 #ifndef SDHCI_USE_LEDS_CLASS
         sdhci_activate_led(host);
 #endif
-        if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
+
+        /*
+         * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
+         * requests if Auto-CMD12 is enabled.
+         */
+        if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
                 if (mrq->stop) {
                         mrq->data->stop = NULL;
                         mrq->stop = NULL;
@@ -1132,8 +1238,30 @@ static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
                 host->mrq->cmd->error = -ENOMEDIUM;
                 tasklet_schedule(&host->finish_tasklet);
-        } else
-                sdhci_send_command(host, mrq->cmd);
+        } else {
+                u32 present_state;
+
+                present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
+                /*
+                 * Check if the re-tuning timer has already expired and there
+                 * is no on-going data transfer. If so, we need to execute
+                 * tuning procedure before sending command.
+                 */
+                if ((host->flags & SDHCI_NEEDS_RETUNING) &&
+                    !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
+                        spin_unlock_irqrestore(&host->lock, flags);
+                        sdhci_execute_tuning(mmc);
+                        spin_lock_irqsave(&host->lock, flags);
+
+                        /* Restore original mmc_request structure */
+                        host->mrq = mrq;
+                }
+
+                if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
+                        sdhci_send_command(host, mrq->sbc);
+                else
+                        sdhci_send_command(host, mrq->cmd);
+        }
 
         mmiowb();
         spin_unlock_irqrestore(&host->lock, flags);
@@ -1168,25 +1296,120 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
         else
                 sdhci_set_power(host, ios->vdd);
 
-        ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+        if (host->ops->platform_send_init_74_clocks)
+                host->ops->platform_send_init_74_clocks(host, ios->power_mode);
 
-        if (ios->bus_width == MMC_BUS_WIDTH_8)
-                ctrl |= SDHCI_CTRL_8BITBUS;
-        else
-                ctrl &= ~SDHCI_CTRL_8BITBUS;
+        /*
+         * If your platform has 8-bit width support but is not a v3 controller,
+         * or if it requires special setup code, you should implement that in
+         * platform_8bit_width().
+         */
+        if (host->ops->platform_8bit_width)
+                host->ops->platform_8bit_width(host, ios->bus_width);
+        else {
+                ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+                if (ios->bus_width == MMC_BUS_WIDTH_8) {
+                        ctrl &= ~SDHCI_CTRL_4BITBUS;
+                        if (host->version >= SDHCI_SPEC_300)
+                                ctrl |= SDHCI_CTRL_8BITBUS;
+                } else {
+                        if (host->version >= SDHCI_SPEC_300)
+                                ctrl &= ~SDHCI_CTRL_8BITBUS;
+                        if (ios->bus_width == MMC_BUS_WIDTH_4)
+                                ctrl |= SDHCI_CTRL_4BITBUS;
+                        else
+                                ctrl &= ~SDHCI_CTRL_4BITBUS;
+                }
+                sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+        }
 
-        if (ios->bus_width == MMC_BUS_WIDTH_4)
-                ctrl |= SDHCI_CTRL_4BITBUS;
-        else
-                ctrl &= ~SDHCI_CTRL_4BITBUS;
+        ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 
-        if (ios->timing == MMC_TIMING_SD_HS &&
-            !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
+        if ((ios->timing == MMC_TIMING_SD_HS ||
+             ios->timing == MMC_TIMING_MMC_HS)
+            && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
                 ctrl |= SDHCI_CTRL_HISPD;
         else
                 ctrl &= ~SDHCI_CTRL_HISPD;
 
-        sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+        if (host->version >= SDHCI_SPEC_300) {
+                u16 clk, ctrl_2;
+                unsigned int clock;
+
+                /* In case of UHS-I modes, set High Speed Enable */
+                if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
+                    (ios->timing == MMC_TIMING_UHS_SDR104) ||
+                    (ios->timing == MMC_TIMING_UHS_DDR50) ||
+                    (ios->timing == MMC_TIMING_UHS_SDR25) ||
+                    (ios->timing == MMC_TIMING_UHS_SDR12))
+                        ctrl |= SDHCI_CTRL_HISPD;
+
+                ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+                if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
+                        sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+                        /*
+                         * We only need to set Driver Strength if the
+                         * preset value enable is not set.
+                         */
+                        ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
+                        if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
+                                ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
+                        else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
+                                ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
+
+                        sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+                } else {
+                        /*
+                         * According to SDHC Spec v3.00, if the Preset Value
+                         * Enable in the Host Control 2 register is set, we
+                         * need to reset SD Clock Enable before changing High
+                         * Speed Enable to avoid generating clock gliches.
+                         */
+
+                        /* Reset SD Clock Enable */
+                        clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+                        clk &= ~SDHCI_CLOCK_CARD_EN;
+                        sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+                        sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+                        /* Re-enable SD Clock */
+                        clock = host->clock;
+                        host->clock = 0;
+                        sdhci_set_clock(host, clock);
+                }
+
+
+                /* Reset SD Clock Enable */
+                clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+                clk &= ~SDHCI_CLOCK_CARD_EN;
+                sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+                if (host->ops->set_uhs_signaling)
+                        host->ops->set_uhs_signaling(host, ios->timing);
+                else {
+                        ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+                        /* Select Bus Speed Mode for host */
+                        ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+                        if (ios->timing == MMC_TIMING_UHS_SDR12)
+                                ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+                        else if (ios->timing == MMC_TIMING_UHS_SDR25)
+                                ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+                        else if (ios->timing == MMC_TIMING_UHS_SDR50)
+                                ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
+                        else if (ios->timing == MMC_TIMING_UHS_SDR104)
+                                ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
+                        else if (ios->timing == MMC_TIMING_UHS_DDR50)
+                                ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
+                        sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+                }
+
+                /* Re-enable SD Clock */
+                clock = host->clock;
+                host->clock = 0;
+                sdhci_set_clock(host, clock);
+        } else
+                sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 
         /*
          * Some (ENE) controllers go apeshit on some ios operation,
@@ -1201,26 +1424,49 @@ out:
         spin_unlock_irqrestore(&host->lock, flags);
 }
 
-static int sdhci_get_ro(struct mmc_host *mmc)
+static int check_ro(struct sdhci_host *host)
 {
-        struct sdhci_host *host;
         unsigned long flags;
-        int present;
-
-        host = mmc_priv(mmc);
+        int is_readonly;
 
         spin_lock_irqsave(&host->lock, flags);
 
         if (host->flags & SDHCI_DEVICE_DEAD)
-                present = 0;
+                is_readonly = 0;
+        else if (host->ops->get_ro)
+                is_readonly = host->ops->get_ro(host);
         else
-                present = sdhci_readl(host, SDHCI_PRESENT_STATE);
+                is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
+                                & SDHCI_WRITE_PROTECT);
 
         spin_unlock_irqrestore(&host->lock, flags);
 
-        if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
-                return !!(present & SDHCI_WRITE_PROTECT);
-        return !(present & SDHCI_WRITE_PROTECT);
+        /* This quirk needs to be replaced by a callback-function later */
+        return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
+                !is_readonly : is_readonly;
+}
+
+#define SAMPLE_COUNT    5
+
+static int sdhci_get_ro(struct mmc_host *mmc)
+{
+        struct sdhci_host *host;
+        int i, ro_count;
+
+        host = mmc_priv(mmc);
+
+        if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
+                return check_ro(host);
+
+        ro_count = 0;
+        for (i = 0; i < SAMPLE_COUNT; i++) {
+                if (check_ro(host)) {
+                        if (++ro_count > SAMPLE_COUNT / 2)
+                                return 1;
+                }
+                msleep(30);
+        }
+        return 0;
 }
 
 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
@@ -1245,11 +1491,322 @@ out:
         spin_unlock_irqrestore(&host->lock, flags);
 }
 
+static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+        struct mmc_ios *ios)
+{
+        struct sdhci_host *host;
+        u8 pwr;
+        u16 clk, ctrl;
+        u32 present_state;
+
+        host = mmc_priv(mmc);
+
+        /*
+         * Signal Voltage Switching is only applicable for Host Controllers
+         * v3.00 and above.
+         */
+        if (host->version < SDHCI_SPEC_300)
+                return 0;
+
+        /*
+         * We first check whether the request is to set signalling voltage
+         * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
+         */
+        ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+        if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
+                /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
+                ctrl &= ~SDHCI_CTRL_VDD_180;
+                sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+                /* Wait for 5ms */
+                usleep_range(5000, 5500);
+
+                /* 3.3V regulator output should be stable within 5 ms */
+                ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+                if (!(ctrl & SDHCI_CTRL_VDD_180))
+                        return 0;
+                else {
+                        printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
+                                "signalling voltage failed\n");
+                        return -EIO;
+                }
+        } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
+                  (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
+                /* Stop SDCLK */
+                clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+                clk &= ~SDHCI_CLOCK_CARD_EN;
+                sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+                /* Check whether DAT[3:0] is 0000 */
+                present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
+                if (!((present_state & SDHCI_DATA_LVL_MASK) >>
+                       SDHCI_DATA_LVL_SHIFT)) {
+                        /*
+                         * Enable 1.8V Signal Enable in the Host Control2
+                         * register
+                         */
+                        ctrl |= SDHCI_CTRL_VDD_180;
+                        sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+                        /* Wait for 5ms */
+                        usleep_range(5000, 5500);
+
+                        ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+                        if (ctrl & SDHCI_CTRL_VDD_180) {
+                                /* Provide SDCLK again and wait for 1ms*/
+                                clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+                                clk |= SDHCI_CLOCK_CARD_EN;
+                                sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+                                usleep_range(1000, 1500);
+
+                                /*
+                                 * If DAT[3:0] level is 1111b, then the card
+                                 * was successfully switched to 1.8V signaling.
+                                 */
+                                present_state = sdhci_readl(host,
+                                                        SDHCI_PRESENT_STATE);
+                                if ((present_state & SDHCI_DATA_LVL_MASK) ==
+                                     SDHCI_DATA_LVL_MASK)
+                                        return 0;
+                        }
+                }
+
+                /*
+                 * If we are here, that means the switch to 1.8V signaling
+                 * failed. We power cycle the card, and retry initialization
+                 * sequence by setting S18R to 0.
+                 */
+                pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
+                pwr &= ~SDHCI_POWER_ON;
+                sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
+
+                /* Wait for 1ms as per the spec */
+                usleep_range(1000, 1500);
+                pwr |= SDHCI_POWER_ON;
+                sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
+
+                printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
+                        "voltage failed, retrying with S18R set to 0\n");
+                return -EAGAIN;
+        } else
+                /* No signal voltage switch required */
+                return 0;
+}
+
+static int sdhci_execute_tuning(struct mmc_host *mmc)
+{
+        struct sdhci_host *host;
+        u16 ctrl;
+        u32 ier;
+        int tuning_loop_counter = MAX_TUNING_LOOP;
+        unsigned long timeout;
+        int err = 0;
+
+        host = mmc_priv(mmc);
+
+        disable_irq(host->irq);
+        spin_lock(&host->lock);
+
+        ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+        /*
+         * Host Controller needs tuning only in case of SDR104 mode
+         * and for SDR50 mode when Use Tuning for SDR50 is set in
+         * Capabilities register.
+         */
+        if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
+            (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
+            (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
+                ctrl |= SDHCI_CTRL_EXEC_TUNING;
+        else {
+                spin_unlock(&host->lock);
+                enable_irq(host->irq);
+                return 0;
+        }
+
+        sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+        /*
+         * As per the Host Controller spec v3.00, tuning command
+         * generates Buffer Read Ready interrupt, so enable that.
+         *
+         * Note: The spec clearly says that when tuning sequence
+         * is being performed, the controller does not generate
+         * interrupts other than Buffer Read Ready interrupt. But
+         * to make sure we don't hit a controller bug, we _only_
+         * enable Buffer Read Ready interrupt here.
+         */
+        ier = sdhci_readl(host, SDHCI_INT_ENABLE);
+        sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
+
+        /*
+         * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
+         * of loops reaches 40 times or a timeout of 150ms occurs.
+         */
+        timeout = 150;
+        do {
+                struct mmc_command cmd = {0};
+                struct mmc_request mrq = {0};
+
+                if (!tuning_loop_counter && !timeout)
+                        break;
+
+                cmd.opcode = MMC_SEND_TUNING_BLOCK;
+                cmd.arg = 0;
+                cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
+                cmd.retries = 0;
+                cmd.data = NULL;
+                cmd.error = 0;
+
+                mrq.cmd = &cmd;
+                host->mrq = &mrq;
+
+                /*
+                 * In response to CMD19, the card sends 64 bytes of tuning
+                 * block to the Host Controller. So we set the block size
+                 * to 64 here.
+                 */
+                sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
+
+                /*
+                 * The tuning block is sent by the card to the host controller.
+                 * So we set the TRNS_READ bit in the Transfer Mode register.
+                 * This also takes care of setting DMA Enable and Multi Block
+                 * Select in the same register to 0.
+                 */
+                sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
+
+                sdhci_send_command(host, &cmd);
+
+                host->cmd = NULL;
+                host->mrq = NULL;
+
+                spin_unlock(&host->lock);
+                enable_irq(host->irq);
+
+                /* Wait for Buffer Read Ready interrupt */
+                wait_event_interruptible_timeout(host->buf_ready_int,
+                                        (host->tuning_done == 1),
+                                        msecs_to_jiffies(50));
+                disable_irq(host->irq);
+                spin_lock(&host->lock);
+
+                if (!host->tuning_done) {
+                        printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
+                                "Buffer Read Ready interrupt during tuning "
+                                "procedure, falling back to fixed sampling "
+                                "clock\n");
+                        ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+                        ctrl &= ~SDHCI_CTRL_TUNED_CLK;
+                        ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
+                        sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+                        err = -EIO;
+                        goto out;
+                }
+
+                host->tuning_done = 0;
+
+                ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+                tuning_loop_counter--;
+                timeout--;
+                mdelay(1);
+        } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
+
+        /*
+         * The Host Driver has exhausted the maximum number of loops allowed,
+         * so use fixed sampling frequency.
+         */
+        if (!tuning_loop_counter || !timeout) {
+                ctrl &= ~SDHCI_CTRL_TUNED_CLK;
+                sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+        } else {
+                if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
+                        printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
+                                " failed, falling back to fixed sampling"
+                                " clock\n");
+                        err = -EIO;
+                }
+        }
+
+out:
+        /*
+         * If this is the very first time we are here, we start the retuning
+         * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
+         * flag won't be set, we check this condition before actually starting
+         * the timer.
+         */
+        if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
+            (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
+                mod_timer(&host->tuning_timer, jiffies +
+                        host->tuning_count * HZ);
+                /* Tuning mode 1 limits the maximum data length to 4MB */
+                mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
+        } else {
+                host->flags &= ~SDHCI_NEEDS_RETUNING;
+                /* Reload the new initial value for timer */
+                if (host->tuning_mode == SDHCI_TUNING_MODE_1)
+                        mod_timer(&host->tuning_timer, jiffies +
+                                host->tuning_count * HZ);
+        }
+
+        /*
+         * In case tuning fails, host controllers which support re-tuning can
+         * try tuning again at a later time, when the re-tuning timer expires.
+         * So for these controllers, we return 0. Since there might be other
+         * controllers who do not have this capability, we return error for
+         * them.
+         */
+        if (err && host->tuning_count &&
+            host->tuning_mode == SDHCI_TUNING_MODE_1)
+                err = 0;
+
+        sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
+        spin_unlock(&host->lock);
+        enable_irq(host->irq);
+
+        return err;
+}
+
+static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
+{
+        struct sdhci_host *host;
+        u16 ctrl;
+        unsigned long flags;
+
+        host = mmc_priv(mmc);
+
+        /* Host Controller v3.00 defines preset value registers */
+        if (host->version < SDHCI_SPEC_300)
+                return;
+
+        spin_lock_irqsave(&host->lock, flags);
+
+        ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+        /*
+         * We only enable or disable Preset Value if they are not already
+         * enabled or disabled respectively. Otherwise, we bail out.
+         */
+        if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
+                ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
+                sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+        } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
+                ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
+                sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+        }
+
+        spin_unlock_irqrestore(&host->lock, flags);
+}
+
 static const struct mmc_host_ops sdhci_ops = {
         .request        = sdhci_request,
         .set_ios        = sdhci_set_ios,
         .get_ro         = sdhci_get_ro,
         .enable_sdio_irq = sdhci_enable_sdio_irq,
+        .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
+        .execute_tuning                 = sdhci_execute_tuning,
+        .enable_preset_value            = sdhci_enable_preset_value,
 };
 
 /*****************************************************************************\
@@ -1295,10 +1852,20 @@ static void sdhci_tasklet_finish(unsigned long param)
 
         host = (struct sdhci_host*)param;
 
+        /*
+         * If this tasklet gets rescheduled while running, it will
+         * be run again afterwards but without any active request.
+         */
+        if (!host->mrq)
+                return;
+
         spin_lock_irqsave(&host->lock, flags);
 
         del_timer(&host->timer);
 
+        if (host->version >= SDHCI_SPEC_300)
+                del_timer(&host->tuning_timer);
+
         mrq = host->mrq;
 
         /*
@@ -1306,7 +1873,7 @@ static void sdhci_tasklet_finish(unsigned long param)
          * upon error conditions.
          */
         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
-                (mrq->cmd->error ||
+            ((mrq->cmd && mrq->cmd->error) ||
                  (mrq->data && (mrq->data->error ||
                   (mrq->data->stop && mrq->data->stop->error))) ||
                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
@@ -1372,6 +1939,20 @@ static void sdhci_timeout_timer(unsigned long data)
         spin_unlock_irqrestore(&host->lock, flags);
 }
 
+static void sdhci_tuning_timer(unsigned long data)
+{
+        struct sdhci_host *host;
+        unsigned long flags;
+
+        host = (struct sdhci_host *)data;
+
+        spin_lock_irqsave(&host->lock, flags);
+
+        host->flags |= SDHCI_NEEDS_RETUNING;
+
+        spin_unlock_irqrestore(&host->lock, flags);
+}
+
 /*****************************************************************************\
  *                                                                           *
  * Interrupt handling                                                        *
@@ -1427,7 +2008,7 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
                 sdhci_finish_command(host);
 }
 
-#ifdef DEBUG
+#ifdef CONFIG_MMC_DEBUG
 static void sdhci_show_adma_error(struct sdhci_host *host)
 {
         const char *name = mmc_hostname(host->mmc);
@@ -1460,6 +2041,16 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
 {
         BUG_ON(intmask == 0);
 
+        /* CMD19 generates _only_ Buffer Read Ready interrupt */
+        if (intmask & SDHCI_INT_DATA_AVAIL) {
+                if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
+                    MMC_SEND_TUNING_BLOCK) {
+                        host->tuning_done = 1;
+                        wake_up(&host->buf_ready_int);
+                        return;
+                }
+        }
+
         if (!host->data) {
                 /*
                  * The "data complete" interrupt is also used to
@@ -1483,7 +2074,11 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
 
         if (intmask & SDHCI_INT_DATA_TIMEOUT)
                 host->data->error = -ETIMEDOUT;
-        else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
+        else if (intmask & SDHCI_INT_DATA_END_BIT)
+                host->data->error = -EILSEQ;
+        else if ((intmask & SDHCI_INT_DATA_CRC) &&
+                SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
+                        != MMC_BUS_TEST_R)
                 host->data->error = -EILSEQ;
         else if (intmask & SDHCI_INT_ADMA_ERROR) {
                 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
@@ -1501,10 +2096,28 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
                  * We currently don't do anything fancy with DMA
                  * boundaries, but as we can't disable the feature
                  * we need to at least restart the transfer.
+                 *
+                 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
+                 * should return a valid address to continue from, but as
+                 * some controllers are faulty, don't trust them.
                  */
-                if (intmask & SDHCI_INT_DMA_END)
-                        sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
-                                SDHCI_DMA_ADDRESS);
+                if (intmask & SDHCI_INT_DMA_END) {
+                        u32 dmastart, dmanow;
+                        dmastart = sg_dma_address(host->data->sg);
+                        dmanow = dmastart + host->data->bytes_xfered;
+                        /*
+                         * Force update to the next DMA block boundary.
+                         */
+                        dmanow = (dmanow &
+                                ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
+                                SDHCI_DEFAULT_BOUNDARY_SIZE;
+                        host->data->bytes_xfered = dmanow - dmastart;
+                        DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
+                                " next 0x%08x\n",
+                                mmc_hostname(host->mmc), dmastart,
+                                host->data->bytes_xfered, dmanow);
+                        sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
+                }
 
                 if (intmask & SDHCI_INT_DATA_END) {
                         if (host->cmd) {
@@ -1614,6 +2227,14 @@ int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
 
         sdhci_disable_card_detection(host);
 
+        /* Disable tuning since we are suspending */
+        if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
+            host->tuning_mode == SDHCI_TUNING_MODE_1) {
+                host->flags &= ~SDHCI_NEEDS_RETUNING;
+                mod_timer(&host->tuning_timer, jiffies +
+                        host->tuning_count * HZ);
+        }
+
         ret = mmc_suspend_host(host->mmc);
         if (ret)
                 return ret;
@@ -1655,11 +2276,26 @@ int sdhci_resume_host(struct sdhci_host *host)
         ret = mmc_resume_host(host->mmc);
         sdhci_enable_card_detection(host);
 
+        /* Set the re-tuning expiration flag */
+        if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
+            (host->tuning_mode == SDHCI_TUNING_MODE_1))
+                host->flags |= SDHCI_NEEDS_RETUNING;
+
         return ret;
 }
 
 EXPORT_SYMBOL_GPL(sdhci_resume_host);
 
+void sdhci_enable_irq_wakeups(struct sdhci_host *host)
+{
+        u8 val;
+        val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
+        val |= SDHCI_WAKE_ON_INT;
+        sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
+}
+
+EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
+
 #endif /* CONFIG_PM */
 
 /*****************************************************************************\
@@ -1691,7 +2327,9 @@ EXPORT_SYMBOL_GPL(sdhci_alloc_host);
 int sdhci_add_host(struct sdhci_host *host)
 {
         struct mmc_host *mmc;
-        unsigned int caps;
+        u32 caps[2];
+        u32 max_current_caps;
+        unsigned int ocr_avail;
         int ret;
 
         WARN_ON(host == NULL);
@@ -1708,18 +2346,21 @@ int sdhci_add_host(struct sdhci_host *host)
         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
         host->version = (host->version & SDHCI_SPEC_VER_MASK)
                                 >> SDHCI_SPEC_VER_SHIFT;
-        if (host->version > SDHCI_SPEC_200) {
+        if (host->version > SDHCI_SPEC_300) {
                 printk(KERN_ERR "%s: Unknown controller version (%d). "
                         "You may experience problems.\n", mmc_hostname(mmc),
                         host->version);
         }
 
-        caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
+        caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
                 sdhci_readl(host, SDHCI_CAPABILITIES);
 
+        caps[1] = (host->version >= SDHCI_SPEC_300) ?
+                sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
+
         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
                 host->flags |= SDHCI_USE_SDMA;
-        else if (!(caps & SDHCI_CAN_DO_SDMA))
+        else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
                 DBG("Controller doesn't have SDMA capability\n");
         else
                 host->flags |= SDHCI_USE_SDMA;
@@ -1730,7 +2371,8 @@ int sdhci_add_host(struct sdhci_host *host)
                 host->flags &= ~SDHCI_USE_SDMA;
         }
 
-        if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
+        if ((host->version >= SDHCI_SPEC_200) &&
+                (caps[0] & SDHCI_CAN_DO_ADMA2))
                 host->flags |= SDHCI_USE_ADMA;
 
         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
@@ -1779,8 +2421,13 @@ int sdhci_add_host(struct sdhci_host *host)
                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
         }
 
-        host->max_clk =
-                (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+        if (host->version >= SDHCI_SPEC_300)
+                host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
+                        >> SDHCI_CLOCK_BASE_SHIFT;
+        else
+                host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
+                        >> SDHCI_CLOCK_BASE_SHIFT;
+
         host->max_clk *= 1000000;
         if (host->max_clk == 0 || host->quirks &
                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
@@ -1794,7 +2441,7 @@ int sdhci_add_host(struct sdhci_host *host)
         }
 
         host->timeout_clk =
-                (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
+                (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
         if (host->timeout_clk == 0) {
                 if (host->ops->get_timeout_clock) {
                         host->timeout_clk = host->ops->get_timeout_clock(host);
@@ -1806,36 +2453,185 @@ int sdhci_add_host(struct sdhci_host *host)
                         return -ENODEV;
                 }
         }
-        if (caps & SDHCI_TIMEOUT_CLK_UNIT)
+        if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
                 host->timeout_clk *= 1000;
 
         /*
+         * In case of Host Controller v3.00, find out whether clock
+         * multiplier is supported.
+         */
+        host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
+                        SDHCI_CLOCK_MUL_SHIFT;
+
+        /*
+         * In case the value in Clock Multiplier is 0, then programmable
+         * clock mode is not supported, otherwise the actual clock
+         * multiplier is one more than the value of Clock Multiplier
+         * in the Capabilities Register.
+         */
+        if (host->clk_mul)
+                host->clk_mul += 1;
+
+        /*
          * Set host parameters.
          */
         mmc->ops = &sdhci_ops;
+        mmc->f_max = host->max_clk;
         if (host->ops->get_min_clock)
                 mmc->f_min = host->ops->get_min_clock(host);
-        else
-                mmc->f_min = host->max_clk / 256;
-        mmc->f_max = host->max_clk;
-        mmc->caps |= MMC_CAP_SDIO_IRQ;
+        else if (host->version >= SDHCI_SPEC_300) {
+                if (host->clk_mul) {
+                        mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
+                        mmc->f_max = host->max_clk * host->clk_mul;
+                } else
+                        mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
+        } else
+                mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
+
+        mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
+
+        if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
+                host->flags |= SDHCI_AUTO_CMD12;
+
+        /* Auto-CMD23 stuff only works in ADMA or PIO. */
+        if ((host->version >= SDHCI_SPEC_300) &&
+            ((host->flags & SDHCI_USE_ADMA) ||
+             !(host->flags & SDHCI_USE_SDMA))) {
+                host->flags |= SDHCI_AUTO_CMD23;
+                DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
+        } else {
+                DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
+        }
 
+        /*
+         * A controller may support 8-bit width, but the board itself
+         * might not have the pins brought out.  Boards that support
+         * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
+         * their platform code before calling sdhci_add_host(), and we
+         * won't assume 8-bit width for hosts without that CAP.
+         */
         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
                 mmc->caps |= MMC_CAP_4_BIT_DATA;
 
-        if (caps & SDHCI_CAN_DO_HISPD)
-                mmc->caps |= MMC_CAP_SD_HIGHSPEED;
+        if (caps[0] & SDHCI_CAN_DO_HISPD)
+                mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
 
-        if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
+        if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
+            mmc_card_is_removable(mmc))
                 mmc->caps |= MMC_CAP_NEEDS_POLL;
 
-        mmc->ocr_avail = 0;
-        if (caps & SDHCI_CAN_VDD_330)
-                mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
-        if (caps & SDHCI_CAN_VDD_300)
-                mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
-        if (caps & SDHCI_CAN_VDD_180)
-                mmc->ocr_avail |= MMC_VDD_165_195;
+        /* UHS-I mode(s) supported by the host controller. */
+        if (host->version >= SDHCI_SPEC_300)
+                mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
+
+        /* SDR104 supports also implies SDR50 support */
+        if (caps[1] & SDHCI_SUPPORT_SDR104)
+                mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
+        else if (caps[1] & SDHCI_SUPPORT_SDR50)
+                mmc->caps |= MMC_CAP_UHS_SDR50;
+
+        if (caps[1] & SDHCI_SUPPORT_DDR50)
+                mmc->caps |= MMC_CAP_UHS_DDR50;
+
+        /* Does the host needs tuning for SDR50? */
+        if (caps[1] & SDHCI_USE_SDR50_TUNING)
+                host->flags |= SDHCI_SDR50_NEEDS_TUNING;
+
+        /* Driver Type(s) (A, C, D) supported by the host */
+        if (caps[1] & SDHCI_DRIVER_TYPE_A)
+                mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
+        if (caps[1] & SDHCI_DRIVER_TYPE_C)
+                mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
+        if (caps[1] & SDHCI_DRIVER_TYPE_D)
+                mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
+
+        /* Initial value for re-tuning timer count */
+        host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
+                              SDHCI_RETUNING_TIMER_COUNT_SHIFT;
+
+        /*
+         * In case Re-tuning Timer is not disabled, the actual value of
+         * re-tuning timer will be 2 ^ (n - 1).
+         */
+        if (host->tuning_count)
+                host->tuning_count = 1 << (host->tuning_count - 1);
+
+        /* Re-tuning mode supported by the Host Controller */
+        host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
+                             SDHCI_RETUNING_MODE_SHIFT;
+
+        ocr_avail = 0;
+        /*
+         * According to SD Host Controller spec v3.00, if the Host System
+         * can afford more than 150mA, Host Driver should set XPC to 1. Also
+         * the value is meaningful only if Voltage Support in the Capabilities
+         * register is set. The actual current value is 4 times the register
+         * value.
+         */
+        max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
+
+        if (caps[0] & SDHCI_CAN_VDD_330) {
+                int max_current_330;
+
+                ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
+
+                max_current_330 = ((max_current_caps &
+                                   SDHCI_MAX_CURRENT_330_MASK) >>
+                                   SDHCI_MAX_CURRENT_330_SHIFT) *
+                                   SDHCI_MAX_CURRENT_MULTIPLIER;
+
+                if (max_current_330 > 150)
+                        mmc->caps |= MMC_CAP_SET_XPC_330;
+        }
+        if (caps[0] & SDHCI_CAN_VDD_300) {
+                int max_current_300;
+
+                ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
+
+                max_current_300 = ((max_current_caps &
+                                   SDHCI_MAX_CURRENT_300_MASK) >>
+                                   SDHCI_MAX_CURRENT_300_SHIFT) *
+                                   SDHCI_MAX_CURRENT_MULTIPLIER;
+
+                if (max_current_300 > 150)
+                        mmc->caps |= MMC_CAP_SET_XPC_300;
+        }
+        if (caps[0] & SDHCI_CAN_VDD_180) {
+                int max_current_180;
+
+                ocr_avail |= MMC_VDD_165_195;
+
+                max_current_180 = ((max_current_caps &
+                                   SDHCI_MAX_CURRENT_180_MASK) >>
+                                   SDHCI_MAX_CURRENT_180_SHIFT) *
+                                   SDHCI_MAX_CURRENT_MULTIPLIER;
+
+                if (max_current_180 > 150)
+                        mmc->caps |= MMC_CAP_SET_XPC_180;
+
+                /* Maximum current capabilities of the host at 1.8V */
+                if (max_current_180 >= 800)
+                        mmc->caps |= MMC_CAP_MAX_CURRENT_800;
+                else if (max_current_180 >= 600)
+                        mmc->caps |= MMC_CAP_MAX_CURRENT_600;
+                else if (max_current_180 >= 400)
+                        mmc->caps |= MMC_CAP_MAX_CURRENT_400;
+                else
+                        mmc->caps |= MMC_CAP_MAX_CURRENT_200;
+        }
+
+        mmc->ocr_avail = ocr_avail;
+        mmc->ocr_avail_sdio = ocr_avail;
+        if (host->ocr_avail_sdio)
+                mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
+        mmc->ocr_avail_sd = ocr_avail;
+        if (host->ocr_avail_sd)
+                mmc->ocr_avail_sd &= host->ocr_avail_sd;
+        else /* normal SD controllers don't support 1.8V */
+                mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
+        mmc->ocr_avail_mmc = ocr_avail;
+        if (host->ocr_avail_mmc)
+                mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
 
         if (mmc->ocr_avail == 0) {
                 printk(KERN_ERR "%s: Hardware doesn't report any "
@@ -1850,12 +2646,11 @@ int sdhci_add_host(struct sdhci_host *host)
          * can do scatter/gather or not.
          */
         if (host->flags & SDHCI_USE_ADMA)
-                mmc->max_hw_segs = 128;
+                mmc->max_segs = 128;
         else if (host->flags & SDHCI_USE_SDMA)
-                mmc->max_hw_segs = 1;
+                mmc->max_segs = 1;
         else /* PIO */
-                mmc->max_hw_segs = 128;
-        mmc->max_phys_segs = 128;
+                mmc->max_segs = 128;
 
         /*
          * Maximum number of sectors in one transfer. Limited by DMA boundary
@@ -1868,10 +2663,14 @@ int sdhci_add_host(struct sdhci_host *host)
          * of bytes. When doing hardware scatter/gather, each entry cannot
          * be larger than 64 KiB though.
          */
-        if (host->flags & SDHCI_USE_ADMA)
-                mmc->max_seg_size = 65536;
-        else
+        if (host->flags & SDHCI_USE_ADMA) {
+                if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
+                        mmc->max_seg_size = 65535;
+                else
+                        mmc->max_seg_size = 65536;
+        } else {
                 mmc->max_seg_size = mmc->max_req_size;
+        }
 
         /*
          * Maximum block size. This varies from controller to controller and
@@ -1880,7 +2679,7 @@ int sdhci_add_host(struct sdhci_host *host)
         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
                 mmc->max_blk_size = 2;
         } else {
-                mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
+                mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
                                 SDHCI_MAX_BLOCK_SHIFT;
                 if (mmc->max_blk_size >= 3) {
                         printk(KERN_WARNING "%s: Invalid maximum block size, "
@@ -1906,6 +2705,15 @@ int sdhci_add_host(struct sdhci_host *host)
 
         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
 
+        if (host->version >= SDHCI_SPEC_300) {
+                init_waitqueue_head(&host->buf_ready_int);
+
+                /* Initialize re-tuning timer */
+                init_timer(&host->tuning_timer);
+                host->tuning_timer.data = (unsigned long)host;
+                host->tuning_timer.function = sdhci_tuning_timer;
+        }
+
         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
                 mmc_hostname(mmc), host);
         if (ret)
@@ -1999,6 +2807,8 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
         free_irq(host->irq, host);
 
         del_timer_sync(&host->timer);
+        if (host->version >= SDHCI_SPEC_300)
+                del_timer_sync(&host->tuning_timer);
 
         tasklet_kill(&host->card_tasklet);
         tasklet_kill(&host->finish_tasklet);